SWITCHED-CAPACITOR TECHNIQUES FOR HIGH-ACCURACY FILTER AND ADC DESIGN

Transcription

1 SWITCHED-CAPACITOR TECHNIQUES FOR HIGH-ACCURACY FILTER AND ADC DESIGN

2 QQ ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN-10: LOW-FREQUENCY NOISE IN ADVANCED MOS DEVICES Haartman, Martin v., Östling, Mikael ISBN-10: THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS Jespers, Paul G.A. ISBN-10: PRECISION TEMPERATURE SENSORS IN CMOS TECHNOLOGY Pertijs, Michiel A.P., Huijsing, Johan H. ISBN-10: X CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS Yuan, Fei ISBN: RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS Reynaert, Patrick, Steyaert, Michiel ISBN: IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN: ADVANCED DESIGN TECHNIQUES FOR RF POWER AMPLIFIERS Rudiakova, A.N., Krizhanovski, V. ISBN CMOS CASCADE SIGMA-DELTA MODULATORS FOR SENSORS AND TELECOM del Río, R., Medeiro, F., Pérez-Verdú, B., de la Rosa, J.M., Rodríguez-Vázquez, A. ISBN SIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONING Philips, K., van Roermund, A.H.M. Vol. 874, ISBN CALIBRATION TECHNIQUES IN NYQUIST A/D CONVERTERS van der Ploeg, H., Nauta, B. Vol. 873, ISBN ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIP Fayed, A., Ismail, M. Vol. 872, ISBN WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS Doris, Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES Pastre, Marc, Kayal, Maher Vol. 870, ISBN: HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: X DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifânio da Franca, José Vol. 867, ISBN: DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, José (Eds.) Vol. 860, ISBN: ANALOG DESIGN ESSENTIALS Sansen, Willy Vol. 859, ISBN: SWITCHED-CAPACITOR TECHNIQUES FOR HIGH-ACCURACY FILTER AND ADC DESIGN Patrick J. uinn, Arthur H.M. van Roermund ISBN:

3 Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design By PATRICK J. QUINN Xilinx, Dublin, Ireland and ARTHUR H.M. VAN ROERMUND Technical University of Eindhoven, The Netherlands

4 A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN (HB) ISBN (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. Printed on acid-free paper All Rights Reserved 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

5 To Siobhán

6 ABSTRACT Abstract In this book, switched-capacitor (SC) techniques are proposed which allow the attainment of higher intrinsic analogue accuracies than previously possible in such application areas as analogue filter and analogue-to-digital converter (ADC) design. The design philosophy is to create the required functionality without relying on trimming or digital calibration means but instead to develop methods which have reduced dependence on both component matching (especially capacitor matching) and parasitic effects (especially parasitic capacitance). At a system level, orthogonal design procedures are employed which ensure that artefacts due to expected circuit imperfections are avoided in the system transfer function. For instance, in SC filter design, orthogonal-hardware-modulation helps alleviate the effects of N- path mismatch through the introduction of an extra degree of freedom, where the number of hardware paths N (hardware modulation) is decoupled from the functional modulation factor n n, as introduced by the transformation zæ z. In algorithmic ADC design, both cyclic and pipelined, conventional techniques make use of multiplying digital-to-analogue converters (or MDACs) which require SC circuits with accurate capacitor ratios to implement accurate signal multiplication. On the other hand, in this book, the ADC function is decomposed into the simple sub-functions of signal addition and level shifting which can be implemented using SC techniques which don t rely on accurate capacitor ratios. ( d -Q) At circuit level, delta-charge flow techniques are employed to realize SC circuits with more accurate transfers than their conventional charge-transfer (QT) counterparts. Unlike QT SC circuits, d -Q SC circuits do not require signal charge transfer from capacitor to capacitor via the amplifier virtual earth node. Instead, only a delta charge d Q flows in the virtual earth node due to the presence of parasitic capacitors at the amplifier input terminals. In SC filter design, delta-charge-redistribution is a means for the accurate implementation of ( d -QR) filter transfer functions using passive charge redistribution between capacitors in the feedback path of an amplifier, instead of active charge transfer between capacitors through the active intervention of an amplifier in QT SC filters. In ADC design, a highly accurate method (C+C) for the stacking of capacitor voltages is proposed which uses a floating-hold-buffer for implementation. The accuracy of signal addition is practically insensitive to the matching and linearity of the signal capacitors as well as the presence of parasitic terminal capacitance. A number of other innovative circuit techniques have been included in the book, such as: a versatile accurate track-and-hold (T&H) which is re-programmable for unipolar, bipolar and vii

7 viii Abstract differential modes; clock-skew insensitive sampling; a common-mode-feedback circuit which significantly boosts the common-mode rejection ratio of single-ended amplifiers; high-efficiency dual-input transconductance amplifiers which make use of the level shift properties of switched capacitors; a low-reference dynamic comparator. The validity of the concepts developed and analyzed in the book has been demonstrated in practice with the design of CMOS SC bandpass filters and algorithmic ADC stages (both cyclic and pipelined). The intrinsic accuracies achieved go beyond those achieved with previous state-of-the-art solutions with a consequent reduction in power consumption for the same speed applications. For example, a 10.7MHz radio IF selectivity filter integrated in standard CMOS, employing the proposed methods, achieves an accuracy greater than ceramic filters. Another example is an ADC with better than 12-bit intrinsic performance, albeit capacitors with only 9-bits matching accuracy were used in the realization. The ADC architecture is also very robust and has proven itself in an embedded digital VLSI application in the very newest 65nm CMOS. The power consumptions and silicon areas of the solutions proposed here are lower than other known solutions from the literature.

8 CONTENTS Contents 1Abstract vii 3Symbols and Abbreviations xv Symbols xv Abbreviations xvii 1Chapter 1: Introduction Cost-Performance Trade-offs in IC Design Modern IC Design Challenges Digital IC Design Challenges Analogue IC Design Challenges Test Challenges Process and Design Work-Arounds Switched Capacitors for Analogue Signal Conditioning Key Points for High Performance SC Design Scope of Book Book Organization Chapter 2: Key Concepts for Accurate SC Design Orthogonal Design Procedures in Filter and ADC Realizations Delta Charge Flow SC Techniques The Sample-And-Hold Stage: Voltage Buffer The Delta-Charge-Redistribution Stage: Voltage Down-Scaler C+C Concept: Voltage Up-Scaler The Floating-Hold-Buffer Conclusions Chapter 3: SC Amplifier Design at Black-Box Level Amplifier Design Considerations ix

9 x Contents 3.2 The Settling Error Model Static Error Dynamic Error Design Procedure for Optimized Settling Single-Ended or Fully-Differential Capacitor Sizes OTA Architecture Choice of V on OTA Transconductance Matching Considerations Influence of Channel Mobility Factor Choice of Gate Lengths Minimum Settling Time Constant and Bias Current OTA Slewing Requirement in SC Applications The Slew Rate Model Minimum OTA Tail Current for No Slewing Calculation of Slew Time, tslew Dynamic Settling Error including OTA Slewing Conclusions Chapter 4: Amplifier Architectures for SC Applications Review of Amplifier Architectures Primary OTA Stages Telescopic OTA Current Mirror OTA Folded OTA General Conclusions for the Three Primary OTA Stages OTA Cascade Stages Pre-buffer Stage Pre-gain Stage Miller Output Stage Ahuja Output Stage The Dual-Input Telescopic OTA The SC Single-Input Telescopic OTA SC DITO Architectures Design Considerations Amplifier Noise Signal Range Cascode Frequency Response Design Issues The Effect of Cascoding on the Closed-Loop Settling Response Low Frequency Miller Multiplication Neutralization

10 Contents xi 4.4 Boosting the g m of a Cascode Stage using Active Feedback The RGC with High Frequency Design Considerations Reducing Low Frequency Miller Multiplication Low Voltage High Frequency RGC Architectures Suitability of RGCs for Low Voltage LV RGC using Level Shift Buffers LV RGC using Folded Cascode Voltage Sensing LV RGC using Dynamic Biasing OTA DC Gain Improvement using Partial Positive Feedback OTA Design Strategy Circuit Implementation of Partial Positive Feedback Optimization of SC Settling Response with Inclusion of Feedback Loop Switches Effect on Settling of Switch Resistance in OTA Feedback Loop Switch Design Strategy for Speed-up Conclusions Chapter 5: Low-Sensitivity SC BPF Concepts Sensitivity comparison of SC and CT Filters BPF Function Including Hardware Imperfections SC BPF Based on Modified N-Path Design Technique High-Q BPF Construction N-Path Design Issues Modified N-Path Technique using Orthogonal Hardware Modulation Delta Charge Redistribution (δ-qr) δ-qr for Filter Design δ-qr vs. QT SC Integrators δ-qr N-path SC BPFs QT SC BPF Via State-Of-The-Art Biquad Hybrid N-Path SC BPF (QT/δ-QR) δ-qr Type I N-path SC BPF (δ-qr-i) δ-qr Type II N-path SC BPF (δ-qr-ii) Performance Comparison of N-path SC BPF Stages Conclusions Chapter 6: High-Accuracy δ-qr SC BPF Design and Measurements SC Video BPF - the TV Cloche Filter System Level Considerations Design of SC Cloche Filter Circuitry Filter Architecture SC BPF Amplifier Common-Mode Feedback Chip Layout

11 xii Contents Measurement Results MHz SC Radio IF BPF System Context Design of Radio IF Filter Circuitry SC Filter Design Selectable Gain Control Track-and-Hold Amplifier Clock Layout Measurement Results Conclusions Appendix: Bandwidth Shrinkage of Cascaded Filter Stages Chapter 7: ADC Design at Black-Box Level ADC Black Box Representation Performance Specifications Static Error Specifications Offset and Gain Errors Differential Non-linearity (DNL) Integral Non-linearity (INL) Dynamic Error Specifications Signal-to-Noise Ratio (SNR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Intermodulation Distortion (IMD) Anti-Aliasing Pre-Filter Sampling Sampling Jitter Sample Clock Phase Noise Related to Allowable Sampling Jitter Sample Clock Noise Spectrum Quantization Quantization Noise Uniform coding model Long and short coding model Signal-to-Quantization Noise Ratios Quantizer Distortion Effective Bits ADC Conversion Efficiency Minimum SNR Limit Minimum Power Limits

12 Contents xiii Minimum Theoretical Power Limit Minimum Practical Power Limit for Class A Operation ADC Figures of Merit Conclusions Chapter 8: Design Criteria for Cyclic and Pipelined ADCs Operation of Cyclic and Pipelined ADCs The ADC Algorithm Digital Output Decoding Accuracy Limitations of Cyclic/Pipelined ADCs Lumped Error Model Limitations on Static Accuracy Offset Errors Capacitor Mismatch Gain Errors Amplifier Gain Errors Limitations on Dynamic Accuracy Linear and Non-linear Settling Constraints Thermal Noise Pipelined ADC Specific Design Issues Design Optimization of Multi-bit Input Stage Design Optimization of Scaled Pipelined ADCs Estimation of Static Power Consumption of Pipelined ADCs Conclusions Chapter 9: Capacitor Matching Insensitive High-Resolution Low-Power ADC Concept The ADC Algorithm Re-visited Review of SC Concepts for Analogue Addition The Floating-Hold-Buffer for Accurate Analogue Addition Implementation of C+C ADC Stage Practical Performance Issues Conclusions Chapter 10: High-Accuracy ADC Design and Measurements System Overview Application Space ADC Architecture Flexible ADC Sampling Modes Unipolar Mode Bipolar Mode Fully differential mode Proposed Reconfigurable Track-and-Hold

13 xiv Contents The T&H in Unipolar Mode The T&H in Bipolar and Differential Modes T&H Summary Proposed Cyclic ADC based on New Concept Proposed Single-ended OTA with High CMRR The CMFB Requirement in Single-ended OTAs A New Current CMFB for the Single-ended Current Mirror OTA Influence of Differential Transistor Mismatch on the OTA CMRR Experimental Verification Low-Reference Comparator Cyclic ADC Fabrication and Measurement Results Pipelined ADC Design Conclusions Main Conclusions Bibliography Index 241

14 SYMBOLS AND ABBREVIATIONS Symbols and Abbreviations Symbols A 0 B x C fb C in C L C L fix C Lsw C Leff C ox f s f sig g m L m Q QT r s S T t slew V REF V DD V on V ds(sat) Amplifier DC gain Spectral bandwidth of x, where x is RF, IF, or ch (channel) OTA external feedback capacitance OTA external input capacitance OTA external load capacitance Permanently connected amplifier external load capacitance including parasitics Switching amplifier load capacitance Effective load capacitance the amplifier sees at its output Gate capacitance per unit gate area Sampling frequency Signal frequency The small signal transconductance defined at the bias current Effective gate length of MOST Discrete time variable Quality factor Charge transfer (SC circuit), where signal charge is transferred completely from one capacitor to the other through the active intervention of an amplifier Pole radius in z-domain Laplace frequency variable Scaling factor Sampling period Slewing time Reference voltage Supply voltage The MOST on voltage, or gate over-drive voltage, defined as V GS - V T, required to keep the MOST biased at the edge of saturation with all voltages and currents fixed at their DC bias levels Defined as V gs - V T, it is the minimum instantaneous drain-source voltage required xv

15 xvi Symbols and Abbreviations to ensure the MOST stays in saturation V margin Extra voltage safety margin above V on to ensure MOST stays biased in saturation - generally, Vds( sat) < Von + Vmarg in v sat Maximum charge carrier velocity in silicon ( m s -1 ) VT ( V Threshold voltages for PMOSTs(NMOSTs) - note is assumed to be positive p T ) V n TP W Effective gate width of MOST X Y DC bias value of x, with y the descriptor - x is generally a current, i, or a voltage, v x y AC value of x with y a descriptor X y Total instantaneous value of x, where X y = X Y + x y z z-domain frequency variable β fb Closed loop amplifier feedback factor δ-q Delta charge flow technique referring to a new class of SC circuit δ-qr Delta charge redistribution Quantization step size of a data converter (analogue equivalent of 1 LSB) ε s Static settling error resulting mainly from finite amplifier DC gain ε d Dynamic settling error resulting mainly from finite amplifier bandwidth ε Total combined settling error of a SC circuit at the end of a clock period ϕ x Defines a clock phase x γ Attenuation factor due to capacitive division from the signal input of a SC circuit to the differential input of the OTA κ Ratio of OTA output parasitic capacitance to its input parasitic capacitance µ eff Effective inversion layer charge carrier mobility, including the effect of vertical field mobility degradation µ 0 Inversion layer charge carrier mobility, when low vertical field (typically, 5x10 10 µm 2 V -1 s -1 ) θ Process dependent factor inversely proportional to the oxide thickness (typically, 24 A o /d ox V -1 ) σ( X) Standard deviation of X τ Time constant of linear step response ω cl Closed loop bandwidth in radians/s ω ol Open loop bandwidth in radians/s ω T Radial transition frequency ω u Unity gain radial frequency, where the gain of the amplifier is reduced to 1 In parallel with (used for parallel combinations of resistors or capacitors)

16 Symbols and Abbreviations xvii Abbreviations ADC ASD ASIC ATE BIST BPF CAD CMFB CMOS CMRR DAC DEC DITO DNL DS ENOB FD FOM FPGA FS GBW HF HPF IC IF IMD I/O INL IP ITRS LF LHP LHS LPF LSB MDAC MOST MSB OHM Analogue-to-digital converter Analogue sampled data Application specific integrated circuit Automatic test equipment Built-in-self-test Bandpass filter Computer aided design Common mode feedback Complementary metal oxide semiconductor Common mode rejection ratio Digital-to-analogue converter Digital error correction Dual-input telescopic OTA Differential non-linearity Double sampling Effective number of bits Fully differential Figure of merit Field programmable gate array Full scale (of ADC) Gain-bandwidth (defined in radians per second) High frequency Highpass filter Integrated circuit Intermediate frequency Intermodulation distortion Input/output interface Integral non-linearity Intellectual property (block) International Roadmap for Semiconductors Low frequency Left half s-plane Left hand side Lowpass filter Least significant bit Multiplying DAC MOS transistor Most significant bit Orthogonal hardware modulation

17 xviii Symbols and Abbreviations OSR OTA PM PSRR PVT RF RGC RHP RHS RMS S&H SNR SC SE SEM SiP SITO SoC SR SS T&H VHF VLSI Oversampling ratio, f s /f sig Operational transconductance amplifier Phase margin (in degrees) Power supply rejection ratio Process, voltage supply and temperature variations Radio frequency Regulated cascode - this term is used interchangeably with the term active feedback cascode Right half s-plane Right hand side Root mean square Sample-and-hold Signal-to-noise ratio Switched-capacitor Single-ended Scanning electron microscope System in package Single-input telescopic OTA System-on-a-chip Slew rate Single sampling Track-and-hold Very high frequencies Very large scale integration