IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANSCEIVERS

Transcription

1 IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANSCEIVERS

2 ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Related Titles: asasdas CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS Yuan, Fei ISBN: ADVANCED DESIGN TECHNIQUES FOR RF POWER AMPLIFIERS Rudiakova, A.N., Krizhanovski, V. ISBN CMOS CASCADE SIGMA-DELTA MODULATORS FOR SENSORS AND TELECOM del Río, R., Medeiro, F., Pérez-Verdú, B., de la Rosa, J.M., Rodríguez-Vázquez, A. ISBN Titles in former series International Series in Engineering and Computer Science: SIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONING Philips, K., van Roermund, A.H.M. Vol. 874, ISBN CALIBRATION TECHNIQUES IN NYQUIST A/D CONVERTERS van der Ploeg, H., Nauta, B. Vol. 873, ISBN ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIP Fayed, A., Ismail, M. Vol. 872, ISBN WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS Doris, Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES Pastre, Marc, Kayal, Maher Vol. 870, ISBN: HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: X DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifânio da Franca, José Vol. 867, ISBN: DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, José (Eds.) Vol. 860, ISBN: ANALOG DESIGN ESSENTIALS Sansen, Willy Vol. 859, ISBN: DESIGN OF WIRELESS AUTONOMOUS DATALOGGER IC'S Claes and Sansen Vol. 854, ISBN: MATCHING PROPERTIES OF DEEP SUB-MICRON MOS TRANSISTORS Croon, Sansen, Maes Vol. 851, ISBN: LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS Leroux and Steyaert Vol. 843, ISBN: SYSTEMATIC MODELING AND ANALYSIS OF TELECOM FRONTENDS AND THEIR BUILDING BLOCKS Vanassche, Gielen, Sansen Vol. 842, ISBN: LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENT REDUCTION van der Meer, van Staveren, van Roermund Vol. 841, ISBN: VOLUME 595 WIDEBAND LOW NOISE AMPLIFIERS EXPLOITING THERMAL NOISE CANCELLATION Bruccoleri, Klumperink, Nauta Vol. 840, ISBN:

3 IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANSCEIVERS by Sao-Jie Chen National Taiwan University, Taipei, Taiwan and Yong-Hsiang Hsieh Muchip, Hsin-Chu, Taiwan

4 A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN (HB) ISBN (HB) ISBN (PB) ISBN (PB) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. Printed on acid-free paper All Rights Reserved 2006 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

5 Contents List of Figures List of Tables List of Abbreviations Preface Acknowledgments ix xiii xv xvii xix 1. INTRODUCTION 1 1. Wireless LAN Standards IEEE HiperLan HiperLan II OpenAir HomeRF and SWAP BlueTooth Wireless in the 21 st Century The 802 Standard and the IEEE IEEE b IEEE a IEEE g Performance and Characeristic 5 4. Background and Motivation 7 v

6 vi Contents 5. IEEE g RF Transceiver Performance Requirement Synthesizer Output Phase Noise Circuit Linearity Modulator/Demodulator I/Q Gain and Phase Imbalance 8 6 Transceiver Design Goal Solutions on I/Q Balance 9 2. TRANSCEIVER ARCHITECTURE DESIGN Receiver Architecture Superheterodyne Receiver Low-IF Receiver Zero-IF Receiver Comparison of Our Choice Transceiver Architecture The Choice of Intermediary Frequency Receiver Chain Link Budget Receiver Adjacent Channel Rejection Receiver Cascade Gain Receiver Cascade Noise Figure Receiver Dynamic Range RF/IF Section Gain Windows Receiver IF VGA and I/Q Demodulator Specification Cascade Gain of IF/BB Cascade Noise Figure of IF/BB Transmitter Chain Link Budget Transmit Circuits Gain Distribution and Gain Range Transmit Error Vector Magnitude Transmit Signal Spectral Mask I/Q MODULATOR AND DEMODULATOR DESIGN I/Q Modulator and Demodulator Architecture Overview Variable Gain Amplifier and Low-Pass Filter Re-use RX/TX Two-Mode Variable Gain Control Amplifier RX/TX Two-Mode Low-Pass Filter DC Offset Cancellation AN AUTO-I/Q CALIBRATED MODULATOR DC Offset, I/Q Gain and Phase Imbalance DC Offset, I/Q Gain and Phase Imbalance Auto-Calibration DC Offset Auto-Calibration I/Q Gain Imbalance Auto-Calibration I/Q Quadrature Phase Mismatch Auto-Calibration 61

7 Contents vii 2.4 Implementation of I/Q Auto-Calibration Circuitry TX I/Q Auto-Calibration Measurement Result AN AUTO-I/Q CALIBRATED DEMODULATOR Single Test Tone Design I/Q Gain Imbalance and Quadrature Phase Mismatch Auto-Calibration I/Q Gain Imbalance Auto-Calibration I/Q Quadrature Phase Mismatch Auto-Calibration Implementation of I/Q Auto-Calibration Circuitry RX I/Q Auto-Calibration Measurement Result SYSTEM MEASUREMENT RESULT Transmitter Measurement Result Receiver Measurement Result CONCLUSION 87 References 89

8 List of Figures 1-1 Expected a, b and g Data Rates at Varying Distance from Access Point Superheterodyne Receiver Architecture Problem Caused by Image Low-IF Receiver Architecture Zero-IF Receiver Architecture Effect of Even-Order Distortion on Interferers Transceiver in Receiver Mode Transceiver in Transmitter Mode The signal relative position Spurious Response Chart Spurious Response Chart with three Different Regions PCB Network from Antenna to Transceiver I/O Simplified Receiver Architecture Input Power versus I/Q Output SNR when RF/IF has two Gain Modes Input Power Versus I/Q Output SNR when RF/IF has Three Gain Modes Cascade Noise Figure Requirement of IF VGA and I/Q Demodulator Simplified Transmitter Architecture Simplified Architecture of RX VGA and I/Q Demodulator Simplified Architecture of I/Q Modulator and TX VGA VGA Cell Design: (a) from [17] and (b) the Proposed Architecture 46 ix

9 x List of Figures 3-4 RX/TX Two-Mode Variable Gain Control Amplifier (VGA) Architecture RX/TX Two-mode Gain Control Circuit RX/TX Two-Mode Third-Order Bessel Low-Pass Filter OTA Cell with two Differential Pairs for RX Input and TX Input Offset Cancellation by (a) Capacitive Coupling, (b) Negative Feedback, and (c) the Proposed Single end Feedback Structure DC Offset Cancellation Loop with Two Different Loop Bandwidths An Illustration on the Error Vector and its Components Circuits Non-ideal Effects on Constellation caused by: (a) DC Offset, (b) I/Q Gain imbalance, and (c) Quadrature Phase Mismatch Auto-I/Q Calibration Flow Chart Transceiver Block Diagram in Modulator I/Q Calibration Simplified Modulator I/Q Calibration Signal Path Flow Chart of Modulator Auto DC Offset Cancellation Flow Chart of Modulator Auto I/Q Gain Imbalance Calibration Flow Chart of Modulator Auto Quadrature Phase Mismatch Calibration Architecture of S/C Comparator Simplified Circuit of a Delay Cell Simplified Circuit of TX input Buffer with Gain and DC Offset Tuning Test Environment Setup for I/Q Auto-Calibration on a TX Modulator Measurement Result of TX DC Offset Auto-Calibration Measurement Results of TX I/Q Gain Imbalance Auto-Calibration: (a) the Whole Calibration Process and (b) the Zoom-in of (a) TX Modulator Single Side-Band Rejection Test Transceiver Block Diagram in Demodulator I/Q Calibration Mode Block Diagram of RX Detector and Comparator in Gain Calibration Mode Flow Chart of Demodulator Auto I/Q Gain Imbalance Cancellation Block Diagram of RX Detector and Comparator in Phase Calibration Mode Flow Chart of Demodulator Auto I/Q Phase Mismatch Cancellation 75

10 List of Figures xi 5-6 Measurement Result of RX I/Q Gain Imbalance Auto-Calibration Measurement Result of Quadrature Phase Mismatch Auto-Calibration Die Micrograph AC Characteristic Test Board IF Output Power vs VGA Control Voltage Phase Noise Plot RF Output Spectrum Mask Constellation in a g 54Mbps Data Rate Mode RF/IF Section Cascade Noise Figure and Gain Cascade Gain of IF VGA and Demodulator under Different VGA Control Voltages RX I and Q Output Voltage Swings (Less than 1 Quadrature Phase Error and 0.1dB Gain Imbalance) RX Output SNR vs RF Input Power 85

11 List of Tables 1-1 IEEE Specifications WLAN User Requirements and Technology Characteristics in the U.S. [2] Comparison of Receiver Architectures Adjacent Channel Rejection Requirement Receive Sensitivity Requirement RX Chain Cascade Noise Figure under Different RF/IF Section Gain Calculation Result of Important Parameters under Different Input Power Receive FE Specification in Two-Gain Windows Receive FE specification in Three-Gain Windows Transmitter Performance Summary Receiver Performance Summary 86 xiii

12 List of Abbreviations A/D AFC AGC AP BB BW CCK DAC DSSS ETSI EVM FE FSK HPF I IF IL LAN LNA LO LPF OFDM PA PAPR PCB PER Analog-to-Digital Converter Automatic Frequency Control Auto Gain Control Access Point Baseband Bandwidth Complementary Code Keying Digital-to-Analog Converter Direct Sequence Spread Spectrum European Telecommunications Standards Institute Error Vector Amplitude Front-End Frequency-Shift Keying High Pass Filter In-phase Intermediate Frequency Insertion Loss Local Area Network Low Noise Amplifier Local Oscillator Low Pass Filter Orthogonal Frequency Division Multiplexing Power Amplifier Peak to Average Power Ratio Print Circuit Board Package Error Ratio xv

13 xvi PLL Q QAM QPSK RF RX S/C SAW SNR SoC SSB SWAP TDD TX VCO VGA WiFi WLIF List of Abbreviations Phase Lock Loop Quadrature Quadrature Amplitude Modulation Quadrature Phase Shift Keying Radio Frequency Receiver Sample and Compare Surface Acoustic Wave Signal-to-Noise Ratio System-on-Chip Single Side Band Semantic Web Application Platform Time-Division-Duplex Transmitter Voltage Control Oscillator Variable Gain control Amplifier Wireless Fidelity Wireless LAN Interoperability Forum

14 Preface In the market of wireless communication, high data-rate transmission and high spectral efficiency have been the trend. The IEEE a/g standards working at 5GHz/2.4GHz ISM bands can support data rates up to 54Mbits/s using OFDM modulation. The newly proposed n technology now uses 64-QAM to achieve higher spectral efficiency. The DVB and many other systems will also use QAM for its data transmission. The cost of achieving this higher spectral efficiency using higher order QAM is that the transmitter and receiver requires a higher signal to noise ratio (SNR) in order to modulate and demodulate the signal with the same level of error rate performance (relative to a baseline BPSK or QPSK system). The dominant vectors on SNR degradation are noise floor, signal distortion, down conversion (up conversion for transmitter) local phase noise and the modulator/demodulator I/Q gains and phases imbalance. There are a lot of vectors that degrade the matching of gains and phases between I/Q signals: the instinct layout mismatch, the random mismatch of the devices, the different temperature over the I/Q signal paths, etc. Solutions on I/Q gains and phases mismatch compensation can be classified into three schools. The first school uses a fully-digital compensation technique. For example, Eberle et al. [5] presented a digital compensation architecture for the I/Q mismatch problem that occurred in a digital receiver. The second one uses baseband plus RF front-end to calibrate the gain and phase mismatch. For example, baseband signal processing techniques have been used to generate a test signal to the RF front-end [6, 7]. Since the output of the RF front-end running this test signal will give information on the I/Q mismatch, the baseband can sense this output to determine a control code for the front-end circuits to compensate the I/Q mismatch. But most of xvii

15 xviii Preface the academic institutes and even business have limited man-power to develop an RF front-end plus a baseband IC for compensation purposes. The third one uses a fully-analog compensation technique without baseband circuitry to control the calibration process. For example, Hsieh et al. [9] first presented an auto-i/q calibrated transceiver with no more than 5% hardware overhead for the calibration circuitry. This book will use an g transceiver design as an example to give a detail description on the I/Q gains and phases imbalance auto-calibration mechanism. The first part of this work discusses the reasons on why we would like to design an g transceiver and the architecture of the transceiver. We decide to use a superheterodyne architecture for the transceiver with the baseband filters and to re-use the IF Variable Gain Control (VGA) in both modulator and demodulator to reduce the chip size. System link budget calculation has also been showed on this part. The second part include Chapters 4 and 5. The DC offset cancellation in modulator, and the I/Q gains and phases imbalance auto-calibration in both modulator and demodulator are discussed on this part. The final chapters illustrate the chip measured result. Sao-Jie Chen Graduate Institute of Electronics Engineering and Department of Electrical Engineering National Taiwan University Taipei, Taiwan, 2006 Yong-Hsiang Hsieh RF IC Product Design Department Muchip Hsin-Chu, Taiwan, 2006

16 Acknowledgments Many persons contributed to development of this book. First, Dr Syed K. Enam, and Dr David-J Chen are acknowledged for their valuable inputs to the circuits and architecture. The circuits described in the text were realized in close cooperation with the graduate students from Prof. Sao-Jie Chen s research group and with colleagues from Muchip. In particular, we want to express our appreciation to the following persons: Dennis Cheng, Wei-Yi Hu, Shin-Ming Lin, Chao-Liang Chen, Wen-Kai Li for their contributions to the work described in the text. Finally, we would like to thank our parents and our wives. Sao-Jie Chen Graduate Institute of Electronics Engineering and Department of Electrical Engineering National Taiwan University Taipei, Taiwan, 2006 Yong-Hsiang Hsieh RF IC Product Design Department Muchip Hsin-Chu, Taiwan, 2006 xix