ICM7555, ICM7556. General Purpose Timers. Features. Applications. Pinouts ICM7555 (8 LD PDIP, SOIC) TOP VIEW. Data Sheet August 24, 2006 FN2867.

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1 ICM7555, ICM755 Data Sheet F7.9 General Purpose Timers The ICM7555 and ICM755 are CMOS RC timers providing significantly improved performance over the standard SE/E 555/ and 355 timers, while at the same time being direct replacements for those devices in most applications. Improved parameters include low supply current, wide operating supply voltage range, low THRESHOLD, and currents, no crowbarring of the supply current during output transitions, higher frequency performance and no requirement to decouple COTROL for stable operation. Specifically, the ICM7555 and ICM755 are stable controllers capable of producing accurate time delays or frequencies. The ICM755 is a dual ICM7555, with the two timers operating independently of each other, sharing only V+ and GD. In the one shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled by two external resistors and one capacitor. Unlike the regular bipolar SE/E 555/ devices, the COTROL terminal need not be decoupled with a capacitor. The circuits are triggered and reset on falling (negative) waveforms, and the output inverter can source or sink currents large enough to drive TTL loads, or provide minimal offsets to drive CMOS loads. Features Exact Equivalent in Most Cases for SE/E555/55 or TLC555/55 Low Supply Current - ICM μa - ICM μa Extremely Low Input Currents pa High Speed Operation MHz Guaranteed Supply Voltage Range V to V Temperature Stability %/ C at +5 C ormal Reset Function - o Crowbarring of Supply During Output Transition Can be Used with Higher Impedance Timing Elements than Regular 555/ for Longer RC Time Constants Timing from Microseconds through Hours Operates in Both Astable and Monostable Modes Adjustable Duty Cycle High Output Source/Sink Driver can Drive TTL/CMOS Outputs have Very Low Offsets, HI and LO Pb-Free Plus Anneal Available (RoHS Compliant) Applications Precision Timing Pulse Generation Sequential Timing Time Delay Generation Pulse Width Modulation Pulse Position Modulation Missing Pulse Detector Pinouts ICM7555 ( LD PDIP, SOIC) TOP VIEW ICM755 ( LD PDIP, CERDIP) TOP VIEW DISCHARGE GD 3 7 DISCHARGE THRESHOLD 5 COTROL THRESH- OLD COTROL DISCHARGE THRESHOLD COTROL 9 GD 7 CAUTIO: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. --ITERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc.,, 5,. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Ordering Information PART UMBER PART MARKIG TEMP. RAGE ( C) PACKAGE PKG. DWG. # ICM7555CBA 7555 CBA to +7 Ld SOIC M.5 ICM7555CBA-T 7555 CBA to +7 Ld SOIC Tape and Reel M.5 ICM7555CBAZ (ote) 7555 CBAZ to +7 Ld SOIC (Pb-free) M.5 ICM7555CBAZ-T (ote) 7555 CBAZ to +7 Ld SOIC (Pb-free) Tape and Reel M.5 ICM7555IBA 7555 IBA -5 to +5 Ld SOIC M.5 ICM7555IBAT 7555 IBA -5 to +5 Ld SOIC Tape and Reel M.5 ICM7555IBAZ (ote) 7555 IBAZ -5 to +5 Ld SOIC (Pb-free) M.5 ICM7555IBAZ-T (ote) 7555 IBAZ -5 to +5 Ld SOIC (Pb-free) Tape and Reel M.5 ICM7555IPA 7555 IPA -5 to +5 Ld PDIP E.3 ICM7555IPAZ (ote) 7555 IPAZ -5 to +5 Ld PDIP** (Pb-free) E.3 ICM755IPD ICM755IPD -5 to +5 Ld PDIP E.3 ICM755IPDZ (ote) ICM755IPDZ -5 to +5 Ld PDIP** (Pb-free) E.3 ICM755MJD ICM755MJD -55 to +5 Ld Cerdip F.3 **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. OTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. F7.9

3 Absolute Maximum Ratings Supply Voltage V Input Voltage Trigger, Control Voltage, Threshold, Reset (ote ) V+ +.3V to GD -.3V Output Current ma Operating Conditions Temperature Range ICM7555C C to +7 C ICM7555I, ICM755I C to +5 C ICM755M C to +5 C Thermal Information Thermal Resistance (Typical, ote ) θ JA ( C/W) θ JC ( C/W) Lead CERDIP Package Lead PDIP Package* /A Lead PDIP Package* /A Lead SOIC Package /A Maximum Junction Temperature (Hermetic Package) C Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to +5 C Maximum Lead Temperature (Soldering s) C (SOIC - Lead Tips Only) * Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTIO: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. OTES:. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +.3V or less than V- -.3V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply of the ICM7555 and ICM755 must be turned on first.. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details. Electrical Specifications Applies to ICM7555 and ICM755, unless otherwise specified T A = +5 C (OTE ) -55 C TO +5 C PARAMETER SYMBOL TEST CODITIOS MI TYP MAX MI TYP MAX UITS Static Supply Current I DD ICM7555 = 5V 3 μa = 5V 3 3 μa ICM755 = 5V μa = 5V μa Monostable Timing Accuracy R A = K, C =.μf, = 5V % 5 μs Drift with Temperature (ote 3) = 5V 5 ppm/ C = V ppm/ C = 5V 5 ppm/ C Drift with Supply (ote 3) = 5V to 5V.5.5 %/V Astable Timing Accuracy R A = R B = K, C =.μf, = 5V % μs Drift with Temperature (ote 3) = 5V 5 ppm/ C = V ppm/ C = 5V 5 ppm/ C Drift with Supply (ote 3) = 5V to 5V.5.5 %/V Threshold Voltage V TH = 5V % Trigger Voltage V TRIG = 5V % Trigger Current I TRIG = 5V 5 na Threshold Current I TH = 5V 5 na Control Voltage V CV = 5V % 3 F7.9

4 Electrical Specifications Applies to ICM7555 and ICM755, unless otherwise specified (Continued) T A = +5 C (OTE ) -55 C TO +5 C PARAMETER SYMBOL TEST CODITIOS MI TYP MAX MI TYP MAX UITS Reset Voltage V RST = V to 5V.... V Reset Current I RST = 5V 5 na Discharge Leakage I DIS = 5V 5 na Output Voltage V OL = 5V, I SIK = ma...5 V = 5V, I SIK = 3.mA...5 V V OH = 5V, I SOURCE =.ma.3.. V = 5V, I SOURCE =.ma V Discharge Output Voltage V DIS = 5V, I SIK = 5mA... V = 5V, I SIK = 5mA. V Supply Voltage (ote 3) Functional Operation V Output Rise Time (ote 3) t R R L = M, C L = pf, = 5V 75 ns Output Fall Time (ote 3) t F R L = M, C L = pf, = 5V 75 ns Oscillator Frequency (ote 3) f MAX = 5V, R A = 7Ω, R B = 7Ω, C = pf MHz OTES: 3. These parameters are based upon characterization data and are not tested.. Applies only to military temperature range product (M suffix). Functional Diagram THRESHOLD 5 COTROL R COMPARATOR A + R - FLIP-FLOP 7 DRIVERS 3 DISCHARGE + - n R COMPARATOR B GD OTE: This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs. TRUTH TABLE THRESHOLD DISCHARGE SWITCH Don t Care Don t Care Low Low On > / 3 (V+) > / 3 (V+) High Low On < / 3 (V+) > / 3 (V+) High Stable Stable Don t Care < / 3 (V+) High High Off OTE: will dominate all other inputs: will dominate over THRESHOLD. F7.9

5 Schematic Diagram P P R P P THRESHOLD P COTROL R P P R DISCHARGE GD R = kω ±% (TYP) Application Information General The ICM7555 and ICM755 devices are, in most instances, direct replacements for the E/SE 555/ devices. However, it is possible to effect economies in the external component count using the ICM7555 and ICM755. Because the bipolar E/SE 555/ devices produce large crowbar currents in the output driver, it is necessary to decouple the power supply lines with a good capacitor close to the device. The ICM7555 and ICM755 devices produce no such transients. See Figure. SUPPLY CURRET (ma) 5 3 SE/E555 ICM7555/5 TIME (ns) The ICM7555 and ICM755 produce supply current spikes of only ma - 3mA instead of 3mA - ma and supply decoupling is normally not necessary. Also, in most instances, the COTROL decoupling capacitors are not required since the input impedance of the CMOS comparators on chip are very high. Thus, for many applications, two capacitors can be saved using an ICM7555 and three capacitors with an ICM755. POWER SUPPLY COSIDERATIOS Although the supply current consumed by the ICM7555 and ICM755 devices is very low, the total system supply current can be high unless the timing components are high impedance. Therefore, use high values for R and low values for C in Figures A, B, and 3. R GD DISCHARGE THRESHOLD FIGURE A. ASTABLE OPERATIO C K COTROL OPTIOAL CAPACITOR ALTERATE FIGURE. SUPPLY CURRET TRASIET COMPARED WITH A STADARD BIPOLAR 555 DURIG A TRASITIO 5 F7.9

6 R A t = -ln (/3) R A C =.R A C R B 3 ICM R A DISCHARGE THRESHOLD COTROL C OPTIOAL CAPACITOR FIGURE B. ALTERATE ASTABLE COFIGURATIO V OPTIOAL CAPACITOR FIGURE 3. MOOSTABLE OPERATIO C DRIVE CAPABILITY The output driver consists of a CMOS inverter capable of driving most logic families including CMOS and TTL. As such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of.5v or more, the ICM7555 and ICM755 will drive at least two standard TTL loads. ASTABLE OPERATIO The circuit can be connected to trigger itself and free run as a multivibrator, see Figure A. The output swings from rail to rail, and is a true 5% duty cycle square wave. (Trip points and output swings are symmetrical.) Less than a % frequency variation is observed over a voltage range of +5V to +5V. f = RC (EQ. ) The timer can also be connected as shown in Figure B. In this circuit, the frequency is: f =. ( R A + R B ) C (EQ. ) The duty cycle is controlled by the values of R A and R B, by the equation: D = ( R A + R B ) ( R A + R B ) (EQ. 3) COTROL The COTROL terminal permits the two trip voltages for the THRESHOLD and internal comparators to be controlled. This provides the possibility of oscillation frequency modulation in the astable mode or even inhibition of oscillation, depending on the applied voltage. In the monostable mode, delay times can be changed by varying the applied voltage to the COTROL pin. The terminal is designed to have essentially the same trip voltage as the standard bipolar 555/, i.e.,.v to.7v. At all supply voltages it represents an extremely high input impedance. The mode of operation of the function is, however, much improved over the standard bipolar E/SE 555/ in that it controls only the internal flipflop, which in turn controls simultaneously the state of the and DISCHARGE pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices. MOOSTABLE OPERATIO In this mode of operation, the timer functions as a one-shot. See Figure 3. Initially the external capacitor (C) is held discharged by a transistor inside the timer. Upon application of a negative pulse to pin, the internal flip-flop is set which releases the short circuit across the external capacitor and drives the high. The voltage across the capacitor now increases exponentially with a time constant t = R A C. When the voltage across the capacitor equals / 3 V+, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly and also drives the to its low state. must return to a high state before the can return to a low state. F7.9

7 Typical Performance Curves MIIMUM PULSE WIDTH (ns) = V = 5V = V 3 LOWEST LEVEL OF PULSE (% ) SUPPLY CURRET (ICM7555) (μa) 3 3 T A = - C T A = 7 C SUPPLY (V) SUPPLY CURRET (ICM755) (μa) FIGURE. MIIMUM PULSE WIDTH REQUIRED FOR IG FIGURE 5. SUPPLY CURRET vs SUPPLY SOURCE CURRET (ma) = V = 5V = V SIK CURRET (ma).. T A = - C = V = V = 5V REFERECED TO (V) LOW (V) FIGURE. SOURCE CURRET vs FIGURE 7. SIK CURRET vs T A = 7 C SIK CURRET (ma).. = V = V = 5V SIK CURRET (ma).. = V = V = 5V..... LOW (V) FIGURE. SIK CURRET vs..... LOW (V) FIGURE 9. SIK CURRET vs 7 F7.9

8 Typical Performance Curves (Continued) ORMALIZED FREQUECY DEVIATIO (%) R A = R B = kω C =.μf R A = R B = MΩ C = pf.... SUPPLY (V) FIGURE. ORMALIZED FREQUECY STABILITY I THE ASTABLE MODE vs SUPPLY PROPAGATIO DELAY (ns) 5 3 = 5V T A = 7 C T A = - C 3 LOWEST LEVEL OF PULSE (% ) FIGURE. PROPAGATIO DELAY vs LEVEL OF PULSE CAPACITACE (F). m m m μ μ μ n n n p p (R A + R B ) kω kω kω MΩ MΩ MΩ p. k k k M M FREQUECY (Hz) FIGURE. FREE RUIG FREQUECY vs R A, R B AD C DISCHARGE SIK CURRET (ma).. = V = V = 5V..... DISCHARGE LOW (V) FIGURE. DISCHARGE CURRET vs DISCHARGE ORMALIZED FREQUECY DEVIATIO (%) R A = R B = kω C =.μf = V = 5V = V TEMPERATURE ( C) = V FIGURE 3. ORMALIZED FREQUECY STABILITY I THE ASTABLE MODE vs TEMPERATURE CAPACITACE (F). m m m μ μ μ n n n p p kω kω kω MΩ MΩ MΩ p n μ μ μ m m m TIME DELAY (s) FIGURE 5. TIME DELAY I THE MOOSTABLE MODE vs R A AD C R A F7.9

9 Small Outline Plastic Packages (SOIC) ICM7555, ICM755 IDEX AREA 3 e D B.5(.) M C A M E -B- -A- -C- SEATIG PLAE A B S H.5(.) M B A α.(.) L M h x 5 OTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication umber 95.. Dimensioning and tolerancing per ASI Y.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (. inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured.3mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M.5 (JEDEC MS--AA ISSUE C) LEAD ARROW BODY SMALL OUTLIE PLASTIC PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A B C D E e.5 BSC.7 BSC - H h L α - Rev. /5 9 F7.9

10 Dual-In-Line Plastic Packages (PDIP) ICM7555, ICM755 IDEX AREA BASE PLAE SEATIG PLAE D B -C- -A- 3 / B D e D E -B- A. (.5) M C A A L B S OTES:. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ASI Y.5M Symbols are defined in the MO Series Symbol List in Section. of Publication o Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.5mm). 9. is the maximum number of terminal positions.. Corner leads (,, / and / + ) for E.3, E.3, E.3, E.3, E. will have a B dimension of inch (.7 -.mm). A e C E C L e A C e B E.3 (JEDEC MS--BA ISSUE D) LEAD DUAL-I-LIE PLASTIC PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A A B B , C D D E E e. BSC.5 BSC - e A.3 BSC 7. BSC e B L Rev. /93 F7.9

11 Dual-In-Line Plastic Packages (PDIP) ICM7555, ICM755 IDEX AREA BASE PLAE SEATIG PLAE D B -C- -A- 3 / B D e D E OTES:. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ASI Y.5M Symbols are defined in the MO Series Symbol List in Section. of Publication o Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.5mm). 9. is the maximum number of terminal positions.. Corner leads (,, / and / + ) for E.3, E.3, E.3, E.3, E. will have a B dimension of inch (.7 -.mm). -B- A. (.5) M C A A L B S A e C E C L e A C e B E.3 (JEDEC MS--AA ISSUE D) LEAD DUAL-I-LIE PLASTIC PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A A B B C D D E E e. BSC.5 BSC - e A.3 BSC 7. BSC e B L Rev. /93 F7.9

12 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLAE SEATIG PLAE S b ccc M bbb S b C A - B C A - B S D A A e D S OTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (,, /, and /+) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b. 5. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S at all four corners.. is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ASI Y.5M Controlling dimension: ICH. E L M c ea/ S D S aaa M C A - B LEAD FIISH BASE METAL b M (b) SECTIO A-A -D- -A- Q -C- A -Bα S ea c D S (c) F.3 MIL-STD-35 GDIP-T (D-, COFIGURATIO A) LEAD CERAMIC DUAL-I-LIE FRIT SEAL PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A b...3. b b b c.... c D E e. BSC.5 BSC - ea.3 BSC 7. BSC - ea/.5 BSC 3. BSC - L Q S α aaa bbb ccc M , 3 Rev. /9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. o license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see F7.9

DATASHEET. Features. Applications. Pin Configurations ICM7555 (8 LD PDIP, SOIC) TOP VIEW ICM7555, ICM7556. General Purpose Timers

DATASHEET. Features. Applications. Pin Configurations ICM7555 (8 LD PDIP, SOIC) TOP VIEW ICM7555, ICM7556. General Purpose Timers DATASHEET ICM555, ICM55 General Purpose Timers The ICM555 and ICM55 are CMOS RC timers providing significantly improved performance over the standard SE/E 555/55 and 55 timers, while at the same time being