DATASHEET. Features. Applications. Pin Configurations ICM7555 (8 LD PDIP, SOIC) TOP VIEW ICM7555, ICM7556. General Purpose Timers

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1 DATASHEET ICM555, ICM55 General Purpose Timers The ICM555 and ICM55 are CMOS RC timers providing significantly improved performance over the standard SE/E 555/55 and 55 timers, while at the same time being direct replacements for those devices in most applications. Improved parameters include low supply current, wide operating supply voltage range, low Threshold, Trigger and Reset currents, no crowbarring of the supply current during output transitions, higher frequency performance and no requirement to decouple Control Voltage for stable operation. Specifically, the ICM555 and ICM55 are stable controllers capable of producing accurate time delays or frequencies. The ICM55 is a dual ICM555, with the two timers operating independently of each other, sharing only V+ and GD. In the one shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled by two external resistors and one capacitor. Unlike the regular bipolar SE/E 555/55 devices, the Control Voltage terminal need not be decoupled with a capacitor. The circuits are triggered and reset on falling (negative) waveforms, and the output inverter can source or sink currents large enough to drive TTL loads, or provide minimal offsets to drive CMOS loads. Pin Configurations ICM555 ( LD PDIP, SOIC) TOP VIEW Features F Rev. Exact equivalent in most cases for SE/E 555/55 or TLC555/55 Low supply current - ICM µa - ICM µa Extremely low input currents pa High speed operation MHz Guaranteed supply voltage range V to V Temperature stability %/ C at +5 C ormal reset function - no crowbarring of supply during output transition Can be used with higher impedance timing elements than regular 555/55 for longer RC time constants Timing from microseconds through hours Operates in both astable and monostable modes Adjustable duty cycle High output source/sink driver can drive TTL/CMOS Outputs have very low offsets, HIGH and LOW Pb-free (RoHS Compliant) Applications Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation Pulse position modulation Missing pulse detector ICM55 ( LD PDIP, CERDIP) TOP VIEW DISCHARGE GD TRIGGER RESET DISCHARGE THRESHOLD 5 COTROL VOLTAGE THRESHOLD COTROL VOLTAGE RESET 5 TRIGGER DISCHARGE THRESHOLD COTROL VOLTAGE RESET 9 GD TRIGGER F Rev. Page of

2 Ordering Information PART UMBER PART MARKIG TEMP. RAGE ( C) TAPE AD REEL (UITS) PACKAGE (RoHS COMPLIAT) PKG. DWG. # ICM555CBAZ (otes, ) 555 CBAZ to + Ld SOIC M.5 ICM555CBAZ-T (otes,, ) 555 CBAZ to +.5k Ld SOIC (Tape and Reel) M.5 ICM555IBAZ (otes, ) 555 IBAZ -5 to +5 Ld SOIC M.5 ICM555IBAZ-T (otes,, ) 555 IBAZ -5 to +5.5k Ld SOIC (Tape and Reel) M.5 ICM555IPAZ (otes, ) 555 IPAZ -5 to +5 Ld PDIP E. ICM55IPDZ (otes, ) ICM55IPDZ -5 to +5 Ld PDIP E. ICM55MJD (o longer available or supported) ICM55MJD -55 to +5 Ld Cerdip F. OTES:. Please refer to TB for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. For Moisture Sensitivity Level (MSL), please see product information page for ICM555, ICM55. For more information on MSL, please see tech brief TB. F Rev. Page of

3 Absolute Maximum Ratings Supply Voltage V Input Voltage Trigger, Control Voltage, Threshold, Reset (ote ) V+ +.V to GD -.V Output Current ma Operating Conditions Temperature Range ICM555C C to + C ICM555I, ICM55I C to +5 C ICM55M C to +5 C Thermal Information Thermal Resistance (Typical, otes 5, ) JA ( C/W) JC ( C/W) Ld CERDIP Package Ld PDIP Package* Ld PDIP Package* Ld SOIC Package Maximum Junction Temperature (Hermetic Package) C Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to +5 C * Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTIO: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. OTES:. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +.V or less than V- -.V may cause destructive latch-up. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply of the ICM555 and ICM55 must be turned on first. 5. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB9 for details.. For JC, the case temp location is taken at the package top center. Electrical Specifications Applies to ICM555 and ICM55, unless otherwise specified. (ote ) -55 C TO +5 C PARAMETER SYMBOL TEST CODITIOS MI TYP MAX MI TYP MAX UIT Static Supply Current I DD ICM555 = 5V µa = 5V µa ICM55 = 5V µa = 5V µa Monostable Timing Accuracy R A = k, C =.µf, = 5V % 5 µs Drift with Temperature (ote ) = 5V 5 ppm/ C = V ppm/ C = 5V 5 ppm/ C Drift with Supply (ote ) = 5V to 5V.5.5 %/V Astable Timing Accuracy R A = R B = k, C =.µf, = 5V % µs Drift with Temperature (ote ) = 5V 5 ppm/ C = V ppm/ C = 5V 5 ppm/ C Drift with Supply (ote ) = 5V to 5V.5.5 %/V Threshold Voltage V TH = 5V % Trigger Voltage V TRIG = 5V % Trigger Current I TRIG = 5V 5 na Threshold Current I TH = 5V 5 na Control Voltage V CV = 5V % F Rev. Page of

4 Electrical Specifications Applies to ICM555 and ICM55, unless otherwise specified. (Continued) (ote ) -55 C TO +5 C PARAMETER SYMBOL TEST CODITIOS MI TYP MAX MI TYP MAX UIT Reset Voltage V RST = V to 5V.... V Reset Current I RST = 5V 5 na Discharge Leakage I DIS = 5V 5 na Output Voltage V OL = 5V, I SIK = ma...5 V = 5V, I SIK =.ma...5 V V OH = 5V, I SOURCE =.ma... V = 5V, I SOURCE =.ma... V Discharge Output Voltage V DIS = 5V, I SIK = 5mA... V = 5V, I SIK = 5mA. V Supply Voltage (ote ) Functional Operation.... V Output Rise Time (ote ) t R R L = M, C L = pf, = 5V 5 ns Output Fall Time (ote ) t F R L = M, C L = pf, = 5V 5 ns Oscillator Frequency (ote ) f MAX = 5V, R A = Ω, R B = Ω, C = pf MHz OTES:. These parameters are based upon characterization data and are not tested.. Applies only to military temperature range product (M suffix). Functional Diagram THRESHOLD 5 COTROL VOLTAGE R COMPARATOR A + R - FLIP-FLOP RESET DRIVERS DISCHARGE TRIGGER + - n OTE: R COMPARATOR B GD This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs. FIGURE. FUCTIOAL DIAGRAM TRUTH TABLE THRESHOLD VOLTAGE TRIGGER VOLTAGE RESET DISCHARGE SWITCH Don t Care Don t Care Low Low On > / (V+) > / (V+) High Low On < / (V+) > / (V+) High Stable Stable Don t Care < / (V+) High High Off OTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD. F Rev. Page of

5 Schematic Diagram P P R P P THRESHOLD P COTROL VOLTAGE R TRIGGER P P R R = kω ±% (TYP) RESET DISCHARGE GD FIGURE. SCHEMATIC DIAGRAM Application Information General The ICM555 and ICM55 devices are, in most instances, direct replacements for the SE/E 555/55 devices. However, it is possible to effect economies in the external component count using the ICM555 and ICM55. Because the bipolar SE/E 555/55 devices produce large crowbar currents in the output driver, it is necessary to decouple the power supply lines with a good capacitor close to the device. The ICM555 and ICM55 devices produce no such transients (see Figure ). SUPPLY CURRET (ma) 5 SE/E 555 ICM555/55 The ICM555 and ICM55 produce supply current spikes of only ma to ma instead of ma to ma and supply decoupling is normally not necessary. Also, in most instances, the Control Voltage decoupling capacitors are not required since the input impedance of the CMOS comparators on chip are very high. Thus, for many applications, two capacitors can be saved using an ICM555 and three capacitors with an ICM55. POWER SUPPLY COSIDERATIOS Although the supply current consumed by the ICM555 and ICM55 devices is very low, the total system supply current can be high unless the timing components are high impedance. Therefore, use high values for R and low values for C in Figures, 5, and. R GD TRIGGER RESET 5 DISCHARGE THRESHOLD C k COTROL VOLTAGE OPTIOAL CAPACITOR ALTERATE TIME (ns) FIGURE. ASTABLE OPERATIO FIGURE. SUPPLY CURRET TRASIET COMPARED WITH A STADARD BIPOLAR 555 DURIG A TRASITIO F Rev. Page 5 of

6 R A t = -ln (/) R A C =.R A C 5 R B TRIGGER RESET ICM555 5 R A DISCHARGE THRESHOLD COTROL VOLTAGE C OPTIOAL CAPACITOR FIGURE 5. ALTERATE ASTABLE COFIGURATIO V OPTIOAL CAPACITOR FIGURE. MOOSTABLE OPERATIO C DRIVE CAPABILITY The output driver consists of a CMOS inverter capable of driving most logic families including CMOS and TTL. As such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of.5v or more, the ICM555 and ICM55 will drive at least two standard TTL loads. ASTABLE OPERATIO The circuit can be connected to trigger itself and free run as a multivibrator, see Figure. The output swings from rail-to-rail, and is a true 5% duty cycle square wave. Trip points and output swings are symmetrical. Less than a % frequency variation is observed over a voltage range of +5V to +5V. f = RC (EQ. ) The timer can also be connected as shown in Figure 5. In this circuit, the frequency is as shown by Equation : f =. R A + R B C (EQ. ) COTROL VOLTAGE The Control Voltage terminal permits the two trip voltages for the Threshold and Trigger internal comparators to be controlled. This provides the possibility of oscillation frequency modulation in the astable mode or even inhibition of oscillation, depending on the applied voltage. In the monostable mode, delay times can be changed by varying the applied voltage to the Control Voltage pin. RESET The Reset terminal is designed to have essentially the same trip voltage as the standard bipolar 555/55, i.e.,.v to.v. At all supply voltages it represents an extremely high input impedance. The mode of operation of the Reset function is, however, much improved over the standard bipolar SE/E 555/55 in that it controls only the internal flip-flop, which in turn controls simultaneously the state of the Output and Discharge pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices. The duty cycle is controlled by the values of R A and R B, by Equation : D = R A + R B R A + R B (EQ. ) MOOSTABLE OPERATIO In this mode of operation, the timer functions as a one-shot (see Figure ). Initially the external capacitor (C) is held discharged by a transistor inside the timer. Upon application of a negative Trigger pulse to pin, the internal flip-flop is set, which releases the short-circuit across the external capacitor and drives the Output high. The voltage across the capacitor now increases exponentially with a time constant t = R A C. When the voltage across the capacitor equals / V+, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly and also drives the to its low state. Trigger must return to a high state before the can return to a low state. F Rev. Page of

7 Typical Performance Curves MIIMUM PULSE WIDTH (ns) 9 5 = V = 5V = V LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (% ) SUPPLY CURRET (ICM555) (µa) SUPPLY VOLTAGE (V) T A = - C T A = + C SUPPLY CURRET (ICM55) (µa) FIGURE. MIIMUM PULSE WIDTH REQUIRED FOR TRIGGERIG FIGURE. SUPPLY CURRET vs SUPPLY VOLTAGE SOURCE CURRET (ma) = V = 5V = V SIK CURRET (ma).. T A = - C = V = V = 5V VOLTAGE REFERECED TO (V) FIGURE 9. SOURCE CURRET vs VOLTAGE..... LOW VOLTAGE (V) FIGURE. SIK CURRET vs VOLTAGE T A = + C SIK CURRET (ma).. = V = V = 5V SIK CURRET (ma).. = V = V = 5V..... LOW VOLTAGE (V) FIGURE. SIK CURRET vs VOLTAGE..... LOW VOLTAGE (V) FIGURE. SIK CURRET vs VOLTAGE F Rev. Page of

8 Typical Performance Curves (Continued) ORMALIZED FREQUECY DEVIATIO (%) R A = R B = kω C =.µf R A = R B = MΩ C = pf.... SUPPLY VOLTAGE (V) FIGURE. ORMALIZED FREQUECY STABILITY I THE ASTABLE MODE vs SUPPLY VOLTAGE PROPAGATIO DELAY (ns) 5 = 5V T A = + C T A = - C LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (% ) FIGURE 5. PROPAGATIO DELAY vs VOLTAGE LEVEL OF TRIGGER PULSE DISCHARGE SIK CURRET (ma).. = V = V DISCHARGE LOW VOLTAGE (V) = 5V..... FIGURE. DISCHARGE CURRET vs DISCHARGE VOLTAGE ORMALIZED FREQUECY DEVIATIO (%) R A = R B = kω C =.µf = V = 5V = V TEMPERATURE ( C) = V FIGURE. ORMALIZED FREQUECY STABILITY I THE ASTABLE MODE vs TEMPERATURE CAPACITACE (F). m m m µ µ µ n n n p p (R A + R B ) kω kω kω MΩ MΩ MΩ p. k k k M M FREQUECY (Hz) FIGURE. FREE RUIG FREQUECY vs R A, R B AD C CAPACITACE (F). m m m µ µ µ n n n p p kω kω kω MΩ MΩ MΩ p n µ µ µ m m m TIME DELAY (s) FIGURE. TIME DELAY I THE MOOSTABLE MODE vs R A AD C R A F Rev. Page of

9 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISIO CHAGE F. Converted to new datasheet template. Updated Ld PDIP Pin Configuration on page by adding or to pins that have same name. Updated Thermal Information on page by removing Maximum Lead Temperature and Adding T JC values with corresponding note. Updated Ordering Information table on page by removing obsoleted parts, adding Tape and Reel option column, adding MSL note and numbering notes accordingly. Updated POD M.5 to most current version. POD changes are as follows: Changed in Typical Recommended Land Pattern the following:.(.95) to.(.). (.) to.(.). to 5.(.5) Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC 99-. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. o license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see F Rev. Page 9 of

10 Package Outline Drawing M.5 LEAD ARROW BODY SMALL OUTLIE PLASTIC PACKAGE Rev, / DETAIL "A". (.5). (.) IDEX AREA. (.5). (.5). (.) 5. (.).5 (.).5 (.) x 5 TOP VIEW SIDE VIEW B.5 (.).9 (.). (.) SEATIG PLAE 5. (.9). (.9).5 (.9).5 (.5). (.). (.5) -C-. (.5).5(.).(.).5(.).(.) 5 5.(.5) SIDE VIEW A TYPICAL RECOMMEDED LAD PATTER OTES:. Dimensioning and tolerancing per ASI Y.5M-99.. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (. inch) per side.. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only.. The lead width as measured.mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.. This outline conforms to JEDEC publication MS--AA ISSUE C. F Rev. Page of

11 Dual-In-Line Plastic Packages (PDIP) IDEX AREA BASE PLAE SEATIG PLAE D B / B D e D E A. (.5) M C A A L B S -B- -C- -A- OTES:. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ASI Y.5M-9.. Symbols are defined in the MO Series Symbol List in Section. of Publication o Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.5mm). 9. is the maximum number of terminal positions.. Corner leads (,, / and / + ) for E., E., E., E., E. will have a B dimension of. -.5 inch (. -.mm). A e C E C L e A C e B E. (JEDEC MS--BA ISSUE D) LEAD DUAL-I-LIE PLASTIC PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A A B B.5..5., C D D E E e. BSC.5 BSC - e A. BSC. BSC e B L Rev. /9 F Rev. Page of

12 Dual-In-Line Plastic Packages (PDIP) IDEX AREA BASE PLAE SEATIG PLAE D B -C- -A- / B D e D E OTES:. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ASI Y.5M-9.. Symbols are defined in the MO Series Symbol List in Section. of Publication o Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.5mm). 9. is the maximum number of terminal positions.. Corner leads (,, / and / + ) for E., E., E., E., E. will have a B dimension of. -.5 inch (. -.mm). -B- A. (.5) M C A A L B S A e C E C L e A C e B E. (JEDEC MS--AA ISSUE D) LEAD DUAL-I-LIE PLASTIC PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A A B B C D D E E e. BSC.5 BSC - e A. BSC. BSC e B L Rev. /9 F Rev. Page of

13 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLAE SEATIG PLAE S b ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- OTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (,, /, and /+) may be configured with a partial lead paddle. For this configuration dimension b replaces dimension b. 5. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimension Q shall be measured from the seating plane to the base plane.. Measure dimension S at all four corners.. is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ASI Y.5M Controlling dimension: ICH. E L M c ea/ S D S aaa M C A - B LEAD FIISH BASE METAL b M (b) SECTIO A-A S ea c D S (c) F. (MIL-STD-5 GDIP-T (D-, COFIGURATIO A) LEAD CERAMIC DUAL-I-LIE FRIT SEAL PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A b.... b....5 b b c.... c..5.. D E e. BSC.5 BSC - ea. BSC. BSC - ea/.5 BSC. BSC - L Q S o 5 o 9 o 5 o - aaa bbb ccc M , Rev. /9 F Rev. Page of