Copyright 1979, by the author(s). All rights reserved.

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2 MOS SWITCHED CAPACITOR LADDER FILTERS by David James Allstt Memrandum N. UCB/ERL M79/30 May 1979 f / > Vi )

3 l' MOS SWITCHED CAPACITOR LADDER FILTERS t by David James Allstt Memrandum N. UCB/ERL M79/30 May 1979 (V ELECTRONICS RESEARCH LABORATORY Cllege f Engineering University f Califrnia, Berkeley 94720

4 Ph.D. MOS SWITCHED CAPACITOR LADDER KILTERS Duvid James Allstt ABSTRACT Dept. f Electrical Engineering and Cmputer Sciences Chairman f Cmmittee /r Switched capacitr techniques have been investigated fr realizing preci sin high-rder, frequency-selective filters using standard MOS technlgy. New techniques have been develped fr designing recursive switched capacitr singly- and dubly-terminated active ladder filters which simulate lwsensitivity passive RLC ladder netwrks. Three fully-integrated experimental NMOS prttypes have been designed and fabricated. The first circuit implemented a fifth-rder Chebyshev lwpass respnse with 0.1 db passband ripple and an 83 db dynamic range. The secnd design was a third-rder Elliptic lwpass filter which verified a new and efficient methd f including cmplex transmissin zers. This filter achieved a 90 db ACKNOWLEDGEMENTS I am very grateful t Prfessrs Rbert W. Brdersen, Paul R. Gray, and David A. Hdges fr the pprtunity t participate in their MOS analg circuit tech niques research prgram. Their technical guidance and assistance are largely respnsible fr the success f this prject. I have als benefitted greatly frm the persnal advice, encuragement, and supprt frm my clsest advisrs. Prfessrs Paul R. Gray, and Rbert W. Brdersen. I am indebted t many f the graduate students in the Integrated Circuits Grup, bth past and present, fr their useful discussins and assistance. The labratry assistance f D. McDaniel and D. Rgers is acknwledged, and the effrts f D. Simpsn, C. Tast, B. Fuller and B. Kerekes are appreciated. The measurement assistance prvided by the Hughes Aircraft Crp., and the die phtgraphy prvided by Texas Instruments, Inc., are acknwledged. This research was supprted by the Jint Services Electrnics Prgram Cn tract F C-0100, by the Naval Research Office Cntract N C- 0238, and by a dctral fellwship frm the IBM Crpratin. dynamic range with a pwer dissipatin f 18 mw. The third design was an electrically-prgrammable secnd-rder switched capacitr sectin with lwpass. bandpass, and bandreject utputs. This filter demnstrated a new technique fr prgramming a filter respnse using weighted capacitr arrays. In the switched capacitr technique, MOS capacitr ratis and sampling frequency are used as the precisin elements. MOS peratinal amplifiers with mderate perfrmance specificatins are used t implement the switched capa citr integratrs. * %»

5 u ill DEDICATION My wife, Vickie, meticulusly drew mst f the thesis figures and was a great help in assembling the final draft. Withut her lve, understanding and encurage ment, nne f this wrk wuld have been pssible. I dedicate this thesis t her fr the many sacrifices she has made. TABLE OF CONTENTS CHAPTER 1: INTRODUCTION 1 CHAPTER 2: SWITCHED CAPACITOR LADDER FILTER SYNTHESIS Sensitivity f the Dubly-Terminated RLC Ladder Filter The MOS Switched Capacitr Resistr Cncept The MOS Switched Capacitr Integratr Flwgraph Synthesis Techniques MOS Switched Capacitr Filter Circuits Dubly-Terminated All-Ple Lwpass Ladder Filter Lwpass Ladder Filter with Finite Transmissin Zers Singly-Terminated All-Ple Lwpass Ladder Filter Dubly-Terminated Bandpass Ladder Filters Singly-Terminated Bandpass Ladder Filter Singly-Terminated Highpass Ladder Filter Dubly-Terminated Highpass Ladder Filter 44 2.C.8. Dubly-Terminated Elliptic Highpass Ladder Filter 48 CHAPTER 3: CONSIDERATIONS FOR THE MONOLITHIC MOS IMPLEMENTATION OF SWITCHED CAPACITOR FILTERS Sampled-Data Discrete-Time Effects Cntinuus-Time RC Integratrs Discrete-Time Switched Capacitr Integratrs DDI Switched Capacitr Filters withut Predistrtin DDI Switched Capacitr Filters with Predistrtin Type-1 LDI Switched Capacitr Filters Type-II LDI Switched Capacitr Fillers LDI Switched Capacitr Filters with Predistrtin Switched Capacitr Filters with Multiple Sampling Rates Passive Cmpnent Nnideal Effects MOSFET Channel (Switch) Resistance MOSFET Nnlinearity and Threshld Vltage Effects MOSFET Channel-Resistance Thermal Nise Capacitively-Cupled Clck Feedthrugh Junctin and Surface Leakage Currents MOS Capacitr Rati Errrs MOS Capacitr Temperature Cefficient MOS Capacitr Vltage Cefficient Parasitic Capacitances 94

6 iv 3.3. Nnidealities Assciated with the Active Cmpnents 96 3:3.1. Operatinal Amplifier DC Open-Lp Gain Operatinal Amplifier DC Offset Vltage Cmmn-Mde Range and CMRR Amplifier Slew-Rate Amplifier Settling Respnse 100 CHAPTER 4: DYNAMIC RANGE CONSIDERATIONS FOR SWITCHED CAPACITOR FILTERS Harmnic Distrtin in a Switched Capacitr Integratr Scaling Techniques fr Switched Capacitr Filters Ill Impedance Scaling Switched Capacitr Nde-Vltage Scaling Switched Capacitr Lp Scaling Nise in a Switched Capacitr Integratr 123 CHAPTER 5: EXPERIMENTAL RESULTS FOR NMOS LOWPASS PROTOTYPES NMOS Depletin-Lad Operatinal Amplifier DC Open-Lp Gain Equivalent Input Offset Vltage Cmmn-Mde Range and CMRR Equivalent Input Nise Pwer Supply Rejectin Pwer Supply Current versus Supply Vltage Slew-Rate Perfrmance Unity-Gain Bandwidth DDI Switched Capacitr Fifth-Order Chebyshev Lwpass Filter Frequency Respnse Frequency Respnse versus Sampling Rate Frequency Respnse versus Pwer Supply Variatins Harmnic Distrtin Nise Perfrmance LDI Switched Capacitr Third-Order Elliptic Lwpass Filter Frequency Respnse Frequency Respnse versus Sampling Rate Frequency Respnse versus Pwer Supply Vltages Harmnic Distrtin Nise Perfrmance Pwer Supply Rejectin Phase Sensitivity Temperature Perfrmance Intermdulatin Distrtin Quantizing Nise 175 CHAPTER 6: AN ELECTRICALLY-PROGRAMMABLE SWITCHED CAPACITOR FILTER Synthesis f the Prgrammable Secnd-Order Sectin Design f the Prgrammable Switched Capacitr Arrays 6.3. Practical Design Cnsideratins 180 ]g Sampled-Data Transfer Functins Exaci Design Equatins 186 igg Op Amp DC Gain Effects fr Integratr Stages Op Amp Gain Effects fr Bandreject Stage Tp-Plate Parasitic Capacitance NMOS Prttype Experimental Results Center Frequency Prgramming Clck Frequency Prgramming Selectivity Prgramming J9g Gain Prgramming Lw-Q Passband Details Dynamic Range A Frmant Speech Synthesis System The Vcal Tract Mdel A Switched Capacitr Frmant Synthesizer 204 CHAPTER 7: CONCLUSIONS 207 APPENDIX 1: NMOS METAL-GATE ENHANCEMENT-DEPLETION PROCESS 209 APPENDIX 2: NMOS ENHANCEMENT-DEPLETION DEVICE CHARACTERISTICS 214 APPENDIX 3: SIMULATION TECHNIQUES FORSWITCHED CAPACITOR FILTERS 217 REFERENCES 225

7 Chapter 1 INTRODUCTION Precisin high-rder filters are widely used in varius types f electrnic equip ment such as telecmmunicatins and ther vice-band systems 111. Mnlithic implementatin f these lw frequency filters requires the realizatin flng time cnstants in small silicn area, and the realizatin f transfer functins that are insensitive t parameter variatins. In additin, it is desirable t btain a very pre cise respnse withut external trimming peratins. Cnventinal active filters implemented with thin-film r hybrid technlgies d nt meet these requirements, and therefreare nt suitable fr many applicatins. Recently, these bjectives have been realized in a mnlithic implementatin using a cmpatible Biplar/JFET technlgy [21. Althugh excellent results have been btained, this apprach requires a relatively large chip area fr lw frequency applicatins, and the required biplar prcess is nt directly cmpatible with dense digital lgic which is needed fr many LSI system applicatins. Anther prmising mnlithic filtering apprach uses charge transfer devices (CTD's) t implement sampled-data transversal filters 13]. In the past, this apprach had tw main disadvantages: (1) The large inserun lss (which was typi cally 20 db) limited the available dynamic range [41, and (2) the relatively lw sam pling rates cmplicated the design f the cntinuus-time anti-alias prefilter [5]. If higher clck frequencies were used relative t the passband frequencies in rder t reduce the prefilter requirements, mre CTD stages were required which further reduced the dynamic range and increased the silicn area requirements. Recently, these prblems have been slved by using a duble split-electrde CCD structure perating at 32 khz with a 128 khz sampled-data prefilter [441. This apprach appears t be very prmising fr future applicatins. In the 1960's and early 1970's, filtering by using switches and capacitrs was investigated theretically [6]-[81. At that time, a suitable integrated circuit technl gy did nt exist which culd efficiently realize these filters. Recent wrk using analg sampled-data techniques has demnstrated the viability f MOS technlgy fr implementing secnd-rder filters. The classical direct-frm secnd-rder digital filter sectin [91-[101 has been implemented in an equivalent integrated circuit frm using an MOS sampled-data apprach [11]. This apprach (as well as the directfrm digital prttype) has a relatively high sensitivity f the transfer functin t cmpnent variatin with the additinal disadvantage that the sensitivity increases as the rati f the sampling rate t passband frequencies increases. Hence, there is a tradeff between the sensitivity prperties f the direct-frm sampled-data filter, and the requirements fr the cntinuus-time anti-aliasing prefilter. In digital filter implementatins, these prblems were slved by using a mdified secnd-rder structure [121. Recently, MOS equivalents f these filters, as well as biquad secnd-rder sectins, have been realized with excellent results using switched capacitrs t simulate resistrs in sampled-data switched capacitr integratr cnfiguratins [13]-[15]. A majr advantage f this apprach is that the sensitivity f the respnse f these filters decreases with increasing clck frequency, in cntrast t the direct-frm implementatins. Unfrtunately, high-rder filters realized by cascading these secnd-rder sectins can be t sensitive t cmpnent variatins t meet high-precisin filtering requirements. It is well knwn frm mdern filter thery that fr high-rder fillers, a passive dubly-terminated RLC ladder achieves very lw sensitivity t cmpnent varia tins in the passband respnse, and in fact, has zer sensitivity when the pwer transfer is maximized between surce and lad [ ). This lw sensitivity is maintained by using "leapfrg" r "active ladder synthesis" t simulate RLC ladder netwrks with active filter building blcks ( ). In rder t btain minimum

8 sensitivity high-rder filters, a similar apprach t the leapfrg design was taken in this thesis which makes use f new switched capacitr techniques. The precisin elements in these filters are mnlithic MOS capacitrs whse ratis determine the frequency respnse. The inherent temperature stability (< 25 ppm/ C) and high matching accuracy (0.1%) f MOS capacitr ratis [21]-[23l make it pssible t implement mnlithic high-rder filters with extremely precise frequency characteristics 124]-(251. The apprach t synthesis taken in this dissertatin will be t cnfigure the switched capacitr circuits t simulate the lw-sensitivity cntinuus-time RLC ladder circuits, s that the design tables that are available fr these fillers can be used [26M271. It will be shwn that it is pssible t minimize mst f the discrete-time effects (particularly phase shifts due t time delays) which will allw design using classical cntinuus-time thery directly. Hwever, ne discrete-time characteristic which must be cnsidered is the necessity f prviding a cntinuustime anti-aliasing prefilter preceding the switched capacitr filter. The lw sensi tivity prperties f the ladder filters are actually imprved with increased sampling frequency, and thus, the anti-aliasing prefilter requirements are greatly reduced (cmpared t thectd and direct-frm appraches) by perating the switched capa citr filters at clck frequencies which are many limes greater than the passband frequencies. InChapter 2, the sensitivity prperties f dubly-terminated RLC ladder filters are presented. The signal flwgraph synthesis prcedure is reviewed, and varius filter types are synthesized using switched capacitr integratrs as the basic building blcks. Several new singly- and dubly-terminated highpass structures are presented. In Chapter 3, the practical design aspects fr MOS integrated circuit implemen tatins f switched capacitr ladder filters are given alng with a descriptin f the effects f finite sampling frequency. A new LDI integratr is presented which is insensitive t parasitic capacitance. In Chapter 4, nise and dynamic range cnsideratins fr MOS active ladder filters are presented. Als presented are new scaling techniques which are mre general than the scaling prcedures which are used in the RLC prttypes. In Chapter 5, experimental results btained frm tw different integrated NMOS switched capacitr ladder filters are described. The first design is a Che byshev fifth-rder all-ple lwpass filter, and the secnd design implements a third-rder elliptic lwpass respnse including a very efficient realizatin f transmissin zers. These filters achieve very precise respnses with wide dynamic range while requiring small chip area, lw pwer dissipatin, and relatively lw per frmance peratinal amplifiers. An NMOS depletin-lad peratinal amplifier design is als summarized. Chapter 6 presents the synthesis prcedures and design cnsideratins fr an MOS switched capacitr prgrammable filter fr applicatins in frmant speech syn thesis. New experimentakresults are presented fr a prgrammable secnd-rder switched capacitr sectin. A summary f this research prject is presented in Chapter 7. In Appendix 1, the NMOS depletin-lad metal-gate prcess which was used t fabricate the experimental test circuits is given. Appendix 2 cntains the measured NMOS device parameters which are used t estimate the perfrmance parameters fr the NMOS peratinal amplifier. In Appendix 3, mdels are presented which are useful fr simulating switched capacitr filters using a digital netwrk analysis prgram called D1NAP [28]. It is shwn that mst f the imprtant analg effects can be mdelled in the digital dmain. This apprach has the advantage f accurately predicting discrete-time

9 effects in cntrast t a cntinuus-time simulatin apprach. Chapter 2 SWITCHED CAPACITOR LADDER FILTER SYNTHESIS This chapter begins with a review f the sensitivity prperties f dublyterminated RLC ladder filters fllwed by a review f the switched capacitr resis tr cncept, and the develpment f the switched capacitr integratr. In the final sectins, the signal flwgraph synthesis prcedure is develped and used t design bth singly- and dubly-terminated lwpass, bandpass, and highpass switched capa citr ladder fillers Sensitivity f the Dubly-Terminated RLC Ladder Filter Fr high-rder filters, a passive dubly-terminated RLC ladder achieves very lw sensitivity in the passband respnse, and in fact, has zer sensitivity when the pwer transfer is maximized between surce and lad 16]-(17). Fig. 2.1(a) shws a dubly-terminated RLC fifth-rder lwpass ladder filter. In Fig. 2.1(b), the pwer delivered t the utput is pltted fr variatin f a cmpnent value. When all ele ments achieve their nminal values, the pwer delivered t the utput is max imum. Hwever, if a reactive element value is either increased r decreased, the dp pwer delivered t the utput decreases. Since the slpe,, is nminally zer, X small perturbatins in the element values will cause very small changes in the passband respnse f the filter [27]. The lw passband sensitivity is illustrated by cnsidering a specific example. The fifth-rder RLC lwpass ladder filter f Fig. 2.1(a) has been frequency scaled t realize a Chebyshev respnse with 0.1 db nminal passband ripple and a nminal cutff frequency f 3.4 khz as shwn in Fig. 2.2(a) [291. this particular filter is mst sensitive t the variatin f C3. The transfer functin f Fib. 2.2(b) shws the simulated results fr the passband deviatin frm the nminal design fr ±1%

10 R1 L-2 L4 IN Ci^TVi c s^r:tv5 R2ffV6 VOUT "ii VI, vl, (a) MAX = 0 NOM (b) NOM ^X Fig (a) An RLC dubly-terminated fifth-rder lwpass ladder filter; (b) the utput pwer fr variatin f a reactive element value. Fig (a) A nminal fifth-rder Chebyshev lwpass respnse with 0.1 db passband ripple and a 3.4 khz cutff frequency; (b) simulated passband deviatin fr ±1% variatins in C3.

11 ,^.,_ 10 variatins in C3 (30J. At thse frequencies where the filter respnse f Fig. 2.2(a) has again f -6dB, indicating maximum pwer transfer, the passband deviatin, and hence the sensitivity f Fig. 2.2(b) is zer. > > b The sensitivity acrss the entire passband is very lw since a variatin f ±1% in C3 results in a maximum <N a. Q. a. E Q. a. passband deviatin f nly ±0.015 db. The passband sensitivity f this dublyterminated RLC ladder is abut 10 times lwer than a similar singly-terminated >S 1 CM CO RLC ladder [31], and abut 20 times lwer than a similar cascade RLC realiza tin [321. Hence, fr implementing high-rder, high precisin mnlithic filters, it LU m- 3Z is desirable t use an equivalent frm f the dubly-terminated RLC structure in rder t btain the desired lw sensitivity. Unfrtunately, the netwrk f Fig. 2.1(a) cntains bth inductrs and resistrs which are difficult t implement in MOS technlgy. The next sectins will describe an apprach fr cnverting an RLC filter int an equivalent MOS switched capacitr ladder which is well-suited fr integratin, and which retains nearly ideal sensitivity prperties.,s O 2.2. The MOS Switched Capacitr Resistr Cncept Large resistance values are difficult t accurately realize in integrated circuits due t the lack f high resistivity regins. One pssible slutin t this prblem is t use lightly dped plysilicn resistrs LU UJO CM IS) ^" >* ' c in ^rti. CL O a. a.. a. 6 E E (TO a. O -«. Unfrtunately, the abslute values f these resistrs vary widely with temperature and prcessing variatins, and their vltage cefficient is rather large 133). In implanted and diffused resistrs have similar disadvantages as shwn in Table I [34]. (These resistrs are ften adequate fr the required cntinuus-time anti-aliasing prefilter). Recently, these disadvantages have been vercme by using acapacitr which is switched between vltage surces t simulate a resistr as shwn in Fig. 2.3(b) [13J-I151. At time t,*, turns n MOSFET MA, and Cu is charged t E M i3 l3 O s5^ * UDO»- II O_J d tr. ccc> cc Q Q_ t- i/i i- LU l/> LU >- h- i/i 1- H t LU Z«K QC LU :fficient OLTAGE :hing racy MATC ACCU CO Q. < a LU Z 1- CC t/> -j cc l/> a. 3 z ~LU Zc: a Z LU 3: ti 1 a. >: a _i 2ll. </> Table I. Prperties f mnlithic resistrs and capacitrs.

12 11 12 Qi - CUV, (2.1) Vi R -VWV ^ V2 (a) I At time (t + Tc), <t>2 turns n MOSFET MB (MA is nw turned ff), and Cu is charged t Q2 - cuv2. (2.2) The current which flws nt Cu is given by. A QCVa-V,) At Tc (2.3) V, The current flwing thrugh the resistr f Fig. 2.3(a) during the same perid f time is I Va-V, (2.4) (b) Therefre, an equivalent switched capacitr resistance, Req, can be defined by V ON equating Eqns. (2.3) and (2.4): V, OFF *1 R «i--l_ (2.5) V, ON V, OFF <t>: where Cu is the switched capacitr value, and fc is the sampling frequency. This equivalence is valid fr sampling rates which are much greater than the signal fre quencies f interest. If this cnditin is nt met, mre exact sampled-data analysis is required [35]-[36]. Fig (c) (a) A cnventinal resistr, and (b) a switched capacitr "resistr"; (c) the tw-phase nn-verlapping clck signals used t switch the MOSFET's. Cu may be switched between tw pints which are nt vltage surces. Fr example, in Fig. 2.4, the resistr, R,, is replaced by the switched capacitr, C,, t frm a sampled-data passive lwpass filter. Sampled-data techniques are required t analyze these circuits, and in certain cases, ther factrs such as clck duty cycles

13 13 14 R JVAAAr V,N C2^rs Vqut must be cnsidered which can greatly cmplicate the design [37]. In this disserta tin, it will be assumed that the switching ccurs between vltage surces (includ ing virtual grunds) as in the example f the switched capacitr integratr which will be described in the next sectin The MOS Switched Capacitr Integratr 00 Cnventinal filtering appraches used t implement audi and ther lw fre quency filters wuld require RC integratrs, as in Fig. 2.5(a), with lng time cn-! slants. If the time cnstants were realized as RC prducts, large amunts f chip area wuld be required. Anther disadvantage f this apprach is that in rder t insure reprducibility, the abslute values f bth R and C must be tightly cn trlled, which is extremely difficult fr typical temperature and prcessing variatins as indicated previusly in Table 1. These disadvantages are vercme by using the switched capacitr circuit (b) j shwn in Fig. 2.5(b) which, when the rati f the sampling frequency t the max- ' imum passband frequency is large, clsely apprximates the cnventinal integratr f Fig. 2.5(a) [13]-[14]. The switched capacitr integratr is perated with twphase nnverlapping clcks as shwn earlier in Fig. 2.3(c). During the sample phase, 0, the switches are thrwn t the left, and the difference between vltages V, and V2 is sampled and stred n Cu. During the integratin phase, <f>2, the switches are thrwn t the right, and the difference vltage is scaled and stred n C. By switchingcu at a high clck rate, fc, relative t the passband frequencies, an Fig (a) A single-ple RC lwpass filter, and (b) a passive single-ple switched capacitr lwpass filter. equivalent resistance is btained f value leq 1 fc<v (2.6) I resulting in an integratr gain cnstant f. *

14 15 16 REqC fe c, (2.7) Fig. 2.5(b) can als be analyzed directly using a z-dmain analysis [35], and -V0UT the cnservatin f charge principle. Assuming ideal cmpnents, the charge stred n the capacitrs at time (t-tc) is q,(t-tc) - Cu[v2(t-Tc)-V,(t-Tc)] (2.8a) and q2(t-tc) - C,V0Ul(t-Tc). (2.8b) At time t when the switches are thrwn t the right, the p amp discharges Cu nt VquT C], and the system charge is nw q2(t) - C,V0Ul(t) (2.9a) and q,(t) - 0. (2.9b) Eqns. (2.8) and (2.9) can be equated t yield V0UI(t) - -^ [v2(t-tc)-v,(t-tc)] +Vul(t-Tc). (2.10) In the z-dmain, this expressin becmes Fig (a) A cnventinal RC differential integratr, and (b) a switched capacitr integratr with differential inputs. Vu,(z) z-,v2(z)-z-,v,(z)] +z-»vut(z) (2.11) which is slved fr Vul(z):

15 17 18 VOUI(z) l-z-> (2.12) Assuming f«fc, and replacing z=estc in Eqn. (2.12) by its Taylr series expan sin, with s=e$ c. fc Vul(s) «[v2(s)-v,(s)j, (2.13) Hence, the term "integratr" is used t represent this building blck, and the gain cnstant derived frm Eqn. (2.13) agrees with the intuitive result f Eqn. (2.7). The differential integratin prperty is als evident frm Eqn. (2.12). The switched capacitr realizes very large resistance values in very small chip areas. Fr example, frm Eqn. (2.5), it is seen that by switching a 1 pfcapacitr at 100 khz, an equivalent resistance f 10 Mfl is realized in an area f nly abut 5mil2 fr Cu plus a few additinal mil2 fr the tw minimum gemetry MOSFET switch transistrs. (It is als interesting t nte frm Eqn. (2.5) that as the resis tance value increases, the area required fr its switched capacitr implementatin actually decreases). If this equivalent resistr is used in cnjunctin with C «=10CU, again cnstant f 104 radians/sec is btained. Hence, byusing the switched capaci tr t simulate a resistance, lng time cnstants are achieved in small silicn area, and since the integratr gain cnstant f Eqn. (2.7) is nw determined by a rati f mnlithic capacitrs, high matching accuracy and excellent temperature stability 2.4. Flwgraph Synthesis Techniques One technique fr designing an active ladder netwrk frm a passive RLC pr ttype is t transfrm the differential equatins describing the netwrk int a picvial.epresentatin called, a flw diagram 20],[25],[38],[39]. The flw diagram cntains ndes fr bth vltage and current variables in the circuit. The branches which intercnnect these ndes represent the transfer functins f each circuit ele ment. There are several valid flw diagram representatins f a given netwrk which require different circuit realizatins. The bjective is t manipulate the signal flw diagram in rder t btain a representatin that can be realized with switched capacitr integratrs. T cnstruct a flw diagram, ne simply creates a nde fr each vltage and current in the circuit, and then intercnnects them with the prper impedance r admittance using KirchhfTs ndal and lp equatins. Once the prper flw diagram is cnstructed, the transfrmatin int a switched capacitr cir cuit easily fllws. A passive dubly-terminated RLC lwpass ladder which will be used as the prttype fr the switched capacitr implementatin was shwn in Fig. 2.1(a). In this figure, the vltages and currents f each circuit element are labelled. A cm plete set f lp and nde equatins which invlves nly integratins is shwn belw: V I. (2.14a) R. are btained in mnlithic MOS implementatins. The next sectin will review flwgraph synthesis prcedures fr MOS switched capacitr active ladder netwrks. V0 - Vin - V, 1. -I0-I2 (2.14b) (2.14c) sci (2.14d)

16 19 20 l2~ir2 (2.14e) V2-V,-V3 ( *> 3 O > ) I3 " h ~ I4 1 -A 4 sl4 v4-v3-v5 I5-I4-U (2.14g) (2.14h) (2.14i) (2.14J) (2.14k) ID ^>{ i 1 1 * If) 1 > 1" 1 -te Ol" 1 > ' H-T \u> v < > IT) 10 > ^ ( > ' I ' 1, _ 1 cu a:\cr. 1 * 1 1 CA 1 * rr_i 1 CO 1 1 a 1 v q: ^ -5?» r T*> 10 «> 1 II «> *-i II V>-Ic7 u-i v6 " V5 vui - V6. (2.141) (2.14m) (2.i4n) (2.14) The flw diagram which represents these equatins is shwn in Fig. 2.6(a). Each nde (vltage r current) is denned by the signal paths flwing int it. The factr written next t each arrw, denting the directin f the path, is the gain fr that path. Multiple inputs int a single nde are cnsidered summed. Since the actual implementatin will use vltage integratrs, it is necessary t transfrm current ndes t vltage ndes. This is perfrmed by multiplying all current ndes by a scaling resistance R s that the currents, Ij, are nw represented as the vltages :> ' ->'' > ( -? < > ' 1 1 * 1 t a 1 ^, -k 1 v? < > Fig \v 1 CA -1* a 10 r-i CM r > ' CM, > ^ ' ^?, ^ Z<> ' T 1 rt 1 n ' CA 1 " 1 CA p rr 1 CO rr rr n 1 v i. 11 cr "cm CM > II L~^ > - II (a) A signal flw diagram fr the circuit f Fig. 2.1(a), and (b) an equivalent type-1 all-vltage frm. -Q

17 21 22 V,'=i<lr In rder t maintain the prper relatinships between the vltage and current ndes, the branch gain factrs are als scaled by R in Fig. 2.6(b). ** ' There are tradeffs between capacitr area and filter dynamic range which are invlved in chsing a value fr R which will be described in greater detail in <, > 1 CM CD > Chapter 4 [40]- [41]. In general, a value f R«l hm is a gd cmprmise, and fr this case, the integratr time cnstants are the riginal L r C values. After 1 " scaling, the terminatins, Rj and R2, are realized by cnnecting the utputs f the m > t lo CA ' > R terminating integratrs t their inputs multiplied by the gains Ri R and. The R2 ptimum chice fr the values f Rj and R2 depends n many factrs, and they will.<*, 1 r 1, 4? i - r <->»CA > I be assumed t equal 1 hm in the designs in this chapter. The flw diagram in Fig. 2.6(b) is ne f many that dewribe the ladder f Fig. 2.1(a). Fr example, the equivalent flw diagam f Fig. 2.6(c) is useful in the develpment f type-h LDI switched capacitr filters which are insensitive t parasitic capacitances. This technique will be discussed in detail in Chapter 3. CM ( > k 1 " 1CA V CM > 2.5. MOS Switched Capacitr Filter Circuits Using the signal flwgraph techniques, and switched capacitr integratrs, z> \ > 'T 1 tr, 1 CA fx cr ^ many types f filters can be designed. This sectin- will present several design examples which illustrate the signal flwgraph synthesis prcedures Dubly-Terminated All-Ple Lwpass Ladder Filler T In the flw diagram f Fig. 2.6(b), it is apparent that the basic element is a z > I differential integratr. If five switched capacitr differential integratrs are intercn nected as indicated in the flw diagram, the result is the cmplete switched capaci Fig (c) A type-u signal flu diagram fr the circuit f Fig. 2.1(a). tr circuit shwn in Fig. 2.7 which clsely apprximates the RLC netwrk f Fig. 2.1(a). In this figure, the phasing f the switches is alternated t btain the

18 23 24 type-1 LDI cnfiguratin. The final step in the design is t determine the capacitr ratis required in the circuit. It will be assumed that R,-R2-R-l hm and that the element values f the passive prttype (Cb L2, C3, L4 and Cs) were btained frm standard design tables s that they crrespnd t a cutff frequency f 1 rad/sec [26],[27],[29]. The rati f the integrating capacitrs (CC, CLj, CC), CLt and CCj in Fig. 2.7) t the switched capacitrs, Cu, can be fund frm Eqn. (2.7) and the flw diagram: cu f«cl (2.15a) fcl2 (2.15b) Eh Cu (2.15c) Shi C f±4 (2.15d) Cct f«cj (2.15e) where tu^, is the desired cutff frequency f the filter, and fc is the sampling fre quency. The terminatins are paths using unit sized capacitrs (assuming 1 hm termi natin and scaling resistrs) frm the utput t the input f the first and last integratrs. Unfrtunately, there is an extra half cycle delay thrugh the termina Fig A fifth-rder switched capacitr type-i LDI dubly-terminated lwpass ladder filter. tin lps. This extra delay causes an errr in the simulated terminatin resistance. In practice, the frequency respnse errr due t this incrrect terminatin is ften negligible [24], [25],[42].

19 Lwpass Ladder Filter with Finite Transmissin Zers The additin f finite transmissin zers t a lwpass ladder filter respnse has great imprtance in many filter applicatins [1]. The zer additin is achieved n the RLC lwpass prttype by adding feedthrugh capacitrs acrss the series arm f the ladder netwrk such as C2 in Fig. 2.8(a). Imaginary axis zer lcatins are the resnant frequencies f the RLC resnant tank circuit, i.e. w0 - [L2C2]"<)5. The flw diagram fr this netwrk is nt as straight frward as fr the simple lwpass case. The usual apprach t flw diagram cnstructin f the circuit is suit able nly fr cntinuus-lime active RC implementatins because it cntains vl tage attenuatrs. Usually, this is nt desirable in a switched capacitr implementa tin since additinal p amps wuld be required. In rder t design a switched capacitr netwrk with zers which des nt require any additinal peratinal amplifiers, it is useful t examine in detail the peratins that are perfrmed by the feedthrugh capacitrs added t the lwpass ladder structure. Referring t Fig. 2.8(a), a three-ple, tw-zer RLC filter is shwn with vltages and currents defined. Using KirchhfTs current law at ndes A and B, the fllwing equatins are derived t explain the functin f C2: IN V0 R2 VOUT * * R, I 0 -z L2 -* I2-4 I ^(C,+C2) C2-3) Vvi( 3*C +C2 1 (b) C,+C2?n(C2+C3) c2 c2+c3!r 2 V,OUT (I0-I2) s(ci+c2) + v, C,+C5 (2.16) and VquT V,- s(c2+c3) T Y, C2+C3 + v, (2.17) Thus, C2 has been identified as an element that feeds sme f the charge at nde A t nde B and vice-versa. As illustrated in Fig. 2.8(b), in rder t implement a cmplex transmissin zer pair, it is necessary t change the integratr gain Fig <a) An RLC third-rder elliptic lwpass ladder filter, and (b) an equivalent frm; <ci the crrespnding signal flwgraph.

20 27 28 cnstants that represent shunt capacitrs t accunt fr the feedthrugh capacitr. This actin, alng with creating the feedfrward and feedback paths, cmpletely simulates the added series capacitance. In the switched capacitr implementatin, the integratr gain cnstants are easily changed by adjusting their capacitr ratis. The paths linking V, and V3 f Fig. 2.8(c) require the additin f tw p amp utputs. Fig. 2.9shws a circuit that achieves the required integratin and additin withut additinal p amp stages. The circuit perfrms a standard sampled-data integratin n Vin, and in additin, cntinuusly multiplies Vx by a cnstant and sums it t the utput. Since Q and Csare held t a virtual grund n ne side by the p amp, Cs charges t Qs~CsVx and the utput due t V is given by, v -_ik«* c vx. (2.18) VqUT Althugh the summatin is cntinuus, in the filter, Vx will be derived frm anther integratr whse utput changes nly nce every clck cycle. Using switched capacitr integratr/summers fr (Cj+C2) and (C2+C3) in Fig. 2.8(c) allws the necessary additins at ndes V, and V3. Since the summatins invlve a sign inversin, sme minr mdificatins must be made t the flw diagram. Fr example, if nde V,, the utput f an p amp, must cntain a fractin f anther nde vltage V3, the tw vltagesmust be f ppsite sign n the flw diagram. The methd described abve fr btaining transmissin zers requires very lit tle additinal hardware ver the all-ple filter circuit. The example chsen t demnstrate the design methds f this sectin is a third-rder elliptic filter [25]. The RLC netwrk cntains 4 energy string devices, while the final switched capa citr circuit shwn in Fig requires nly 3 peratinal amplifiers. In additin, nly 2 switches and 4 small capacitrs are required ver the simple lwpass Fig A switched capacitr integratr/summer.

21 29 30 structure Singly-Terminated All-Ple Lawpass Ladder Filter <r A singly-terminated lwpass fitter is a special case f a-*lubly4erminated RLC netwrk with an infinite lad resistance. Since,the terminatins appear as feedback - paths in the switched capacitr netwrk, the switched capacitr singly-terminated netwrk is derived frm the dubly-terminated netwrk by simply mitting the ter minatin feedback path n the last stage. A singly-terminated fifth-rder switched capacitr lwpass filter is shwn in Fig Dubly-Terminated Bandpass Ladder Filters The bandpass ladder is btained by perfrming the standard lwpass-tbandpass transfrmatin n the lwpass prttype f Fig. 2.12(a). This is dne by letting s» B J_ + ^Is (2.19) where B is the desired bandwidth and m0 is the center frequency as shwn in Table II [43]. Figure 2.12(b) shws a 4-ple RLC bandpass structure after transfr matin. An all-integratr signal flw diagram fr the bandpass ladder is given in Fig. 2.12(c). Frm Eqns. (2.7) and (2.19), the elements in the bandpass netwrk f Fig. 2.12(b) are fund t be Fig A third-rder switched capacitr lype-1 LDI dubly-terminated elliptic lwpassladder filter. CA- B QC, B 1 C,«02 QC ti>0 (2.20a) (2.20b) #

22 ET > Q. O. 3) O, W c. f 'OUT (k! 1 3 f NORMALIZED LOW-PASS ELEMENTS HIGH-PASS ELEMENTS BANDPASS ELEMENTS BAND-REJECT ELEMENTS re ~i 2 3 W 09 -I ar i/> m i * i l/l ~* f * ST re a 3 "2 II i/> X N ftcl-n ft B -nrm B ^LN ft l/bln 1? J; 3 Q. CN ftc^n B n*cn BCn _mm. BC N n ft VS

23 33 3* ^-vw- L2 L2 QL2 B B > (2.20c) IN 7kC R2 VOUT and * i O MAr *» Ri II (a) ^L V L LB c \(r r "U V4 V0UT L^2 QL2O)0 Frm the element values abve, the capacitr ratis are calculated: CCa ^ C,fc QC,fc Cu B w0 CLA Cu - Bfc C,a»02 fc QCjtD (2.20d) (2.21a) (2.21b) 4 (b) Cu - B QL/c (2.21c) VlN V0., V, V4 v0ut CcB Bfc _ fc Cu L^2 QL2tc (2.21d) Nte that the bandpass circuit has the same frm as a lwpass ladder circuit with tw-integratr lps substituted fr single integratrs. This crrespnds t the -transfrmatins f single lwpass elements int L-C resnant circuits as dictated by Eqn. (2.19). A signal flw diagram fr the bandpass ladder is mre cmplicated than that fr the lwpass ladder due t the shunt and series element pairs. A switched capa citr versin f this bandpass filter which is btained frm the flwgraph synthesis prcedure f Sectin IV is shwn in Fig Fig (a) An RLC tw-ple dubly-terminated lwpass ladder prttype; (b) the RLC fur-ple bandpass filter, and (c) the crrespnding signal flwgraph.

24 Singly-Terminated Bandpass Ladder I Filter As in the lwpass case, the singly-termin; atedbandpass ladder is btained frm the dubly-terminated bandpass ladder by sii mply eliminating a terminatin feed back lp. A singly-terminated RLC 4-ple: bandpass derived frm the singlyterminated RLC lwpass f Fig. 2.14(a) is shwn in Fig. 2.14(b), with its switched capacitr equivalent circuit in Fig. 2.IS Singly-Terminated Highpass Ladder Fiilter A highpass filter is btained by perfrming the standard lwpass-t-highpass transfrmatin n the RLC lwpass prttype aas indicated in Table II. This is dne by letting s (2.22) which simply replaces all inductrs by capaichrs and vice-versa. A singlyterminated RLC highpass ladder filter is shwn in Fig. 2.16(a). Figure 2.16(b) shws the crrespnding signal flwgraph whicbi unfrtunately cannt be directly implemented using switched capacitr techniques because summed signals (such as V2) cannt be accessed and fed frward since the summing is. perfrmed int a vir tual grund. The intermediate flwgraph f Fig. 2.16(c) can be cnstructed by defining sme new variables: v2 - - (V, - Vta) - - V," (2.23a) v4--(v3-v2)--v3- (2.23b) Fig A switched capacitr dubly-terminated fur-ple bandpass ladder filler. Ii-Ii + Ij-Ia* (2.23c) I3-l4 + I5-I4. (2.23d)

25 37 38 L jrm =3 V, N R. V OUT (a) L ft V, IN Lq^ OdT* r\ V OUT (b) 1 <^ < ^ =» U-/ Fig (a) An RLC tw-ple singly-terminated lwpass ladder prttype; (b) the crrespnding RLC fur-ple bandpass filter. Fig A switched capacitr singly-terminated fur-ple bandpass ladder filler.

26 39 40 c'ii ft^3 V!N 1L23tv23L4 )v*4 R2 tv5 V0UT I4 OUT, V0UT=A/3-1 9 "I v IN Fig V/-1 V2-l V3-I V4 1 V5 1 > 0 > 9 > 9 >9 > 9 > J_ SC SL SC SL 6 < 6 / < 6 ^ O < 0 It 1 I2 1 I3 1 i; 1 I5 (c) VOUT J_ R2 (a) A furth-rder singly-terminated RLC ladder filter; (b) the flwgraph fr Fig. 2.16(a), and (c) an equivalent intermediate flwgraph. Fig (e) (d) An iniermediaie flwgraph. and (e) the final flwgraph fr the circuit f Fig. 2.16(a).

27 41 42?-V3 = V0UT Vm = Fig (0 A symblic implementatin f the flwgraph in Fig. 2.16(e) using integratrs and summers. Fig («> A type-11 LDI switched capacitr furth-rder singly-terminated highpass ladder filter.»» «

28 43 44 The flwgraph f Fig. 2.16(c) is still nt realizable due t the signals leaving sum ming ndes. Hwever, by nting that *- -"»-& ' (2.24a) V< - V. - - V, (2.24b) and Ti:: i I. sli + Ii sli + L (2.24c) :i >-3. OJ, M> ' J ' 1 -> ' * «< 1 * * W* 1 >*! «1 :.s :..n the signal flwgraph f Fig. 2.16(d) is btained, which when the signs are apprpri ately mdified, results in the flwgraph f Fig. 2.16(e) which is implemented using integratr/summers in Fig. 2.16(f). Figure 2.16(g) shws the switched capacitr versin, and Fig. 2.16(h) shws a DINAP simulatin fr a furth-rder singlyterminated highpass ladder filter with a 300 Hz cutff" frequency when clcked at 128 khz Dubly-Terminated Highpass Ladder Filter A signal flwgraph fr the RLC dubly-terminated ladder filter f Fig. 2.17(a) is shwn in Fig. 2.17(b). Unfrtunately, the cntinuus lp frmed arund the summatin path has a gain which is nminally ne, s that this netwrk is prne t scillatin. Fig <h) A DINAP simulatin fr the circuit f Fig. 2.16(g) with a 300 Hz cutff frequency when clcked at 128 khz. 2 i 2 i i One slutin t this prblem ist use adifferent frm f the infrmatin cn tained in the signal flwgraph. Frm the flwgraph f Fig. 2.17(b), the utput vl tage is Vu, - V, - V, (2.25)

29 45 46 R i L * I «- C T i(^2 V V2 V.n "" L, 3 V! 2L3 3 V3 R2; It?I3 \U VUT (a) (c) (b) Fig (c) A symblic representatin f Fig. 2.17(a) using integratrs and summers. Fig (a) A third-rder dubly-terminated highpass ladder filter and (b) a signal flw diagram.

30 47 48 and the ther utput variables in the circuit are I,, and 13. A dubly-terminated structure can be frmed by slving fr all f the utput variables in terms f them selves and the input vltage t btain: I'-sy-(-v*)-,«-v--4 v - (-Vin> II I3 1, (2.26a) (2.26b) and -i-v v sl3 3 sl3 ut' (2.26c) n:: c3:«cs..«5-3:: e.< >c.» A symblic representatin f these equatins is shwn in Fig. 2.17(c) with a DINAP simulatin in Fig. 2.17(d) fr a 300 Hz cutff frequency when clcked at 128 khz. Since there are n cntinuus lps, this circuit will nt be subject t scillatin Dubly-Terminated Elliptic Highpass Ladder Filter Many applicatins require ahighpass respnse with additinal rejectin f cer tain frequencies. A dubly-terminated RLC elliptic highpass filter is shwn in Fig. 2.18(a). This circuit can be simplified by slving fr V, and V3 Mi; :1...J. 51 "l^fel*-1^ (2.27a) and Fig (d) A DINAP simulatin fr the circuit f Fig. 2.17(c) with a 300 Hz cutff frequency when clcked at 128 khz. V3-skt H(l2-l4)+U-> L2+L3 L2+L3 (2.27b)

31 49 50 t btain the equivalent circuit fr the elliptic highpass shwn in Fig: 2.18(b). Using an equatin frmulatin similar t that f the previus sectin, the circuit f Fig. 2.18(c) is derived with a DINAP simulatin shwn in Fig. 2.18(d). An advan tage f this frmulatin ver a direct fur amplifier implementatin is that by frm ing the equivalent circuit f Fig. 2.18(b), the large L2 value is reduced by paralleling it with the tw smaller inductrs, L, and L3, and therefre, the required silicn area is greatly reduced. Ri WW V, IlA L2 f>rrm1 <D L13lV1 2L3^V3R2 tv4v0ut fit fc fc - m m < m ( ) RH ft v0 I v2 tbl L, v,n H LfL2 p1 v, v3 [ v4: R: V, OUT V, V, L+L-n'I, 'L2+L3Vri "I. (b) Fig (a) A dubly-terminated RLC third-rder elliptic highpass filter, and (b) an equivalent frm.

32 51 n i:: I:: r. I "i 1-3: * * 131 (c) f? It' t Fig (c) A symblic implementatin f Fig. 2.18(a) using integratrs and summers. Fig (di A DINAP simulatin fr the circuit f Fig. 2.18(a) with a 300 Hz cutff frequency when clcked at 128 khz.

33 53 54 Chapter 3 CONSIDERATIONS FOR THE MONOLITHIC MOS IMPLEMENTATION OF SWITCHED CAPACITOR FILTERS In the mnlithic MOS implementatin f switched capacitr ladder filters, there are several imprtant effects which must be cnsidered including: (1) The finite switching frequency f the sampled-data system; (2) nnidealities assciated V IN R VWV with the passive MOS switches and capacitrs, and (3) nnidealities assciated with OUT the peratinal amplifiers. These practical design aspects will be cnsidered in this chapter Sampled-Data Discrete-Time Effects Switched capacitr fillers are analg discrete-time systems which, in many cases, are derived frm cntinuus-time RLC prttypes. In this sectin, the effects f transfrming frm the cntinuus- t the sampled-data dmain are ( ) described Cntinuus-Time RC Integratrs 1-hMvOUT The cnventinal inverting integratr f Fig. 3.1(a) cnsists f a resistr, Rj, a capacitr, C, and an peratinal amplifier. The transfer functin fr this RC integratr is given by H(s) - - (A0+l)sR,C, + 1 (3.1) (b) with magnitude H(>) - [l +(A+O'CRA)2*2] T72" (3.2) Fig (a) A cnventinal cniinuus-time RC integratr; (b) a sampleddata switched capacitr integratr.

34 55 and phase <P(cu) - - it - tan-,&>r A(A0+1) (3.3) H(f) where A is the DC pen-lp gain fan therwise ideal p amp. The magnitude asympttes and phase f Eqns. (3.2) and (3.3) are pltted in Figs. 3.2(a) and (b), fn= 0" ZlTR^Cj respectively. Frm Fig. 3.2(a), it isevident that finite p amp gain results in a lssy integratr with an errr in the integratr bandwidth. T reduce this errr t less than 1%, the p amp is required t have A greater than 100, and when A0 is greater than 1000, the integratr gain cnstant errr is less than 0.1%. If A is infinite, the transfer functin f Eqn. (3.1) becmes H(s) - - =± s (3.4a) f A+1 (a).^'^ T VA+l r equivalently, -180 H(ai) - - t-2- (3.4b) with i>0=. RA The characteristics f analg sampled-data integratrs will be presented in the next sectin Discrete-Time Switched Capacitr Integratrs An imprtant difference between the cnventinal RC integratr f Fig. 3.1(a), and the switched capacitr integratr f Fig. 3.1(b) is that the latter usually nly samples the input signal nce each clck cycle. Hence, there can be a time delay thrugh the integratr f up t ne full clck perid. The excess phase shift assciated with this time delay can result in significant Q-enhancement if a switched capacitr integratr is used t directly replace a cnventinal RC integratr -240» -270 " < (f) Fig >-t \fa l (b) (a) The magnitude..nd (b) the phase plts fr an RC integratr with A representing the p amp DC pen-lp gain.

35 57 58 in an active ladder circuit. This phase shift can cmplicate the design, but mre imprtantly, can break dwn the analgy f the design with the RLC passive ladder prttype. If this happens, the lw sensitivity btainable with a dubly-terminated Fr the next half clck perid frm (n+l/2)tc t (n+l)tc, (i.e. during the sampling interval), the utput des nt change, which yields anther half cycle f delay. Therefre, the transfer functin f the integratr taken at the end f this ladder may be lst. Frtunately, the effect f this deleterius phase shift can be interval (at t-(n+l)tc) has a full cycle f delay in the frward path and is given by, almst cmpletely eliminated. In rder t analyze the effect f the time delay, it is useful t develp a z- transfrm mdel f the inverting integratr f Fig. 3.1(b) (assuming an ideal p amp) [38]-[39]. The switched capacitr, Cu, will be charged t the input vltage, Vm(t), at the beginning f each clck perid, and will be switched t the p amp virtual grund halfway thrugh each cycle. Therefre, at the beginning f the n,h clck perid (i.e. t«ntc), the switch is in the left psitin, and Cu has a charge Qc "CuVjnGiTc). The value f the utput signal at this time is stred as the H,(z) - - cu z"1 i-z"v This integratr is called the Direct-Transfrm Discrete Integratr (DDI) [42]. (3.7) The type-i Lssless Discrete Integratr f Eqn. (3.6) has exactly the same phase shift as a cntinuus-time integratr [42]. Hwever, the DDI integratr represented by Eqn. (3.7) has significant excess phase. T illustrate this result, the frequency respnses f H1/2(z) and Hj(z) are evaluated by setting z^e"" ' t btain charge, QC, n the integrating capacitr, C. Its value was determined a half cycle earlier at t=(n-l/2)tc and therefre, QC =C V0U,((n-l/2)Tc). At the next half Hi/2(i)» -r2- j* wtc 2sin(»-^-) (3.8) cycle time, t«=(n+l/2)tc, the switch is in the right psitin, and the capacitr Cu is discharged by the p amp as the charge is transferred frm Cu t Cj. The charge and n C is nw C,V0Ut[(n+l/2)Tc] - C,Vul[(n-l/2)Tc] - CuVjn(nTc). (3.5) H,(6,)--T^ jw T 6>Tcexp(-j)-^-) T 2sin(>-y-) (3.9) The transfer functin taken at this half cycle time, H1/2(z), is therefre Hwfc> - - cu c«z-l/2 l-z"v (3.6) where the subscript 1/2 indicates that there is nly 1/2 clck cycle f delay in the frward path f this integratr. An integratr with this half-delay prperty is knwn as a type-i Lssless Discrete Integratr (LDI) [42]. with cu0=fc These expressins are factred s that the term in brackets is the deviatin frm the respnse fthe cntinuus-time integratr given in Eqn. (3.4b). Table I shws that the sampling frequency must be large relative t the passband frequencies in rder t minimize the errr in the magnitude f the integratr bandwidth in Eqns. (3.8) and (3.9). (Fr the designs f this thesis, the clck frequency was typically 35 times greater than the maximum passband

36 59 60 frequencies s that the gain cnstant errr was 0.13%). Frm Eqn. (3.9), it is apparent that the DDI integratr has an extra phase NORMALIZED FREQUENCY ERROR IN f GAIN CONSTANT *C MAGNITUDE % , Table I. Magnitude errrs in switched capacitr integratrs versus nrmalized frequency. shift f -it radians in its transfer functin. If nly integratrs with this respnse are used in an active-ladder cnfiguratin, this phase shift is equivalent t intrducing finite Q in the inductrs and capacitrs which are being simulated. Hwever, the sign f this lss is ppsite t that which is btained in circuit ele ments due t parasitic resistances and cnductances, s that instead f a drp in the frequency respnse (which is usually assciated with finite element Q) the respnse exhibits peaking. In mst cases, this peaking is nt desirable s that the integratrs shuld be perated t eliminate the excess phase shift DDI Switched Capacitr Filters Withut Predistrtin As mentined in the previus sectin, if switched capacitr filters are imple mented directly using DDI integratrs, the filter respnse will exhibit peaking due t the Q-enhancement prvided by the excess phase. Fr example, a fifth-rder filter was designed fr a Chebyshev lwpass respnse with a 3.4 khz cutff fre quency, and a ttal passband ripple f 0.1 db when clcked at 128 khz. The simu lated DDI respnse f Fig. 3.3 shws a ttal passband peaking f abut 8dB, and a cutff frequency greater than 4.0 khz. The Q-enhancement is analyzed by cmparing the transfer functin f the cnventinal integratr f Eqn. (3.4a) t the DDI transfer functin f Eqn. (3.7) with its numeratr and denminatr multiplied by zfc [45]. The numeratrs f bth equatins crrespnd t integratr gain cnstants while the denminatrs specify a mapping frm the cntinuus- t the sampled-data dmain: s-fc(z-l)-fc(e,t«-l) Tc. (3.10)

37 «61 62 Cnsider a ple in the s-plane, pc-ac+jwci. Eqn. (3.10) can be used t calculate the new s-plane sampled-data ple psitin by slving fr pi"a{+}ut- t btain: gn K+fc 2 + II fc 1 2 1/2 (3.11) r. and fctan -i <*c+fc (3.12) 3-3 k-! i i Frm these equatins, it is apparent that finite sampling frequency causes significant ple mvement as indicated by the arrws in Fig Table II lists the ideal ple psitins fr the prttype Chebyshev cntinuus-time lwpass filter, and the s- plane sampled-data ple psitins calculated using Eqns. (3.11) and (3.12). It is il* > an j r z UV» SlA interesting t cmpare the values f ple-q fr the tw cases. Fr the cntinuustime case, Qc 2< (3.13) and after the sampled-data ple mvement, the ple-q is * $ (3.14) The values f ple-q fr the fifth-rder Chebyshev DDI switched capacitr exam i * Fig Passband respnse fr a fifth-rder Chebyshev DDI lwpass switched capacitr filter withut predistrtin. Q-enhancemcnt results in abut 8 db f peaking and increases the cutff frequency. Sampling frequency was 128 khz. ple at 128kHz are als presented in Table II where the Q-enhancement due t excess phase is clearly evident. The sensitivity f the peaked respnse f Fig. 3.3 was determined fr ±1% variatins an all capacitr ratis. The results f Fig. 3.5 indicate that the DDI

38 CT t/i w 3" re re rr **. re 3 * a. re 09 OS 3 i/i 0> </> 3 m "* -< Q. re -i C 3 re 3 re a re Q. O X 09 re t ^^ in to m OO X a as 3* 09 X 3 (A N T3 re re 03 v> i/i *-» n 09 ^ re cs a. 3) * < re 3* a re 3* re n O 3* re D "0 O en x y V TJ i m t > > t i T 70 m T» r* * i rn en < i z m g m > H > z > H -H m.j0. -v* II t I ^ t z m > X r- m CD TJ -< O t r~ X m m - < -d a r in (0 r~ X i -i i ^ - TJ X V t z TJ \"* m t» N X S ru -n 70 H TJ O r- m ON IS. p=.sn ^ J r% a. OS ~ / " "* 2. 5" i ri. 3 D 3 CONTINUOUS CASE NORMALIZED POLE POSITIONS j POLE Q DDI SAMPLED DATA CASE (128 KHZ) NORMALIZED POLE POSITIONS j POLE Q PREDISTORTED DDI SAMPLED DATA CASE (128 KHZ) NORMALIZED POLE POSITIONS j POLE Q ' re?j 2. 0 ^ 3- n g..sc a " 3 5' Hi 2 w _, =r a,.» * re re j j j j j j n 5. _, N> 3- J y 00 re 03-1 * * 3 - K " " 2" N 3" <» " ** I»as j? ' s ««~ -i re j j j j j j ,

39 " 0.0 PASSBAND DEVIATION (db) 1.01 <i,<5 peaked respnse has much greater sensitivity than the nminal respnse fthe pas- RLC prttype which cntradicts previusly published remarks [ ]. sive DDI Switched Capacitr Filters With Predistrtin The effect f finite sampling frequency is t increase the ple-q. One way t cmpensate fr Q-enhancement is t chse the initial cntinuus ple lcatins in such away that the sampling effect will mve them t the desired final psitins as.i " 0.0 PASSBAND DEVIATION (db) ^cx^^.99cx2,cx4 illustrated symblically in Fig Analytically, it is necessary t find the predistrted cntinuus ple psitins, pd-ad+ja>di in terms f the sampled-data ple psitins, p-t by letting s-pdi in Eqn. (3.10): ad-fc(ef«cs(y-)-l), 1 'c (3.15) and ' 0.0' PASSBAND DEVIATION (db) I.OICX3-0.5"' Passband sensitivity f the DDI peaked respnse in Fig. 3.3 t integratr gain cnstants fr the fifth-rder switched capacitr filler withut predisinin. Sample raic was 128 khz.,is the reciprcal gain cnstant f the i,h integratr. Fig )d -fce^sino^-). 1 *c (3.16) By setting Pj'=pCi, (i.e. the final sampled-data ple lcatins are equal t the desired cntinuus-time ple psitins) the crrect respnse is btained. Fr example, Eqns. (3.15) and (3.16) have been used t calculate the element values fr apredis trted fifth-rder RLC ladder prttype by multiplying the ples tgether t frm the denminatr plynmial, and then using this plynmial in acauer-type expan sin t extract the Land Cvalues 148). The nrmalized predistrted RLC netwrk is shwn in Fig. 3.7.

40 67 68 IDEAL POLE POSITIONS ON CHEBYSHEV ELLIPSE J6> A Ri L2 _mm_» 0-\\V\r-t-nrnrV "bi X-*XR C1?kCi ^tnc3 "1-^5 R2 x-*x?, Pn- Pn ARE THE D1 u5 PREDISTORTED INITIAL POLE POSITIONS fc =128 KHZ PASSIVE PREDISTORTED VALUES VALUES Ri 1 1 ->» cr NOTE: ARROWS INDICATE SAMPLED-DATA POLE MOVEMENT. R2 1 1 Ci 1.U L c X-^X P, L* c pd5 X-X P, *i- Fig Predistrtin f the initial ple psitins can be used t cmpensate fr the Q-enhancement effect which shifts the predistrted ples t their desired psitins. Sampling rate was 128 khz. Fig Fifth-rder dubly-terminated RLC prttype and the nminal and predistrted element values. Cmpulatins are based n a 128 khz sampling rate.

41 69 70 The predistrted switched capacitr fifth-rder lwpass filter has been simu lated at a 128 khz clck rate fr a ±1% variatin n all capacitr ratis with life results given in Fig Cmpared t the RLC prttype, the predistrtin has increased the sensitivity by abut a factr f 10. In the limit f higher clck rates, switched capacitr integratrs apprach cntinuus-time RC integratrs, and the sensitivity f the switched capacitr filter appraches that f the cntinuus prt 0.2JT db FIFTH ORDER CHEBYSHEV FILTER = 0.1 db SAMPLED DATA VERSION WITH 1*P=0.01 (AFTER OPTIMIZATION) Eg type. Hwever, as the clck rate increases, the required capacitr ratis als increase resulting in an area-sensitivity tradeff. which des nt require predistrtin is desired. Hence, a methd f filter design By using Lssless Discrete Integra trs, predistrtin can be avided in many cases, and nearly ideal sensitivity may be btained. The LDI filter prperties are described in the next tw sectins ; HZ 0.20t Type-I LDI Switched Capacitr Filters The phasing f the switched capacitrs f integratrs which are cnnected CU tgether determines whether the frequency respnse f the integratr is given by H1/2(c) r Hi(u). The tw integratr lp f Fig. 3.9 demnstrates the prper switch phasing required t btain the H,/2(») transfer functin. The signal at the utput f integratr 2 is available as sn as the switched capacitr is cnnected t the p amp, s in rder t avid the extra half cycle f delay (and the resulting H (b>) respnse), the switches f the first integratr must be phased t immediately sample that utput as shwn in the figure. Therefre, the switches f adjacent HZ integratrs shuld be thrwn in ppsite directins as shwn in Fig Integra trs which are clcked t achieve this half-delay prperty are used in the implemen tatin f what will be referred t as type-1 LDI switched capacitr filters. A cm plete schematic fr the type-i LDI dubly-terminated fifth-rder all-ple lwpass switched capacitr ladder filter is shwn in Fig Fig Passband sensitivity t integratr gain cnstants fr the fifth-rder DDI switched capacitr filter with predistrtin. Sampling rate was 128 khz. Integratrs 1 and 2.

42 T db [ HZ 0.20t HZ Fig Passband sensitivity t integratr gain cnstants fr the fifth-rder DDI switched capacitr filter with predistrtin. Sampling rate was 128 khz. Integratrs 3 and t 7- ±1% CU HZ Fig Passband sensitivity t integratr gain cnstants fr the fifth-rder?.\?ritched capaci,r fii,er w«l" Predistrtin. Sampling rate was 128 khz. Integratr 5.

43 73 7* Fig A tw-integratr lp which demnstrates the prper switch phasing required t btain the type-i LDI integratrs. Clck phases are alternated between stages. Fig A fifth-rder lwpass type-i switched capacitr dubly-terminated ladder filter.

44 75 The passband sensitivity f the filter f Fig has been determined fr ±1% variatins n all capacitr ratis. As shwn in Fig. 3.11, the wrst-case sensi tivity f the LDI netwrk is abut 5 times lwer than that f an equivalent predis trted DDI netwrk fr a 128 khz sampling frequency. Unfrtunately, the half-delay LDI realizatin uses the tp plates f the switched capacitrs as inverting integrating inputs, and therefre, the resulting fre quency respnse is slightly in errr due t the tp-plate parasitic. The LDI apprach described in the next sectin eliminates this surce f errr, and in addi tin, simplifies the clck phasing requirements Type-II LDI Switched Capacitr Filters By using nly the bttm plates f switched capacitrs as integrating inputs, the errrs due t tp-plate parasitics are eliminated since ideally, there is n vltage change n the tp plateduring switching, and the bttm plate is switched between vltage surces. The nninverting integratr f Fig. 3.12(a) has a z-plane transfer functin f -l H,<Z)- ^" Z Ci 1-z"1 (3.17a) which can be written in the frequency dmain as H,(c) - -r2- T wtjexphw-y-) T 2sin(<i>-^-) (3.17b) The circuit f Fig. 3.12(b) perfrms the inverting integratin functin with the z- plane transfer functin f Fig Passband sensitivity fr ±1% variatins in -zr- which is the wrst-case fr the filter f Fig Sampling rate was 128 khz. 76

45 77 78 H«(z) - - -i 1-z (3.18a) which can als be expressed, as vout H0(c) - - -r* T cutcexp(+w-^-) T 2sin(<u-^-) (3.18b) It can be seen frm Eqn. (3.17b) that the nninverting integratr has excess V, INO /^*. phase-lag while the inverting integratr f Eqn. (3.18b) has a phase-lead respnse. These integratrs will be used in the implementatin f type-ii LDI switched capa citr filters. A tw-integratr lp using type-ii LDI integratrs is shwn in Fig By using the same clck phasing n bth stages, the leading and lagging phase cm pnents cancel arund the lp, and the crrect frequency respnse is btained. The cnsideratins fr synthesis f type-ii LDI filters are slightly different OUT than fr the type-i case. Fr the type-ii designs, it is desirable t synthesize the I -/v* V N (b) circuits s that the signs f the integrating inputs alternate between stages, i.e., all even stages psitive and all dd stages negative r vice-versa. This sign alternatin allws fr the same clcking n all stages, is cnsistent with existing ladder syn thesis appraches (491- (501, and prvides a direct relatinship t the DINAP simu latin methds t be discussed in Appendix 3. A type-ii LDI fifth-rder all-ple lwpass filter is shwn in Fig (Refer t the crrespnding type-ii LDI flw Fig (a) Type-11 nninverting and (b) inverting switched capacitr integratrs. Bttm plates are used as inputs t eliminate errrs due t the lp-plate parasitic. diagram f Fig. 2.6(c)). Several wrkers are independently investigating the use f type-11 LDI integra trs fr telecmmunicatins applicatins; early indicatins are that excellent results will be btained with this apprach ( ].

46 00 a Q -1 t + ' Ii«r* 1 en SO i^ *tf CM H M TJ u. -O 4> CO * E \ 00.i 2 " ^e^t ID u Hi- O SO E > at a» '.E *G _ c 2 "5 "> 2 ft n C n 2 «> c = "T "O ea O «w cr _ < 2f 3

47 LDI Switched Capacitr Filters With Predistrtin As mentined earlier, bth the DDI and LDI integratrs experience a fre quency dependent magnitude errr. Table 1shws that when the signal frequency appraches the Nyquist rate, -y, the errr in the integratr gain cnstant appraches 57%! Hence, it is bvius that fr high frequency (relative t the sam pling frequency) switched capacitr filters, the magnitude errr must be cmpen sated by using predistrtin. The type-i LDI transfer functin f Eqn. (3.6) maps a cntinuus s-plane ple int a sampled-data s-plane ple by the transfrmatin s ft[z,/2-z-1/2j - 2f^inh s (3.19) 2fc With s-ad+jtdd(, and s'-oi'+jij', Eqn. (3.19) is slved t btain: Switched Capacitr Filters with Multiple Sampling Rates In sampled-data systems such as switched capacitr filters, ne f the mst difficult practical prblems is the requirement fr a cntinuus-time antialiasing prefilter. The prefilter specificatins are reduced by sampling at many limes the passband frequencies, but unfrtunately, this higher sampling rate results in larger capacitr ratis. An ptimum slutin t this prblem is t perate the first stage (s) f the filter at a very high sampling rate t ease the prefilter requirements, and t perate the ther stagescs) at a lwer clck rate in rder t simultaneusly reduce the silicn area requirements. This apprach has been verified by DINAP simulatin fr a third-rder Che byshev lwpass filter with a 3.4 khz cutff and 0.1 db passband ripple. In Fig. 3.15, the first stage is switched at MHz, and the secnd and third stages are switched at 128 khz. The switches are perated t btain zer excess phase shift and di - 2fcCOS CDj' sinh (3.20) arund all interir tw-integratr lps, which requires that the secnd stage in this example has its tw switched capacitrs perating at tw different sampling rates as shwn in the figure. The DINAP simulatins shwn in Fig agree clsely with the expected values. -<-jtf"g csh (3.21) 2fc By letting pj' pv Eqns. (3.20) and (3.21) can be used t calculate the predis trted LDI ple psitins. This predistrtin technique can als be used t cm pensate fr ther types f nnidealities such as finite p amp gain. This technique can als be used t prvide a high sampling frequency stage(s) at the utput f the switched capacitr filter s that cntinuus-time pst filtering, if necessary, becmes easier Passive Cmpnent Nnideal Effects In this sectin, the effects f nnidealities assciated with the passive filter ele ments will be cnsidered (25],[46].

48 Vi Ll>LUf /e I&5TL Lfc r im yjjj^^ C >TN <~V <> - v3=v0ut Fig A third-rder lwpass type-ii LDI switched capacitr filter with tw different sampling frequencies. 83 Bk.1U z -J m «-j i i es -X J>- 3 at JC JO < I 9.JC > <r -» O y A O m 3rj M a n an 0 lo» n n N * -» «in O 9 rj 0» s A) Fig (a) The DINAP respnse fr the circuit f Fig with 128 khz and MHz sampling rates.

49 n I ez MOSFET Channel (Switch) Resistance Finite MOSFET switch resistance limits the rate at which charge is transferred thrugh a switched capacitr circuit. In rder t islate this effect frm pamp set tling effects (which will be shwn t be dminant), it will be assumed that the p amp in the switched capacitr integratr f Fig. 3.17(a) is ideal. During the sam pling interval, d«,, the charging netwrk can be represented as the series RaveCu cmbinatin shwn in Fig. 3.17(b) where R,ve is the average switch resistance. Fr an input vltage f AVj,,, the vltage n Cu at the end f the sampling interval is I I Vu(T,)-AVin(l-e R'"c") (3.22) «v X- u where T, isthe "n" timef «>,. The charge n Cu after 0, is X it X 1 t, QU(T,) - CUVU(T,) - CuAV^l - e_r-c-). (3.23) OS During the integratin phase, <f>2t the p amp attempts t transfer the charge frm Cu t Cj as indicated in Fig. 3.17(c). The vltage n Cu after the integratin inter val, T2, is! VU(T2) - Vu(T,)e R~c" (3.24a) with a charge f * r> Z 3*. «an -Ti QU(T2) - CUVU(T2) - CuVu(T,)e R-c-. (3.24b) Fig (b) The DINAP passband respnse fr the circuit f Fig The ttal change in charge n Cu during ne cmplete clck cycle, AQU-QU(T,)- Q (T2), is given by AQ0 - CuAVt(l - e ""Sd-e R""c"). (3.25)

50 87 88 Since AV0U1-2-, the integratr gain is AV, - * fl-.«>(!-. «*>. (3.26) Hence, incmplete charge transfer due t nn-zer switch resistance is equivalent t a capacitr rati errr. If the values f T, and RaveCu are chsen s that the errr is less than 1%, Eqn. (3.26) suggests that Ts shuld be greater than 5.3 RlveCu time cnstants, while fr a 0.1% errr, 7.6 time cnstants are required. Fr the designs fthis dissertatin, the Tt intervals were typically 75 time cnstants making this effect negligible in cmparisn t settling errrs which will be described later MOSFET Nnlinearity and Threshld Vltage Effects Since the MOS transistrs are being used as charge switches, nnlinearity in the channel resistance is unimprtant prvided that the charging and discharging intervals are sufficiently lng. Hwever, the threshld vltage f the switches must be carefully cnsidered. As an illustratin f this pint, suppse in Fig. 3.17(a) that Cu is initially at 0 vlts when *, and V^ are cnnected t VDD. When Vu has risen t within a threshld vltage f VDD, the switch transistr turns ff. Hence, the input signal may be clipped, resulting in a decrease in the dynamic range f the filter. In single channel MOS technlgy, btstrapped clck drivers can be used t vercme this prblem, and in CMOS technlgy, transmissin gates can be used t btain full vltage swings. V, IN V in Cu^k - (a) - Rave WW (b) - u -v0ut VQUT Fig (a) A switched capacitr integratr, and the RC circuit mdels fr (b) the sampling phase, and (c) the integratin phase.

51 MOSFET Channel-Resistance Thermal Nise Nise will be cnsidered in Chapter 4. *i 4>: Capacitively-Cupled Clck Feedthrugh A switched capacitr integratr is shwn in Fig. 3.18(a) including the gatesurce and gate-drain capacitances fr the MOSFET switches. The 0, clck signal is effectively islated frm the p amp by M2 s that it des nt affect the utput. Hwever, as shwn in Fig. 3.18(b), CGDj cuples a prtin f <f>2 nt the utput which appears as a DC vltage with its magnitude dependent n when the utput is sampled by the next stage [53]-[54]. Fr example, if the utput is sampled n <f>2 (as in type-i LDI filters), the utput vltage is smewhere between 0 vlts and Cxj^DD Tf.. If the utput is sampled after <,, the rising and falling feedthrugh ZL-i GSp-p [CGDjCGSrfN CGd- - V, N M -f <> u ^C u (a) cmpnents apprximately cancel, and the utput DC ffset vltage is very small. Fr the metal-gate NMOS prcess used in the prttype circuits f Chapters 5 and 6, the clck feedthrugh step size was abut 75 mv. Other wrkers have bserved *i_y^~a J v_ less than 10 mv f clck feedthrugh fr silicn-gate NMOS realizatins f switched capacitr filters [57]. & / \ Junctin and Surface Leakage Currents Since the leakage currents are integrated by the switched capacitr integratrs, the circuit can eventually saturate. T prevent this frm happening, it is necessary t prvide a discharge path fr IL as in Fig. 3.19(a) where a switched capacitr resis tr is cnnected in a negative feedback lp between the input and the utput. This feedback path places a negative charge n Cu during </>, which resets the integratr during 4>2 as shwn in Fig. 3.19(b). The effect f this leakage current is t cause a DC ffset vltage at the integratr utput with its magnitude dependent V, OUT Fig X > (b) (a) A switched capacitr integratr with parasitic switch capaci tances; (b) signal wavefrms shwing clck feedthrugh.

52 91 92 n when the utput is sampled. If the utput is sampled at the end f <f>2 as in the 1 J~L type-i LDI integratrs, the ffset crrespnding t time A in Fig. 3.19(b) is 'OS, C ' (3.27) Vu?fcCu IL(t) r where t is the pulse width f <J>2. crrespnds t pint B in Fig. 3.19(b) with a magnitude f If type-ii LDI r DDI clcking is used, the ffset (a) 1l(T+t) 2C, (3.28) Therefre, the ffset fr the type-i integratrs is slightly less than in the ther tw cases. The minimum sampling rate is determined by the leakage currents and their resultant ffset vltages. The vltage drift in Fig. 3.19(b) is typically abut 10 mv/sec, assuming a 1 pf capacitr, 100 fim7 f junctin area, and a thermal leakage current density f 10 na/cm2 [55]. This effect limits the minimum sam pling frequency t a few hundred Hz MOS Capacitr Rati Errrs As mentined previusly, the passband respnse f the dubly-terminated RLC ladder filter is insensitive t cmpnent variatins when there is maximum pwer transfer between input and utput. The fifth-rder type-i LDI switched Fig (a) A switched capacitr integratr with negative feedback t stabil ize against the leakage current, and (b) the crrespnding vltage wavefrms. Effective ffset depends n sampling instant at the utput. capacitr lwpass ladder f Fig has been simulated fr ±1% variatins n all integratr capacitr ratis with a nminal Chebyshev design having a ttal passband ripple f 0.1 db, and a cutff frequency f 3.4 khz when clcked at 128 khz. Fig shws that the wrst-case deviatin in the passband is nly ±0.022 db which is in clse agreement with the sensitivity f the passive RLC prttype.

53 93 9* Previus wrk has shwn that mnlithic capacitrs can easily be matched t within a few tenths f a percent rati accuracy (21), and hence, the passband variatins Fr typical perating vltages, this errr is negligible. Fr example, if V0 0 vlts, Vjn-s-5 vlts, and Vu,-5 vlts, the resulting rati errr is nly 0.01%. due t capacitr rati errrs will be extremely small fr mnlithic MOS realiza tins Parasitic Capacitances If DDI r type-i LDI cnfiguratins are used, it is imprtant t cnsider the MOS Capacitr Temperature Cefficient The temperature-dependent MOS capacitance value can be linearly apprxi mated abut a nminal temperature, T0, by C(T)-C(T0)(l+a(T-T0)) (3.29) parasitic capacitances assciated with the inverting (upper as drawn) and nninvert ing Qwer as drawn) plates f the switched capacitr, Q,, labelled CA and CB, respectively as shwn symblically in Fig. 3.20(b). First, cnsider the bttm-plate parasitic, CB, which will be charged t V2 when the switches are thrwn t the left. When the switches are subsequently thrwn t the right, CB is discharged t where the temperature cefficient, a, is typically 25 ppm/ C [21]. The grund, and thus has n effect n the charge stred n Cj. On the ther hand, temperature-dependent capacitance rati is therefre CU(T) Cu(T0)(l + a(t-t0)) C^ C,(T) " C,(T0)(l +a(t-t0)) " C, (3.30) when the switches are t the left, the tp-plate parasitic, CA, is charged t Vlt and when the switches are thrwn t the right, CA is discharged nt the integrating capacitr, Ct. Hence, CA cntributes an errr charge whse effect must be minim shwing that first-rder temperature variatins cancel, leaving the mnlithic MOS capacitance rati independent f temperature MOS Capacitr Vltage Cefficient The vltage-dependent mnlithic MOS capacitance expressed abut a nmi nal perating vltage, V0, is C(V)-C(VO)(1+0(V-VO)) (3.31) where the vltage cefficient, /S, is typically -10 ppm/vlt (metal ver n+), and the vltage-dependent capacitance rati is cu(vt) cu(y0)(i+(hvm-v0)) ct(ym) " qtag+bfa^-v)) (3.32) ized in the DDI r type-i LDI filter design. Figure 3.20(c) shws the simulated effect that the tp-plate parasitic capaci tance has n the frequency respnse f the fifth-rder Chebyshev type-i LDI lwpass filter. When CA-0, the ideal respnse is btained as in the upper trace. (All ther parameters are assumed ideal.) The lwer trace f Fig. 3.20(c) is fr the case when CA-0.01CU. In this case, there is a DC gain errr f 0.25 db, and a slight peaking in the respnse f 0.05 db. The amunt f this peaking errr which can be tlerated fr a given applicatin usually determines the minimum size f C relative t the tp-plate parasitic. Fr typical mnlithic MOS lwpass realizatins, Cu ranges frm abut 0.5 t abut 2.5 pf. (Fr highpass structures with large capa citr ratis, Cu may be as small as pf [51],[56]).»

54 95 96 The tp-plate parasitic als results in a multiplicatin f the amplifier ffset vltage. In Fig. 3.20(b), suppse that V,-0, V2-Vu and that the amplifier has * *2 i (a) vl ^ OUT CA?fc icu r- V20 <^^ i If J*? (b) OUT an ffset vltage f Vs. Fr this situatin, the DC ffset vltage at the integratr CA utput is VsO-l- ). If Cu becmes very small relative t CA, this multiplicatin can significantly increase the effective utput ffset vltage, althugh this effect is nt usually imprtant if Vs is small Nnidealities Assciated with the Active Cmpnents This sectin will cver sme f the mre imprtant effects assciated with the peratinal amplifiers. c) i fi 4 D.U ^\ /ca= ' X CA =0.01 Cy <, GAIN db (c) Fig (a) A type-1 switched capacitr differential integratr, and (b) a symblic representatin shwing parasitics; (c) effects f tp-plate parasitic n respnse f fifth-rder Chebyshev lwpass filter. Sam pling rate was 128 khz. Hz Operatinal Amplifier DC Open-Lp Gain A switched capacitr integratr is implemented using a differential amplifier, which in the case f Fig. 3.21, has an pen-lp DC gain f A^ Ideally, A<, is infinite, and the integratr has a ple at the rigin in the s-plane as shwn in Fig (b). Hwever, if A0 is finite, the effect is t prduce a lssy integratr by mving the ple away frm the imaginary axis as indicated by the arrw. Fig. 3.21(c) shws the simulated (DINAP) effect that p amp-dc gain variatins have n the frequency respnse f a fifth-rder Chebyshev lwpass filter which has the nminal respnse f Fig. 3.20(c). In the lwer trace, all five p amps have an pen-lp gain f 100. In this case, the filter has a DC gain errr f 0.22 db with a passband drp f 0.09 db due t the ples being pushed away frm the imaginary axis. In the upper trace f Fig. 3.21(c), all five p amps have a pen lp gain f 1000, and the filler respnse shws a DC gain errr f nly 0.02 db. Hence, it can be cncluded that p amps with gains f 1000 can be used t realize switched capa citr lwpass ladder filters with very accurate respnses when the ple Q*s are

55 97 98 small (<10). Fr high-q realizatins, the p amp DC gain is required t be pr prtinately higher. This will be treated in greater detail in Chapter 6. If peratinal amplifiers with a DC gain f less than 1000 are used, predistr (A) tin techniques similar t thse presented in Sectin can be used t cmpen sate the respnse fr the expected gain errrs. Hwever, the amplifier gain shuld A = 100 / A = c nt be made arbitrarily small since the sensitivity f the ple psitins t gain is OUT apprximately, and therefre, fr small A,,, typical prcessing variatins wuld make it difficult t btain a reprducible respnse. (a) (b) Operatinal Amplifier DC Offset Vltage Fig shws that each switched capacitr integratr in the active ladder cnfiguratin is embedded in a negative feedback lp, which defines a stable bias pint even in the presence f p amp DC ffset vltages. In terms f the verall j l 3000 L -Hz filter, the individual integratr ffsets cntribute t a DC ffset vltage at the ut put f the filter which is given by v - 2VC i-l (3.33) where n is the ttal number f integrating stages, and V^ is the DC ffset vltage f the i* stage. The ffset fr each integratr depends n a number f factrs including leakage currents, clck feedthrugh, clck phasing, tp-plate parasitics, and the individual amplifier ffsets as described earlier. Fig (a) Switched capacitr integratr with finite p amp gain; (b) integratr ple psitin versus A(l; (c) effect f pen-lp DC gain n respnse f fifth-rder Chebyshev lwpass filler. Sampling rate was 128 khz.

56 Cmmn-Mde Range and CMRR In switched capacitr integratrs, the psitive input terminal f the differential amplifier is always cnnected t a DC bias vltage. Hence, there is n steady-state cmmn-mde input signal, and therefre the input cmmn-mde range and As shwn in Fig. 3.22(b), the ttal available respnse time, t, cnsists f a slewing time, tslew, and a settling time, tml. Since the settling time is apprximately cn stant, the allwable slewing time is CMRR are nt imprtant parameters. T (3.37) Amplifier Slew-Rate Hence, the required p amp slew-rate is The required p amp slew-rate perfrmance is determined by several different factrs: (1) The maximum rate f change f the integratr utput signal; (2) the sampling frequency, (3) the duty cycle f the clcks, and (4) the clck phasing SR l$lew "Vp,_Js. T (3.38) which determines when the utput is sampled. The switched capacitr integratr f Fig samples the input during d»] and integrates during <f>2 as shwn in the tim ing diagram. It will be assumed that Vut is sampled at the end f <f>2 (which represents the wrst-case) s that the ttal time available fr slewing and settling is t, where T-kdT depends n the duty cycle. Neglecting sampling fr the mment, the utput signal can be represented as where it is assumed that r>tset. Fr example, fr a 3.4kHz signal with a 3 vlt peak, tuvp=0.064 vlts//isec. If kd-0.25 (25% duty cycle), and half f the integratin time is allwed fr settling, -0.5, then the required slew-rate is 0.51 vlts//isec. The prttype filters t be described in Chapters 5 and 6 used an NMOS peratinal amplifier with a measured slew-rate f 1 vlt//isec. ^^uift)-vpsin(>t) (3.34) 3.3.r Anr.Aiiifier Settling Respnse which has a maximum rate f change at»0 f (3.35) Therefre, the maximum change in the utput during ne clck perid is depen dent n the sampling frequency and is given by K'L-"< VpT--^ (3.36) Cnsider a switched capacitr integratr which uses a tw-ple amplifier with a lw frequency gain f Aq and a dminant ple at p,: A(s) dvm(t) dl L p Pi 1+i P2 (3.39) During the sampling interval, the capacitr C, stres theutput vltage, and the p amp is an pen-lp cnditin. During the integratin phase, the circuit can be mdelled as a charge multiplier respnding t a step input. The transfer functin

57 fr the circuit f Fig. 3.23(a) is i-^v( VQUT H(s) 1+ 1 * T(s) (3.40) where T(s) is the lp-gain f the charge multiplier, ( ) T(s)- 1+ _s_ C,A0 Cu+C, Pi 1+ _s_ P2 (3.41) *J +: r0ut Fig J T l^-r-h SLEWING TIME H H" t SLEW SETTLING TIME H (b) / h- t SET (a) A switched capacitr integratr, and (b) the vltage wavefrms defining the slewing and settling times. The step respnse f the circuit depends n the lcatin f the clsed-lp ples in Eqn. (3.40) which are derived as»1,2 P1+P2 ±^[4p,P2(l+T0)-(p,+p2)2]l/2, (3.42) where T0 is the lw frequency lp-gain, CA trt0 Cu+C, A rt-lcus plt is shwn in Fig. 3.23(b). The ples becme cmplex when T _ (P2~Pi>2 _ P2 0" 4p,p2 4p,' (3.43) (3.44) which is typically abut 500 fr NMOS designs. Since the actual lw-frequency lp-gain is usually abut 1000 (A0 ), the transient respnse will be cmplex. The ple psitin, p2, is ften dependent n lading, and therefre, the details f the step respnse shuld be cnsidered fr the wrst-case stage within the filter. In general, settling time is the dminant cnsideratin in determining the maximum

58 sampling frequency fr a switched capadtr filter. V, IN> Cu VfJUT (a) Jj -Pi AP,P2 (b) Fig (a) A mdel fthe switched capacitr integratr during the integra tin lime; (b) rt lcus plt f the ple psitins during the integratin time.

59 Chapter 4 DYNAMIC RANGE CONSIDERATIONS FOR SWITCHED CAPACITOR FILTERS The dynamic range f a switched capacitr filter is defined as the rati f the RMS utput vltage at a given ttal harmnic distrtin (THD) level t the ttal RMS nise vltage within a specified bandwidth. Fr example, in telephny appli catins, the maximum signal level is 3 db belw the 1% THD signal level, and the RMS nise vltage is measured in the c-message band which extends frm 300 Hz t 3.4 khz. The harmnic distrtin generated by a switched capacitr integratr is deter mined by the linearity f the peratinal amplifier, and by the peak signal level at the utput nde f the integratr. The nnlinearity f the MOS capacitrs als cntributes t distrtin, but since the capacitr vltage cefficient is typically very small (10 ppm/vlt fr metal ver n*), THD is usually dminated by the pera tinal amplifiers. There are tw surces f nise in an MOS switched capacitr integratr: (1) The nise f the MOS peratinal amplifier, and (2) the thermal nise gen erated by the switches which frm the switched capadtr resistrs. The nise at the utput f a switched capadtr filter is determined by the RMS sum f the nise cntributins frm each f the integratrs. In this chapter, techniques are presented fr maximizing dynamic range while minimizing the silicn area require ments Harmnic Distrtin in a Switched Capacitr Integratr The gain transfer curve f a typical NMOS peratinal amplifier is smewhat nnlinear as shwn in the enhancement-depletin example f Fig. 4.1(a). The p amp nnlinearities give rise t harmnic distrtin in a switched capadtr integratr which depends n the peak utput signal level. In this sectin, a methd f analyz ing lw-level harmnic distrtin in a switched capadtr integratr is presented. The type-i inverting switched capacitr integratr f Fig. 4.1(b) is imple mented with an MOS peratinal amplifier which has a DC pen-lp gain f A which is a functin f the DC utput vltage as shwn in Fig. 4.1(a) and in Table I. The z-pla". transfer functin f this inverting integratr including gain effects is given by H(z) - - A+l+-^ Ci - A+l and by setting z-e*"1, the magnitude f the integratr transfer functin is btained: (hu) A+l+-^ +[A+l]2-2[A+l] A+l+-^- T17Tcs()T) An analytical evaluatin f harmnic distrtin based n Eqn. (4.2) is quite cmpli (4.1) (4.2) cated. Frtunately, THD can be estimated by using the cncept f differential gain errr which invlves calculatin f the relative gain change at a given utput vl tage with respect t the gain at a quiescent utput vltage (65). differential gain errr is defined as The psitive E*- ^52 (4.3)

60 i 6 VOLTS v0ut SMALL SIGNAL INTEGRATOR (VOLTS) GAIN GAIN AT f 'DD - vss = BB (a) ' V, IN 6>"V*- O O QUI v0ut * (b) Fig (a) Open-lp gain transfer characteristic fr the enhancementdepletin NMOS p amp f Chapter 5; (b) A type-i inverting switched capacitr integratr where the p amp has the gain charac teristic given in (a). Table I. The p amp pen-lp gain, and the integratr gain as a functin f the utput vltage level.

61 and similarly, the negative differential is E--G^G. (4.4) where fr this example, GQ is the integratr gain at zer vlts utput, and G"*" and G~ are the integratr gains at the maximum psitive and negative excursins f the < UJ Q_ > h utput signal, respectively. The secnd and third harmnic distrtin terms are cal culated by using the fllwing equatins: HD2 - I(E+-E") (4.5) V Q X CO CO and HD3 - r7(e*+e-). 24 (4.6) _ "c4 These equatins are valid at small distrtin levels where HD2 is prprtinal t the utput signal, and HD3 is prprtinal t the square f the utput signal. The distrtin perfrmance f the switched capacitr integratr f Fig. 4.1(b) *- at f0-3.2 khz with a 128 khz sampling rate has been calculated using the methd described abve. The integratr gain at f0 (which is ideally ne) was calculated using Eqn. (4.2) with the results shwn in Table I, and then using Eqns. (4.3) thru (4.6), the secnd and third harmnic distrtin terms were calculated as shwn in Fig When the peak utput appraches 4.0 vlts, the harmnic distrtin increases significantly s that the differential analysis described abve can n lnger < i ^ HARMONIC DISTORTION (db) O CO be used. Fig. 4.2 is in gd agreement with the experimental results presented in Chapter 5 which shw a dramatic increase in distrtin fr a similar peak vltage. Fig Secnd and third harmnic distrtin fr the switched capacitr integratr using the p amp characteristic f Fig. 4.1.

62 Ill Scaling Techniques fr Switched Capacitr Filters The dynamic range f a switched capacitr filter with mre than ne integra tin stage is maximized by scaling the circuit s that the peak utput vltage levels are the same fr each f the integratrs [66]. Several different scaling techniques are presented in this sectin alng with a brief discussin f the basic nisedistrtin-silicn area tradeffs Impedance Scaling An RLC prttype circuit is impedance scaled by a factr f k using the fl (a) lwing relatinships [43]: Ri krj (4.7a) and Lj-kLj (4.7b) k VOUT Cm- (4.7c) (b) The effect f impedance scaling is illustrated by cnsidering the secnd-rder RLC prttype shwn in Fig. 4.3(a). The current flwing in this circuit befre scaling is I(s) sc s2lc+src+l Vin(s) (4.8a) and the utput vltage is given by VOUI(s) - 1 s2lc+src+l Vin(s). (4.8b) Fig A singly-terminated secnd-rder RLC filter (a) befre and (b) after impedance scaling. The scaled versin f this circuit btained using Eqn. (4.7) is shwn in Fig. 4.3(b). The value f the current flwing in this circuit is fund by substituting the scaled

63 element values int Eqn. (4.8a) t btain In rder fr the magnitudes f Eqns. (4.10a) and (4.10b) t be equal, the circuit must be impedance scaled by a factr f k 1/2 I(s) -f sc s2kl ShHIf Vin(s) - f k + 1 s2lc+src+l V, (s) (4.9a) A., estimate f the silicn area required t implement a switched capacitr ver sin f the scaled RLC prttype f Fig. 4.3(b) can be made by assuming that the and similarly, the utput vltage is btained frm Eqn. (4.8b) as VOUI(s) Vin(s) Vin(s) '!M[f]~M[ +1 s2lc+src+l (4.9b) area is dminated by the integrating capacitrs fr the L and C stages. The ttal area required is prprtinal t the capacitance rati Area a ^ C fc kl+ k (4.11) It is apparent frm Eqns. (4.8) and (4.9) that impedance scaling reduces the current by a factr f k while the vltage level is unchanged. In a similar manner, all inductr currents in a high-rder filter are reduced by a factr f k due t where L and C are the nrmalized element values fr a cutff frequency f 1 rad/sec and cc is the desired cutff frequency. The area f Eqn. (4.11) is minimized fr a scaling factr f impedance scaling while all capadtr vltages remain unchanged. The dynamic range is maximized by scaling the filter s that all internal 1/2 (4.12) integratr utputs have the same peak amplitude [17],[66], A switched capacitr implementatin f the scaled circuit f Fig. 4.3(b) has ne utput vltage which is directly prprtinal t the inductr current, I (bandpass utput), and anther ut put which is equal t the capacitr vltage, Vu, (lwpass utput). Fr Q»l, the maximum lwpass utput vltage fr the circuit f Fig. 4.3(b) ccurs at the fre quency «0-[LCrl/2 and is Ntice that fr this example, the scaling factr which ptimizes dynamic range als minimizes the silicn area required. Fr high-rder filters, it is generally true that thse cnditins which maximize dynamic range als minimize the required die area. The impedance scaling technique described abve simultaneusly reduces all inductr currents by k. Unfrtunately, fr high-rder filters, the peak inductr (max) - 1 1/2 (4.10a) currents are generally nt equal befre scaling, and therefre after scaling, the peak amplitudes will still be different since all currents are equally affected. Thus, and the maximum bandpass vltage, Vu crrespnding t I is V QUI #.. v 1 "VT(maX> " kr (4.10b) althugh impedance scaling wrks well fr secnd-rder filters, it is nt generally applicable fr ptimizing dynamic range in high-rder filters. A switched capacitr scaling technique which can be used t independently scale all internal ndes

64 U5 116 representing either vltages r currents is presented in the next sectin. Vn-2 Vn Switched Capacitr Nde-Vltage Scaling A sectin f an unsealed type-i LDI switched capacitr ladder filter is shwn in Fig. 4.4(a). In the z-dmain, the three unsealed utput vltages are as fllws: (4.13a) Vn(z) - ^]K,<Z>-Vn+l< (4.13b) and Vn+2 V.,(z) - f C 'n+l f^r][vn(z)-vn+2(z)]. (4.13c) As an example, assume that it is desired t scale the vltage Vn by a factr f k withut affecting the ther utput ndes, s that after scaling, VB(z) ll# M-~H (4.14) Frm this equatin, it is apparent that the vltage at any nde can be scaled by sim ply changing the gain cnstant fr that integratr, i.e., Cn-*kCn. In additin, if a nde is scaled by k, the inputs driven frm that nde must be scaled by in rder t insure that the ther integratr utputs are unchanged. Fr the previus exam ple, this requires that kfccu,-1/2 Vn.2(z) - cn_,.»-*"'. c _, l"2"1 1 v -,fc>f«c z-,/2 VB(Z) (4.15a) Vn-1 (b) Vn+1 Fig A sectin f a switched capacitr ladder filter (a) befre and (b) after nde-vltage scaling.

65 and Vn+1(z) kfccu 2-l/2 V (z) [ftcu z-l/2 1 n+j 1-z-' k Cn+t 1-z"1 (z). n+2 (4.15b) Eqn. (4.15) shws that all f the switched capacitrs driven frm a scaled nde, Vn(z) -. are changed t a value f kcu. Fr example, if a nde vltage is halved (k 2), then all switched capacitrs cnnected t that nde are dubled. The switched capacitr sectin after nde-vltage scaling is shwn in Fig. 4.4(b). In general, tw additinal switched capacitrs are added fr each scaled nde, and if k is nt an integer, the capacitr matching accuracy between the different sized switched capacitrs is slightly reduced. Fr bth nde-vltage scaling and impedance scaling, there is a tradeff between nise and signal level (distrtin). This tradeff is illustrated by assuming nde Vx relative t the input. Hence, the first term determines the nise perfr mance, and the secnd term determines the distrtin perfrmance. Ntice frm Eqn. (4.16b), that as the nise gain is increased by k, the peak amplitude at Vx is reduced by k and vice-versa. Thus, there is a direct tradeff between nise and dis trtin, and it is fr this reasn that the peak amplitudes are set equal fr all stages in rder t maximize dynamic range Switched Capacitr Lp Scaling Fr bandpass and bandreject RLC filters, the relative spread in the LC ele ment values rapidly increases as the seleaivity increases. Fr example, cnsider the RL lwpass prttype shwn in Fig. 4.5(a). Applying the lwpass-t-bandpass transfrmatin f Chapter 2 results in the circuit f Fig. 4.5(b) where the bandpass reactive values are given as that the gain frm the input t the utput f the filter is cnstant. Fr an arbitrary internal nde, Vx, the fllwing relatinships apply fr the unsealed and scaled ver QLn 0>n (4.17a) sins, respectively: v VOUI fvx v K. (4.16a) and Cn- QLnw0' (4.17b) and v VOUl vx k kvu, 1 vx 1 vt 1 V*, kvm (4.16b) Frm these equatins, it is apparent that the rati f -~ increases in prprtin t CB Q2 which is very undesirable because in a switched capacitr implementatin, it results in a similar spread in the required capacitr ratis. In additin, if this net k wrk is nt scaled, the peak current remains cnstant fr a fixed terminatin resis The first term in bth equatins is a measure f the nise gain frm Vx t the ut put f the filter, and the secnd term represents the magnitude f the peak signal at tance while the peak capacitr vltage increases in prprtin t Q. Thus, the dynamic range is significantly degraded fr high-q applicatins.

66 A signal flwgraph fr the RLC bandpass prttype f Fig. 4.5(b) is shwn in R AA/W- Fig. 4.6(a). The current, I,, is given by I,-^M-1 (4.18a) n which can als be written as (a) R WW- Il"T QLn QLn QLn (4.18b) Thus, all inputs t the Ii integratr have been divided by QLn and the integratr gain cnstant has been changed t &>0. Similarly, the lwpass utput vltage, V2, is written as LD= QL n B D, V,- Q"Lr I. (4.19a) r equivalent^, icb= QOnL "-n *M- (4.19b) Fig (b) (a) Asingle-ple RL filter, and (b) a bandpass circuit btained using the lwpass-t-bandpass transfrmatin. Thus, the input f the secnd integratr has been multiplied by QLn, and the gain cnstant has becme w0. Using Eqns. (4.18) and (4.19), an equivalent signal flwgraph is drawn in Fig. 4.6(b). At this pint, the drcuit has been rearranged s that the integratr gain cnstants are equal. Hwever, fr maximum dynamic range, the peak amplitudes must still be scaled t be equal. Frm Eqn. (4.10a), the maximum lwpass utput vltage is fund t be V2(max) - I 1/2 QLn R (4.20a) and the maximum bandpass current is

67 I,(max) - tj-. (4.20b) In rder fr these peak amplitudes t be equal, the lwpass utput must be reduced by a factr f QLn as fllws: QL QL I, QL ^ (4.21) 1-1/QLn V? where V2 is the scaled lwpass utput vltage. The input t the bandpass stage, V,, must als be mdified t accunt fr the scaling as shwn belw and in the scaled flwgraph f Fig. 4.6(c): Fig ^UT0 A series f signal flwgraphs which illustrate the switched capacitr lp-scaling technique. V, - Ji--.lL-Ji. - Jk_J^-v" 1 QLn QLn QLn QLn QL0 V* (4.22) Fr this netwrk, the switched capacitr inputs t the bandpass stage at V, frm V, and I, (thrugh R) becme very small as QL becmes large since the switched.. Cu capacitr size is where Cu is the unit switched capacitr which is usually abut v*-n 1 pf. Because f the small size, it is difficult t accurately define and match these capacitrs in a mnlithic implementatin. This prblem is slved by reruting these tw signals thrugh charge multiplicatin paths assciated with the adjacent lwpass integratr as shwn in Fig. 4.6(d). In this case, the feedfrward capacitrs are qtj-»mes the integratin capacitr in cntrast t the netwrk f Fig. 4.6(c) where they were - times the switched capacitr value. Since the integratin capacitr is usually much larger than the switched capacitr, the capacitr values assciated with the tw feedfrward paths are mre accurately realized in mnl ithic frm. The final netwrk f Fig. 4.6(d) prvides a scaled bandpass utput, but the lwpass utput is lst due t the additin f summatin paths t the lwpass

68 stage. This technique has been verified by ther wrkers fr mnlithic versins f secnd-rder [52] and high-rder [67] bandpass and bandreject filters. The areanise-distrtin cnsideratins are identical t thse f the impedance and ndevltage scaled netwrks Nise in a Switched Capacitr Integratr In this sectin, the surces felectrical nise in a switched capacitr integratr BROADBAND NOISE will be described. The equivalent input nise spectral density f an MOS peratinal amplifier is frequency dependent as illustrated in Fig. 4.7(a). The pwer spectral density at lw frequendes (<10 khz) is dminated by the flicker cmpnent which decreases as, and the spectral density at higher frequendes is relatively cnstant (typically 100 nv/ Hz 1/2) and is determined by the thermal nise assciated with the chan nel resistance f the MOS transistrs. Depending n the passband frequendes f the filter, ne r bth f these cmpnents may be imprtant in determining the 1MHZ dynamic range at the utput f the filter. The nise perfrmance f the Miller integratr f Fig. 4.7(b) will first be analyzed cnsidering bth the thermal nise f the resistr and the equivalent input nisef the peratinal amplifier. It will be assumed that the p amp has a lw fre quency gain f A0with a ne-ple rllff t the unity-gain frequency, fu. The gain cnstant f the integratr is f0 1 2wReqCj as shwn in Fig. 4.8(a). First, cnsider the spectral nise cntributin frm the resistr. As shwn in Fig. 4.8(a), this white nise surce is lwpass filtered by the integratr which has a Ofc> (b) transfer functin f HR(0 1+ JfA0 (4.23) Fig (a) A typical plt f the equivalent input nise pwer spectral den sity fr an NMOS depletin-lad p amp; (b) A Miller integratr with p amp and resistr nise surces.

69 The pwer spectral density at the integratr utput is therefre equal t VWesur^ " [4kTREQ] A 2 fa f (4.24) OPEN-LOOP OP AMP Nw, cnsider the nise cntributed at the integratr utput by the pera tinal amplifier. The transfer functin frm V2;(0 t the integratr utput f Fig. 4.7(b) is given by. 1-hCjReq scir 1REQ (4.25) and is shwn as the darkest line in Fig. 4.8(b). Ntice that this curve is made up f fur separate sectins, and therefre, the utput pwer spearal density can be determined separately fr each f the fur cases as fllws: V2OU,(0 - V2i(OA02 fr 0<f<-2- A (4.26a) V2ut(0 - V2i(f) fr -2-<f<fn (4.26b) -H 1 ^1 I I V ** K 10K 100 K IM^OMHZ V2u,(0 - V2,(0 fr f0<f<fu (4.26c) (b) and V20U,(f) - V2i(f) f fr f ^f (4.26d) Fig (a) Transfer functin frm the resistr nise surce t the utput; (b) the transfer functin frm the p amp equivalent nise surce t the utput. where V2,(f) is the equivalent input nise pwer spectral density f the peratinal amplifier. Given an p amp pwer spectral density, Eqn. (4.26) can be evaluated t determine the ttal RMS nise at the integratr utput in any specified bandwidth.

70 Next, cnsider the spectral density at the utput f the switched capacitr integratr f Fig. 4.9(a) due t the equivalent input p amp nise. Fr baseband frequencies, the switched capcitr is equivalent t a resistr, REQ, and therefre, fr these lw frequencies, the switched capacitr integratr is identical t the Miller integratr f Fig. 4.7(b). Thus, a similar analysis applies with a slight change in the frequency limits as fllws: v, IN«> i-<v( OUT V2OU,(0 - V2i(OA02 fr 0<f< Js. Aft (4.27a) and V2OU,(0 - V2S(0 V2ut(«- V2i(f) fr -^-<f<f0 An frf0<f< - (4.27b) (4.27c) V, AkTRs R N (^)--VWVr-f O O * 1-^V, v0ut assuming y<fu where fc is the switched capacitr sampling frequency. The p f amp nise abve y in frequency must be treated using sampled-data techniques. It will be assumed that fc is greater than the -jr nise crner f the p amp s that flicker nise is ntaliased and thus, nly the bradband p amp nise need be cn sidered. The utput nise fr this case depends n when the utput is sampled. Fr example, if the utput is sampled during #, as in Fig. 4.9(b), the p amp is in unity gain as shwn in Fig. 4.10(a), and the squared RMS nise atthe utput is V2 OUTu a -1 -/VBB3 l+(f)2 df t wlv, uvbb (4.28) w OPEN ^t^ers ^S "N f- )AAA/U- Cy ^r\ (0 OUT where VBB2 is the bradband pwer spectral density. The sampled utput pwer Fig (a) A switched capacitr integratr; (b) the nise mdel during </», and (c) the nise mdel during 4>2.

71 spectral density is therefre 'PSD irfuv uvbb 2fc (4.29) On the ther hand, if the utput is sampled during 02 as in Fig. 4.9(c), the clsed C lp p amp gain is (1+tt-) as shwn in Fig. 4.10(b). The squared RMS nise at ci the utput fr this case is (a) OMHZ V 2 vut CO VBB2(1+-^-)2 l+(f)2(l+>)2 df TfuU+T^VBB2 (4.30) and the crrespnding pwer spectral density is (' 3> 'PSD wfu(l+7^)vbb2 M 2f. Equatins (4.28) thrugh (4.31) assume that fu is less than 1 2irR<C (4.31) If this OMHZ assumptin is nt valid, the same analysis can be used with fu replaced by _ Fig Frequency respnse frm the p amp input nise surce t the integratr utput fr (a) the circuit f Fig. 4.9(b) and (b) fr the circuit f Fig. 4.9(c). The nise cntributins frm the MOSFET switch transistrs als need t be cnsidered. Again, the baseband and high frequency terms will be cnsidered separately. The transistr M( cnnected t 0, has an n resistance f R, as shwn in Fig. 4.9(b). Fr lw frequencies, the switched capacitr can be replaced by a resistr, REq, and the Miller integratr f Fig. 4.7(b) alng with the transfer func tin f Fig. 4.8(a) are used t btain the spectral densities at the integratr utput: Vul2-4kTR,A02 fr0<f<-2- (4.32a)

72 and and the utput spectral density istherefre V0Ul2-4kTRs ^ 2 *>r <f. (4.32b) The ttal squared RMS nise cntributin at the integratr utput frm this nise surce is V2rms " 2kTirRsA0f0. (4-33) At lw frequendes, transistr M2 cnnected t *2 als has its nise filtered by the integratr s that Eqns. (4.32) and (4.33) als apply fr the nise surce f that transistr. Finally, the sampling effects fr these tw nise surces must be cnsidered. When M, is n, as in Fig. 4.9(b), its nise is lwpass filtered by the RSCU cmbina tin giving attal squared RMS nise n Cu f V2 (0 - ktreq [l+(27rfrscu)2] (4.37) When M2 is n, its nise is filtered nt Cu in asimilar manner, and when M2 is subsequently pened, this nise is sampled nt Cu. Hwever, +, then turns n M and this nise vltage is returned t the input surce s that M2 des nt cn tribute any sampled nise at the integratr utput. The spectral density calculatins fr the switched capadtr integratr can be used t estimate the nise perfrmance f any switched capacitr filter by multiply ing the pwer spectral density by \[(()\ where T(f) is the transfer functin frm the integratr utput t the filter utput, and then integrating ver the desired bandwidth. kt v RMS " ~ (4.34) When M, is pened, this nise is sampled nt Cu giving apwer spectral density at Cu f w2 kt. ktr rt (4.35) V2psd " TfT ktreq- The transfer functin frm Cu t the integratr utput is derived frm the circuit f Fig. 4.9(c) t be H(s) Ss. c, l+sr,cu (4.36)

73 133 13!f Chapter 5 EXPERIMENTAL RESULTS FOR NMOS LOWPASS PROTOTYPES In this chapter, experimental results frm tw NMOS integrated switched capadtr ladder filters are presented. The first design realized a fifth-rder Che byshev lwpass respnse, and the secnd, a third-rder Cauer lwpass respnse 124]-[25]. Mnlithic MOS capadtr ratis and dck frequency were used as the predsin cmpnents. The perfrmance f the NMOS depletin-lad pera tinal amplifier used t implement the filters is als given NMOS Depletin-Lad Operatinal Amplifier The NMOS peratinal amplifier used in bth filter designs (shwn schemati cally in Fig. 5.1), is a simplified versin f a recently reprted design [14]. It was integrated using the NMOS metal-gate depletin-lad prcess given in Appendix I. The measured results presented in Table I are in gd agreement with the thereti cal calculatins f Appendix DC Open-Lp Gain The DC pen-lp gain f NMOS depletin-lad peratinal amplifiers depends n bth pwer supply and bdy-bias vltages [14], [47]. Figure 5.2 shws that the measured pen-lp gain fr ±7.5 vlt supplies with 0, 2.5, and 5.0 vlts f bdy bias varied frm 400t 1000 as measured abut zer vlts at the utput. Figure 5.3 shws the lw frequency pen-lp gain characteristics fr ±5.0 vlt supplies with 0, 2.5 and 5.0 vlts bdy bias, and in this case, the gain ranged frm 33 t 60. As discussed in Chapters 3 and 4, fr lwpass filters, it is desirable t have a small-signal vltage gain f several hundred ver the entire utput vltage LA O- CD II Q_ O r- _l O > cmicn CNCM cm*-^ d I- 3 p cj c d T «<r cm ^ d ^ L J xt d 1r d L J O 1r J r. L CM U I Z > i_j 0 0 L J" u c L J lc ^Id 5JcO i > CO iolco L J < d LJ 1^- ii x* c H t 1- Ul t 2 z h- Ul -J Q_ UJ J_ (/) h- _J O > If) i > ii (7) r- Ld Li_ (/) 5 r- Z UJ 2 UJ u z < X z UI J- T~L ^ -1 *- _j 2 t UI H Q _J O > CvJ T ii CO range in rder t minimize frequency respnse errrs and harmnic distrtin. Fig Dcplciin-lad NMOS peratinal amplifier.

74 POWER SUPPLIES DC OPEN-LOOP GAIN VDD = 7.5 VOLTS VSS= ~7'5 VBB=-T I- O^ ID *4" CM i 1 r a»-'v- V I * '* 1 """ i ii i i I I I t" O CM <** ID» I I "1 1 1 I -*-1 < ' I I I I I I I I I - I i LA I i i in in in tv t^ CM I 1 II ll II O t CO Q i/> CD > > > EOUIVALENT INPUT OFFSET CMRR 120 mv 54 db 'j \*» < ^"T 1.'. f^f^w > Table I. PSRR UNITY GAIN BANDWIDTH SLEW RATE POWER DISSIPATION DIE AREA A6 db 1 MHZ 1 VOLT/juSEC 6 mw 400 mil2 Measured NMOS enhancement-depletin peratinal amplifier per frmance parameters. il*. r^ r MM ' -. I I *»» I I I I I I I I 1 \ n! ;r I r-\ i_j_l i i -+ i i j ii i. L I I u. wimi J_.l I I > E ^ i-.q O O in II in I ll d T ll a t c Q > > > > in in m r» t»» t«* 1 1 ll ll II Q t CD O t CO > > > Fig Open-lp p amp gain versus bdy-bias variatins fr ±7.5 vlt pwer supplies.

75 C0 ^> r CM *- i>w ' I.U+H-H-HH lllllllll &-*«.. r- CM T 1 1 I I M I I M I <._L. c I'll I..., J «L Mill. Ml I M I M M 1 i I! i t i i J I iv ; J I I I L. ^ M M II i I I I -J. MM I M O O -i > J: ^ I-.Q O I Q_ in in 1 1 II ll II O C/> CO Q t CO > > > > in ll a > > in in I in I ll II to CD CO CO > > in 1 in 1 ll ll ll a > t t > CD CO > Hence, fr best filter perfrmance, this particular amplifier shuld be perated with ±7.5 supplies with 5.0 vlts bdy bias. Nte frm Fig. 5.2 that when the utput vltage is belw -3.2 vlts, the gain decreases t abut 100. This pint n the gain curve crrespnds t the vltage where a sharp increase in harmnic distrtin is bserved in the filter Equivalent Input Offset Vltage The measured ffset vltage f 122 mv in Fig. 5.4 is typical f this amplifier, and is primarily due t the paraphase input stage. As described in Chapter 3, the amplifier ffset vltages cntribute t a DC ffset vltage at the filter utput which shuld be minimized in rder t maximize dynamic range. The ffset vltage f this particular amplifier can be decreased by unbalancing the input pair f transis trs in rder t cunteract the effect f unequal lads Cmmn-Mde Range and CMRR The measured cmmn-mde range and CMRR are displayed in Fig This parameter is nt imprtant fr switched capadtr integratrs if the p amps are used with the nninverting input cnnected t a DC bias vltage since there are n steady-state cmmn-mde signals fr this case Equivalent Input Nise The measured unity-gain nise spectral density is shwn in Fig The measured j nise crner is at abut 10 khz, and the bradband nise spectral density at 2 khz is abut 1/*V/[Hz],/2. Fig Open-lp p amp gain versus bdy-bias variatins fr ±5.0 vlt pwer supplies.

76 COMMON MODE INPUT (VOLTS) 6 r OUTPUT (VOLTS) 6r -A -2-4 ~6 L DIFFERENTIAL INPUT (mv) VDD= 7.5 V VSS= ~7-5 VBp=-12.5 Vs = 122 mv Fig INPUT OFFSET (mv) VDD= 7.5 V vss=-7-5 VBB =-12.5 CMRR = 54 db Measured p amp cmmn-mde range and CMRR. Fig Op amp input ffset vltage.

77 1M Pwer Supply Rejectin The measured pwer supply rejectin fr bth the VDD and V^ supplies is dbv//hz presented in Fig. 5.7 fr a lw frequency signal. The PSRR is typically greater than 45 db Pwer Supply Current versus Supply Vltage The data fr supply current versus supply vltage given in Fig. 5.8 shws that ±3.0 vlts is required t bias up the amplifier, and the "n" current is abut fia. The ttal pwer dissipatin is 6 mw fr ±7.5 vlt supplies KH2 VDD = 7.5 V Vss =-7.5 VBB = Slew-Rate Perfrmance Slew-rate and settling time can affect the accuracy and distrtin perfrmance f switched capacitr filters. The measured unity-gain transient perfrmance fr ±1 vlt steps is shwn in Fig Fr a lad capacitance f 13 pf, and a 10 pf cmpensatin capacitance, the measured slew-rate is abut 1 vlt//isec Unity-Gain Bandwidth Figure 5.10 shws the simulated p amp magnitude and phase respnse fr ( db VA/hI at 3400 HZ MARKER) ±7.5 vlt supplies with 5.0 vlts bdy bias when cnnected in unity gain with a 10 pf lad. The predicted unity-gain bandwidth is 2.5 MHz with a phase margin f 70 degrees. The measured unity-gain bandwidth was abut 1.5 MHz. Fig Measured p amp unity-gain nise spectral density DDI Switched Capacitr Fifth-Order Chebyshev Lwpass Filter In this sectin, the perfrmance f the DDI (with predistrtin) switched capacitr fifth-rder all-ple Chebyshev lwpass filter shwn schematically in Fig is described. It was integrated using the NMOS depletin-lad metal-gate > " >

78 143 M * ++-f MM H-+4 H 4 I MM ^trjtj' j,t: TT TTT^] ^T4 VERT.2V/DIV H0R.50 mv/div VDD= 7.5V TOTAL SUPPLY CURRENT VBB= PSRR =46 db & al2 aafcij^ a.av; C) rfcfil idi -600 Fig vss vdd Op amp supply current versus pwer supply vltage. INPUT/OUTPUT (1V0LT/DIV) INPUT/OUTPUT (1V0LT/DIV) VERT. 2V/DIV HOR. 50 mv/ DIV VDD= 7.5V.beqebq BBOGnn rrnnuu HRscaa vss=-7-5 VBB= PSRR = 54 db I 1 I 1 I L_J i>s/div., r \ DD= (a) VSS= -5.0 VBB=-10.0 CL = 13 pf CC = i i i i i i i 5.0 V -^/D'V 10 pf (b) Fig Measured p amp PSRR. Y\f, Measured p amp slew-rale perfrmance.

79 : 4} T3 Q Q,J==i in 'A fn L s \ / 6 i» 1 f't : Z1 i ^-"' :!i j?;5 ^r L» "*"" " 1 U".! -IM nnitrr t-v: I i" IK.CI.-* 2t4t*»0*1 >*.jp J U-.:w*-i y ^ y *» ** me\ J.i.Jtri - mi ii«-.» Jl.>-..0«.«il'i IJI alll-i1-3. (-,.> 1 ttl.v.(.l.vli-l ;ci <<t;-< / ll J IC.tl.fl-. il>.**«*-t nrrnrr idinc i 5»» j-rrt»t.»t If. I>».l<>-. j f : > : : /^ : : / u«.-.»-i ' - - "mi...<i fit.;t.«*.....!.'. >..1*1..l,..i'l iv...i «tv<-.:.<-1 S5TST7TT m-jrtmr «> -..{-I il. j $: I» l»..m ia> ;.»>-t in.ci.-. Kiltl l>> :. Ii.< > io. <. «.J.,4l;-< lj>*;..<*i («1 <i.>i.i-i ii»»...i.-l 4W< V E CO a : : M«MM~C* I \ r * "«i : 104 ( i.-i -»»«wr IV-..»»-i...I.-I IC.VII {.(.it.*! Iwl.SI.'. irrrurr IV* t. -.* I3«.J ; «U...1I- 1 -ten-v T.'.I.'! ii*... <-.)»l.-l i*. *r- I «.»..l.- ' Tbrjiir*-! _331jXtC-T ;«-i «.,U-«If.I..-.,_.,, * w»..l.'l >(..'/i-w -TTITTRT ilitlli*! ILl.,.1-1 Ui t. i.'l......;t_,,.., " ~T»«tO>« :.: tt«toot-l 0».B0«0* I t*ml*! "» -!... E cs"i

80 prcess f Appendix 1. The die phtgraph is shwn in Fig The lwer right crner cntains an peratinal amplifier which required a die area f abut 400 mil2. The test transistrs are n the upper right, and the fifth-rder lwpass filter is shwn in the left prtin f the die pht. The peratinal amplifiers, and switched capacitrs are embedded in the center, surrunded by the five integrating capacitrs which range in size frm abut 10 pf t abut 40 pf. The switched capadtrs are each abut 2.3 pf. The verall die size is 98 mils by 105 mils, and the filter is apprximately 70 mils by 90 mils Frequency Respnse The measured frequency respnse fr a sampling rate f 128 khz is given in Fig Figure 5.13(a) shws the respnse ver a large frequency range. The typical stp-band rejectin is abut 80 db. The details f the passband are presented in Fig. 5.13(b). The measured ripple bandwidth and ttal passband ripple are in excellent agreement with the design gals f 3400 Hz and 0.1 db, respec tively. Figure 5.14(a) shws the frequency respnse ver a very wide frequency range. The first alias term at 128 khz is apparent Frequency Respnse versus Sampling Rate The gain cnstant f a switched capacitr integratr is directly prprtinal t the sampling frequency. Hence, the cutff frequency f switched capacitr filters scales linearly with fc. This is illustrated in Fig which shws the respnse fr several difterent sampling rates. Nte that the passband ripple remains cnstant. This feature prvides ne pssible degree f freedm fr designing prgrammable filters which will be described in greater detail in Chapter 6. Fig Die pht f the fifth-rder switched capacitr lwpass ladder filler, test peratinal amplifier, and test transistr array. Die size is 98 mils by 105 mils.

81 a m > i *: in IT) a r-^ fv CM 1 II 1 V ll II II a t <_) CD fj t CD > > > «+rw.» u c > U (G x: 8 s c1 1 «> c 1C) irs. re it 4J 0 JB 0 u LU i a * re -Q U. b U i_ J T3 (/> re 3 3 X x: re r^ W * - 3 > N «X 5 * >, X5 <-J -J x: U «u. C -j T3 m r%8&i &&a* -i *n d -a &M' &MM&S - *r x - *\x.f * '.'.* ' ir'^.'lt' ~ " "* r S uj3 O K CVJ a u c -a 5. J= 3 Ji Q 3 2 Q?? <" c - O 1 i i i i 1 O O LU CVJ *r t CO T3 i i 1 CD a CM t CO CO S i/i 00 Eh

82 OdB a : 128 KHZ b : 64 KHZ Frequency Respnse versus Pwer Supply Variatins When the pwer supplies were changed frm ±7.5 vlts t ±5.0 vlts, the respnses f Fig were btained. The small changes in the respnse illustrates the lw sensitivity f the dubly-terminated switched capacitr ladder structure. The supply vltage cefficient f abslute gain at 1 khz is 0.03 db/vlt Harmnic Distrtin As discussed in Chapter 4, Ttal Harmnic Distrtin (THD) depends n the dB amplifier gain characteristics as well as the signal levels at the utput f each switched capacitr integratr in the filter. The signal levels are determined by the transfer functin frm the input nde t each f the integratr utput ndes. Frm Fig. 5.17, it is apparent that the signal levels are frequency dependent. Hence, the THD is als frequency dependent as shwn in Fig Chapter 4 described scaling techniques t reduce THD Nise Perfrmance Nise cnsideratins were presented in Chapter 4 where it was shwn that the ttal filter utput nise is equal t the entire nise utput f the last stage plus cmpnents frm the ther stages determined by the transfer functins frm the integratr utputs t the utput f the filter. The nise at the utput f an integra tr cnsists f p amp nise, thermal nise f the MOSFET switches, and aliased nise. Figure 5.19 displays the nise spectral density at the utput f the Che byshev filter. 8 KHZ Fig. 5.1S. Switched capacitr fifth-rder Chebyshev lwpass frequency respnse fr different sampling rates.

83 t - J -^11 I 00 0">Q_ 11 J CD : -^ H H «" O» -i & n s =* < < < 70 > < ^ < JJ > CD t O CD t CO c m CD c m II ii II II II II cr Q r-.. _L.!i::!- ;... cr "d" n *< S 3* ^J en en O >! si» O O _ en tn.:.. -' " ^ % -' * W T3 C» < < \J4 t %1 " m i - ' *.:.;.:. :.:' :J «< 3» < =? =r ST 6 I s. T -r~.. i. r I ' ;.... -^ -tj_... L _.: 1 7v X x>jl.'.-..!!, g 2? 90* GAIN (db) DDI FIFTH-ORDER CHEBYSHEV» c t * 3 O 3 3* n a. LOWPASS FILTER 8 fc: 3 * O (T) O "1» 3* -T) 3" 3 3 C CL n < "* O, n OS 3" 00 ffi n HE --

84 THD (db) TOTAL HARMONIC DISTORTION vs. FREQUENCY.$ OUTPUT AMPLI TUDE ' H *= X 3 a VDD=7.5V 3 f» 1 3) 3 n -30- r1-40- n *1 00 tn O i MM _«c r fo» ID n 0 Di n i/- n a 7 < Q. CD r -h < CD CD II 1 r c < II D D < II D, f:. Q. r n I ~ Cfi *< n Q GO r 03 en en ui < O 7* X O X r 7\ X 3" < 3" 6 3. > 70 m t fc

85 LDI Switched Capacitr Third-Older Elliptic Lwpass Filter In this sectin, the perfrmance f the type-i LDI switched capacitr threeple, tw-zer elliptic lwpass filter f Fig is described. The die phtgraph is shwn in Fig The three peratinal amplifiers with their assciated switched capacitrs are shwn in the right prtin, white the integrating and zer-frming capacitrs are alng the left prtin f the pht. The zer-frming capacitrs are abut 2 pf each, and are directly belw the first and third integrating capacitrs. The integrating capacitrs vary in size between 15 and 20 pf. The die size is 40 mils by 110 mils Frequency Respnse The measured frequency respnse fr a sampling rate f 128 khz is given in Fig Figure 5.22(a) shws the respnse ver a wide range f frequencies. The minimum stp-band rejectin is abut 30 db with a transmissin zer at abut 9 khz. The details f the passband are shwn in Fig. 5.22(b). The measured ripple bandwidth and ttal passband ripple are in excellent agreement with the design gals f 3400 Hz, and 0.13 db, respectively. A statistical distributin f insertin lss, clipping level, and passband ripple are displayed in the histgram f Fig based n a sample size f 9 frm a single prcessing run. Excellent prcess track ing appears feasible with this apprach. Fig. 5.14(b) shws the alias term at 128 khz. Nte that the insertin lss fr this filter is 0 db while the insertin lss f the RLC dubly-terminated ladder prttype is 6 db. In switched capacitr filters, the insertin lss can be scaled by simply changing the size f the input switched capa citr relative t the ther switched capacitrs. Fr example, the input capacitr, shwn at the bttm f Fig. 5.21, was dubled in the elliptic filter t increase the Fiji Third-rder elliptic lwpass type-1 LDI swiiched capacitr ladder filler.

86 db ) db 0 r Fig Die pht f the third-rder elliptic lwpass switched capacitr ladder filler. Fig (a) Measured frequency respnse fr the third-rder elliptic switched capacitr lwpass ladder filler clcked at 128 khz, and (b) the passband details.

87 If) gain by 6 db, thus reducing the insertin lss t 0 db. * (A O UI _l -J Z >- 1- >- cc 1- UI => lo z rti»» T UI V _l Q. CO Q. CM M ^~ rr X ^- >- z UI u. a ui cc < a. x u h- -I en u X» t ru < i m 00 CM -JO in cm Is 1- cc m if) UI - if) t z "~~i UI _i <r a. a. CC 01 lo _ TJ " z z cm < t CO» < * k5 lo a. (0 s z -js5 UI > > 1- CM Ul < CD K- X CM 3 id a. _^ r^ z<? -1 1 P"" T^ IO in ff n n f- S1INH do d3qwnn Frequency Respnse versus Sampling Rate Figure 5.24 shws the filter respnse fr several values f clck frequency. In Fig. 5.24(a), the respnse scales with lw sampling rates until the leakage current is significant during the lng integratin perids^ Fr this particular eaumple, the minimum sampling rate is abut 1 khz. Fig. 5.24(b) shws the scaled respnses fr several intermediate sampling frequencies, and Fig. 5.24(c) shws the respnse at high sampling rates. At sampling frequencies abve 300 khz, the slewing and settling errrs in the amplifiers distrt the frequency respnse. Hwever, ther wrkers with higher perfrmance amplifiers have bserved that sampling frequen cies appraching 1 MHz can be used befre significant distrtin ccurs [45],[51]. Figure 5.25 illustrates the clipping level, nise, and passband ripple as a functin f clck frequency Frequency Respnse versus Pwer Supply Vltages The measured frequency respnse fr different pwer supplies is presented in Fig The supply vltage cefficient f abslute gain at 1 khz is 0.03 db/vlt Harmnic Distrtin The transfer functins frm the filter input t each internal integratr utput are shwn as functins f frequency in Fig The measured THD versus fre Fig Histgram f passband ripple, insertin lss and THD fr a sample f 9 third-rder elliptic switched capacitr lwpass ladder fillers. quency is presented in Fig. 5.28, and THD versus signal level fr a 1 khz input is shwn in Fig Fr signal levels f abut 0.3 vlts RMS, THD is less than 0.1%. The increase in distrtin at lwer signal levels is due t the slight amunt f crssver distrtin in the p amp transfer characteristics f Fig ' ^

88 OdB Wm VDD= 7.5 V P. VSS ="7.5 VBB =-12.5 :it*> -rz*3-, «*"«*-5»S L: ^fsp^i; fc= 1,2,4 KHZ HE (a) 7.5 V wu "ivnis indin QH1 y.i ad SV, A ni TVN9IS lfldn 1 *xvw XOOIO^, CO tp <r CM O (O CM CM CM CM CM O100T0 ZH>I 921IV ZH*.*' ) S3WI1 9Q920* IV Q P 3"lddlet 8 CO lx> <T CM * OI00T0 ZHM8211V2HX2) XOOlOj. l?9/l IV ZH//A9P NI 3SI0N.««. ro in r-» lo O r i \ 1 / 1 CM CM Ifig fc=8j16,32,6aj128khz 7.5 V CO > * IU < x _J UI * < -J / z Q. z 2 S 5/ CO >- >- *7 UI s 1- t/ -J z I. Q. CC UI CO z ^" UI "" 3 r UI CC u. \ ^ z * -«* UI \ * «3 uj Of \ _l ui -J Q. CC u. U. cc * ~ UI O t _J \ \ it j / t.(9 5 1 l> z v.cm Fig AO 50 KHZ (c) -Fr=128,200,256, 300 KHZ Swiiched capacitr third-rder elliptic lwpass frequency respnse versus sampling rale. Fig IAXIMUI (DU CY Measured nise spectral density, passband ripple and clipping level versus clck rate fr the elliptic third-rder switched capacitr lwpass ladder filter.

89 OdB -50 DD = 7.5 V VSS= 7.5 BB = -7.5 (LEFT) (RIGHT) fc = 128 KHZ OdB V3lVUT> 10 KHZ - 60 OdB KHZ LEFT:VDDr 7.5V VSS= -7.5 VBB=-12.5 RIGHT:VDD= 5.0 V vss VBB = fc = 128 KHZ VDD= 7.5 V ss = VBB=-12.5 fcl0ck =12B KHZ 16 KHZ Fig Swiiched capacitr third-rder elliptic lwpass internal-nde transfer functins relative t the input. Fig Swiiched capacitr third-rder elliptic lwpass frequency respnse fr different pwer supply vltages.

90 HD I[dB) TOTAL HARMONIC DISTORTION vs FREQUENCY OUTPUT AMPLITUDE 8 2 O CB «"> «/> 5/ C H n _ Q. 3 H g D </> VDD=7.5V -30- Vss=-7.5 VBB^ fc =128KH2 Vp *» 2 =» 2»,. O. 6 Q. -60 ON 05 *" 3 _ ^ cb a.'?i. CB ~ 2. :^ 3* =; c 9-S g - n s. a. 65 n 3?» elf 2. r. re s < > < I V)... «-» ^» i 3 _»"H. cb cb e S Or. SES 3 N CB 5' «*> 2. => U) CB n r Q. &

91 Nise Perfrmance The utput nise spectral density versus frequency is pictured in Fig fr a spectrum analyzer bandwidth f 100 Hz. The sampling rate was 128 khz Pwer Supply Rejectin The measured supply rejectin is presented in Fig fr all pwer supplies and clcks. The rejectin can be increased by mre careful layut which includes shielding wherever required. Higher perfrmance amplifiers wuld als imprve 80 r n 0 this specificatin. > 4. c Phase Sensitivity The phase at the 3400 Hz cutff frequency was measured fr different samples - 40 u 40 - with variatins in dck frequency, clck duty cycle, and temperature. The results given in Table II shw that the switched capacitr dubly-terminated ladder filters CD a> have very lw phase sensitivity in additin t lw magnitude sensitivity. 0 L Temperature Perfrmance 10 khz Three samples were tested at 0, 25, and 65 degrees C. Nise remained cn stant ver temperature; the insertin lss at 1000 Hz changed less than 0.1 db, and the passband ripple-changed less than 0.05 db fr a 2.8 VRMS input signal. The temperature cefficient f abslute gain at 1 khz was abut db/ C. Fig Output nise fr the third-rder elliptic lwpass switched capacitr ladder filter. Analyzer bandwidth is 100 Hz Intermdulatin Distrtin The measured intermdulatin distrtin versus applied signal level is displayed in Fig

92 OdBi OdBx -20 VBB SUPPLY REJECTION VDD SUPPLY REJECTION OdB 10 ( ) VDD=7.5V VSS =-7.5 VBB= KHZ OdB 10 (0 VDD =7.5V VBB= KHZ -20 Vss SUPPLY REJECTION } REJECTION REJECTION (b) + 20 KHZ (d) + 20 KHZ Fig Measured pwer supply rejectin fr the third-rder elliptic lwpass switched capacitr ladder filter, (a) VBB supply; (b) Vss supply. Fig Measured pwer supply rejectin fr the third-rder elliptic lwpass switched capacitr ladder filter, (c) VDD supply; (d) clcks.

93 _ ** n m SAMPLE NO KHZ C 40% nte: DATA IN I AND XT ASSUMES 40% DUTY CYCLE Ul\ \ 3 X - hl\ ^~ \ Gt ^ X. < s LU LU W?. Q z [TDO u g^oh a: 2 H «- < - LU S Z-l5l-2 H 2 ^ F,!< ; _J lli l*izz ru? - _l x GO?<S CM ± > uj r II O CM CO <fr m (9 i qp ni lndd NOiivnnarNd3iNi. ts CO cc > CM - 1x1 O < _J O O > c <x> 3 cl- Table II. Measured phase sensitivity fr the third-rder type-1 LDI swiiched capacitr ladder filler. Fig Measured intermdulatin distrtin (IM) fr the third-rder ellip tic lwpass switched capacitr ladder filter. ' 1

94 Quantizing Nise The utput f switched capacitr filters changes in small steps at each integra tin time as shwn in Fig Hence, there are cmpnents at the clck fre quency due bth t clck feedthrugh and t signal transitins. In this cntext, quantizing nise is defined as the ttal magnitude f the signal at the sampling fre quency in a 1 Hz bandwidth, and isdisplayed in Fig When the input signal is very small, the quantizing nise is due almst entirely t clck feedthrugh which fr the metal-gate prcess used in these experiments is abut 75 mv. VERT. 500mV/DIV HOR. 200JUS/DIV VDD= 7.5 V vss=-7-5 VBB=-12.5 = 128 KHZ CLOCK f,n=lkh2 VERT. 500 mv/div H0R.200JJS/DIV VDD= 7.5 V Vss=-7.5 VBB=-12.5 = 128KHZ "FcLOCK f N=3KH2 Fig Output wavefrms fr the third-rder elliptic lwpass swiiched capacitr ladder filler clcked ai 128 khz.

95 Chapter 6 AN ELECTRICALLY-PROGRAMMABLE SWITCHED CAPACITOR FILTER R Switched capacitr techniques have been used t integrate frequency selective filters using standard MOS technlgy Ill],I13]-I15J,l24j-l25]. In determining the usefulness f this apprach fr a given applicatin, the bvius advantages f integratin such as small size and lw manufacturing cst must be weighed against the disadvantages f the cst and time required t mask prgram a desired filter respnse. This restricts the usefulness f these fillers t thse applicatins with () sufficient manufacturing vlume t justify the expense f mask prgramming, and it cmpletely eliminates their use in applicatins that require a time-varying 1/0 i/<j, respnse such as adaptive filters and speech and music synthesizers. A mnlithic filter which can be prgrammed by the applicatin f digital cntrl signals wuld therefre find widespread use, and is the subject f this chapter [59]. Vinf v2 t^l/w fvut I2t 6.1. Synthesis f the Prgrammable Secnd-Order Sectin In this sectin, the synthesis apprach will be described using s-plane ntatin. (b) The singly-terminated RLC secnd-rder lwpass filler shwn in Fig. 6.1(a) was chsen as the prttype fr this design because it can be cnfigured in an active frm in which the peak gain (G), selectivity (Q), and center frequency (*0) are independently prgrammable. T illustrate this very imprtant pint, cmpare the general frm f the transfer functin fr a secnd-rder lwpass filler which is given by H(s) s2+s^+t-0 (6.1) where k is a cnstant, t the transfer functin fr the RLC circuit f Fig. 6.1(a) Fig (a) The singly-terminated RLC secnd-rder lwpass prttype and (b) an equivalent frm after impedance scaling; (c) the crrespnd ing signal flwgraph.

96 which is given by 1 H(s) LC ^b-k (6.2) In rder t btain prgrammability, Eqns. (6.1) and (6.2) are equated t slve fr L and C in terms f w0 and Q t btain: -M (6.3a) and (6.3b) RQ»0' Fr given values f R and w0, it is apparent that the values fr L and C becme widely separated (prprtinal t Q2) as Q becmes large which is undesirable since it wuld result in a similar spread in the required capacitr ratis in a switched capa citr implementatin. Frtunately, a significant imprvement is btained if the impedances are scaled s that the terminatin resistance, R, is equal t since the After scaling, Ihe reactive elemeni values are equal and are determined by the center frequency independently f Q and peak gain. The scaled RLC prttype is shwn in Fig. 6.1(b), and a crrespnding signal flwgraph is shwn in Fig. 6.1(c). The switched capacitr circuit which implements the flwgraph f Fig. 6.1(c) wuld usually be realized with nly the tw peratinal amplifiers required t implement the tw integratrs. In this case, hwever, the terminatin path presents a practical prblem because fr high Q, the swiiched capacitr which implements the -^ terminatin becmes very small (0.01pF). Therefre, it was decided t use a third peratinal amplifier t realize the terminatin arund the bandpass stage, and t set the peak gain thrugh the filter. The third peratinal amplifier is used in a charge multiplier cnfiguratin as shwn in Fig. 6.2 with a minimum capacitr size f Cs«=0.42 pf. In rder t insure DCstability against leak age currents and pwer-up transients, a switched capacitr resistr was cnnected acrss CQ. It is interesting t nte that the filter ffig. 6.2 has the same frm as a secnd-rder state-variable filler 160]. It thus retains many f the advantageus state-variable prperties including lw sensitiviiiy t cmpnent variatins, and the availably f lwpass, bandpass, and bandreject utputs. L and C values then becme 6.2. Design f the Prgrammable Switched Capacitr Arrays and «w (6.4a) There are several cnsideratins in determining what type f capacitr arrays t use fr prgramming the switched capacitr filler respnse. The silicn area required fr the arrays shuld f curse be minimized while maintaining a large enugh unit capacitr size t prvide gd matching accuracy. Mre imprtantly, C- 1 _ 1 (6.4b) *kk - the arrays must be designed s that capacitr switching during dynamic prgram ming will nt distrt the respnse r create large displacement currents. With these cnsideratins in mind, tw different types f capacitr arrays were designed fr

97 use in the secnd-rder prgrammable filter. Fr the circuit Fig. 6.2, the first-rder relatinships between the prgrammable capacitr ratis, -rp- and -rp-t and the selectivity (Q) and peak gain (G) are given by C_ (6.5a) and Cs (6.5b) Because f the linear relatinships in Eqn. (6.5), six-bit binary-weighted MOS capa citr arrays similar t thse first used by McCreary [58] were chsen t implement these functins as shwn in Fig. 6.3(a). Neglecting the ffset vltage f the pera tinal amplifier, the tp plates f the capacitrs in this array are either switched t grund r t a virtual grund. Since there is n vltage change acrss the capaci trs during switching, there is n harmful flw f displacement currents, and hence, this filter can be used in dynamic prgramming applicatins. Because the charge multiplier cnfiguratin is nt sensitive t parasitic capacitances, a small unit capacitr size (Cs=0.42 pf) was chsen t implement the binary Q and G capacitr arrays fr this stage. The first-rder relatinship between the prgrammable capacitr rati, -, and the center frequency, f0, is Fig The switched capacitr secnd-rder electrically prgrammable filler. cu 27Tf (6.6) ' 1

98 Fig s z s lc-)l- e ^h '0 91 Ac 51 sze u J li ft Hn3 9Z.Z.9*0 ft n0 9Z.99TJ HL ft n [Jn0 99*770 -ft fjn0 8ir0 -ft [ n3 29ZE*0 -ft n0 8998"0 n0 9C98 L ii. t <> I i (a) The six-bit binary-weighted capacitr array used t prgram the gain and the selectivity, and (b) the nn-binary capacitr array used t prgram the center frequency. It was desired t have the center frequencies lgarithmically span an ctave f fre quency such that when the sampling rate was changed by a factr f tw, a new set f center frequencies wuld be btained which wuld smthly cntinue the lga rithmic prgressin. Since the relatinship in Eqn. (6.6) is an inverse (and because f the lgarithmic prgressin), binary-weighted capacitr arrays were nt suitable fr center frequency prgramming. Therefre, a mre flexible type f MOS capaci tr array was develped as shwn in Fig. 6.3(b). The amunt f capacitance selected in this array is determined by turning n all the MOS switches except ne. The switch which is ff electrically separates the array int tw parts. The value f capacitance determining f0 is the sum f all capacitrs between the ff switch and the p amp. As in the binary arrays, the remaining capacitrs t the right f the ff switch are cnnected t grund s that the displacement current generated during prgram switching is minimized. In Fig. 6.4, the capacitance ratis required t prgram eight different center frequencies with lgarithmic spacings are given fr a clck rate f 10 khz. The values f the capacitrs which are prgrammed in the nn-binary array are determined by the difference between adjacent capacitr ratis as shwn in the graph. This type f array is extremely efficient in its use f capacitr area. Fr example, in rder t btain the lwest center frequency f 225 Hz, a capacitr rati f 7.07 is required, and since the ttal capacitance in the array is 7.07 unit squares, n silicn area is wasted. Type-I LDI integratrs were used t implement the filter, and Cu was chsen t be abut 2.6 pf. In this particular design, there is n significant perfrmance advantage in using type-11 LDI integratrs since Cu must be several picfarads in rder t accurately realize the fractinal unit capacitrs required in the Cf arrays. It will be shwn later that the errr intrduced by the tp-plate parasitic capacitance is very small.

99 Eqn. (6.6) als shws a direct ne-t-ne relatinship between f0 and fc. Therefre, fr a given capacitr rati, the sampling frequency can be used t pr gram the center frequencies f the filler. This prgramming technique was als used in the frmant speech synthesis filter t be described later in this chapter. In the next sectin, the practical design cnsideratins fr the switched capacitr pr grammable secnd-rder sectin will be presented Practical Design Cnsideratins The practical limitatins f the MOS peratinal amplifiers, parasitic capaci tances, and ther nnidealities can affect the perfrmance f switched capacitr fillers. In sme cases where the filter specificatins are relatively relaxed as in a frmant speech synthesizer, frequency respnse deviatins can be tlerated if they are predictable. In cases where the specificatins are tighter, it may be necessary t cmpensate r predistrt t eliminate these errrs. Therefre, it is imprtant fr bth cases t develp a set f design equatins which relate the actual filter perfr mance t the parameters f the individual cmpnents. In this sectin, the practi cal design cnsideratins fr the prgrammable secnd-rder filter will be presented Sampled-Data Transfer Functins Fig Capacitr rati versus center frequency. The nn-binary capacitr values are determined by the difference between successive capaci tr ratis. The switched capacitr implementatin has a frequency respnse which is slightly different frm the respnse f the RLC prttype due t the terminatin errrs intrduced by the finite switching frequency. functins are given belw: -fe]l2(22+a'2+1)l "br<z> - [ V.,.. r b3z3+b2z2+b,z+b0 The sampled-data transfer (6.7a)

100 where "-"-s^"-" HLP(z) HBP(z) (z-1) (6.7b) (6.7c) (6.7d) Exact Design Equatins The lwpass transfer functin f Eqn. (6.1) is given in terms f the parame ters >0 and Q which are defined in Fig Frm the figure, it can be seen that the actual peak frequency and selectivity can deviate frm these assumed values by an amunt which becmes significant fr small values f Q. The actual peak fre quency, Wpeak, is given by «i [cuj 2-2 (6.7e) "peak 1 2Q3 1/2 (6.8) [Cul lcrej [c$ C0 2 fc'-u 1 + [cu C + 1 cqj -2[cu] [cs ICQ 1 > -2 cqj (6.7f) (6.7g) (6.7h) and the actual Q value is Qa = Q 1-4Q2 1/2 (6.9) Frm these equatins, it is apparent that the discrepancy in the apprximate expres sins increases as Q decreases. Fr example, if the desired Q is ne, Eqn. (6.8) predicts a peak frequency fa.pe,k-0.707a,, and Eqn. (6.9) predicts aqa value f and QA= bn--!-^- (6.7i) The frequency respnses are btained frm these equatins by setting z=e"ut. The resulting expressins can then be slved t btain the actual sampled-data Q and center frequency values. In general the apprximatin t the RLC prttype becmes better as the clck frequency increases relative t the center frequency. A better fit between the cntinuus and sampled-data respnses can be btained by slightly mdifying the capacitr ratis (64] Op Amp DC Gain Effects fr Integratr Stages The finite DC gain f the NMOS peratinal amplifiers used t implement the switched capacitr integratrs causes errrs in the filler frequency respnse, espe cially fr high Qvalues. (It is assumed here that the bandreject stage is ideal). The actual QA is given in terms f the desired Q by 2Q+A l+a2+4 1/2 =,i_ia (6.10) where the apprximatin is valid fr large Qvalues. This relatinship is pltted in

101 Fig. 6.6 fr tw cases where the p amp has infinite gain, and fr a gain f Fr Q=50, and A-1000, the errr is 10% which gives a QA f 45. This deviatin can be reduced by using higher gain p amps, r by using a cmpensated nnbinary array t crrect fr the gain errrs. The center frequency als depends n the p amp gain as shwn in the fllw ing frmula: CENTER 1 A+l A2+A+,J a \m ^ A+l (6.11) Fr A=1000, the difference between >0 and ia is less than 0.1%, and can there fre be neglected fr mst cases. It shuld be emphasized that it is the DC p amp gain which is mst imprtant, and nt the gain at the center frequency because the switched capacitr integratr respnds t a step respnse where the final value after slewing and settling depends nly n the lw frequency gain. The frequency respnse f the p ampdetermines the settling respnse Op Amp Gain Effects fr the Bandreject Stage A schematic f the gain-setting bandreject stage, neglecting the switched capa citr feedback resistr, is shwn in Fig The utput fthis stage is given by Fig An s-plane ple plt which defines the parameters»0, Q, and the center frequency. Cs ^0 A+l+-^- V. - A+1+- 'BP- (6.12) Thus, the finite DC p amp gain f the bandreject stage intrduces bth a filter gain errr and a filter Q errr as given by the first and secnd bracketed terms, respectively. The filler peak gain errr is maximum when Q is minimum and G is maximum. Fr example, if Q-l, G=64, and A-1000, then the errr in the peak

102 IN - -tf- V_. BP ^f OUT Fig A simplified schematic f the gain-selling bandreject siage. Q Fig A graph f Q versus desired Q fr tw different values f DC p amp gain fr the tw amplifiers used t implement the switched capacitr integratrs.

103 193 19** gain is abut 6%. The Q errr is wrst-case fr minimum Q and G. If G = l, Q=l, and A = 1000, the Q errr is nly abut 0.2% Tp-Plate Parasitic Capacitance Since type-i LDI integratrs were used in this design, it is imprtant t cn sider the effect f the parasitic capacitance cnnected t the tp-plate f the switched capacitrs. Fr a switched capacitr value f Cu, and a tp-plate parasitic capacitance f Cp, the center frequency (assuming everything else is ideal) is n 11/2 (6.13) and the actual Q value is given by Qa = Q 4 t/2 (6.14) (a) In this design, the switched capacitr size was abut 2.3 pf, and the tp-plate parasitic was abut pf. Thus, the errr due t tp-plate parasitic is nly f0 ARRAY DIGITAL abut 0.5% which is negligible fr the frmant speech synthesizer applicatin. necessary, type-11 integratrs culd be used t btain greater accuracy. If LP STAGE Q ARRAY, LOGIC 6.4. NMOS Prttype Experimental Results An experimental prttype f the electrically prgrammable secnd-rder switched capacitr filter shwn schematically in Fig. 6.2 has been integrated using the NMOS metal-gate enhancement-depletin prcess described in Appendix 1. A BP BR STAGE STAGE f0 ARRAY G ARRAY phtgraph f the 88 mils by 105 mils (including bnding pads) die is shwn in Fig The NMOS peratinal amplifier used in this circuit is identical t the ne described in Chapter 5. The prgrammable filter can prduce 32,768 (2,s) different Fig (b) (a) A die phtgraph f the 88 mils by 105 mils NMOS experimen tal chip, and (b) a layut blck diagram f (a). < >

104 frequency respnses at each f the lwpass, bandpass, and bandreject utputs fr each clck frequency. lwing sectins. Representative experimental results are presented in the fl db On Center Frequency Prgramming By applying a 3-bit digital wrd t the tw nn-binary arrays, any ne f eight different center frequencies can be prgrammed. As mentined earlier, the center frequencies were designed with lgarithmic spacings where f0(n) = 1.089f(n 1). The eight experimentally bserved center frequencies shwn in Fig. 6.9 fr a 20 khz clck rate are in gd agreement with the expected design values Clck Frequency Prgramming Hz The gain cnstant f a switched capacitr integratr, >0=fc, is directly prprtinal t the sampling frequency. This ne-t-ne relatinship can als be used as a degree f freedm in prgramming a switched capacitr filter. Since fre quency divisin by a factr f tw is easily achieved using standard flip-flps, this filter was designed in such a way thai when the clck rate was changed by a factr f tw, a new set f center frequencies was generated which smthly cntinued the lgarithmic prgressin as illustrated in Fig Thus, with a 1 khz minimum clck frequency and a 256 khz maximum clck rale, the center frequen cies range ver eight ctaves frm 22.5 Hz t Hz in lgarithmic steps. Fig The eight experimentally bserved prgrammable center frequencies fr a 20 khz clck rate.

105 db ^ ^y^ #i^&;;t^&; Selectivity Prgramming A six-bit digital wrd is used t prgram a binary-weighted capacitr array t any ne f 64 different Q values frm Q=l t Q= 64. Figure 6.11 shws five f the pssible 64 values ranging frm fur t 64 by factrs f tw. Ntice that the highest experimental Q is abut 56. The deviatin frm the desired value f 64 is due t finite DC p amp gain f 1000 as described earlier l Gain Prgramming A six-bit binary wrd is als used t prgram the peak gain thrugh the filter. Figure 6.12 shws seven f the pssible 64 G values ranging frm ne t 64 by fac Hz trs f tw. Gd agreement is bserved between thery and experiment. db Lw-Q Passband Details On Fr lw-q applicatins, there is a significant difference between the actual values fr the center frequency and gain and the parameters w0 and Q due t the theretical apprximatins used in Sectin 6.3. The experimental passband details -40- f Figure 6.13 shw that as Q is decreased, and these apprximatins becme invalid, the peak frequency is reduced such that when Q is ne, 01^ , and the gain is increased by abut 1.25dB. Fr Q ^5, these discrepancies are less than -80J 1% Hz Dynamic Range The utput dynamic range was measured fr maximum and minimum values Fig The eight experimentally bserved center frequencies fr 20 khz and 40 khz clcks. The filter is designed s that the lgarithmic prgressin f center frequencies is smthly cntinued as the sampling rate is changed by a factr f tw. f Q and peak gain. The nisecntributed at the utput f the filler by the internal p amps and their assciated switched capacitr resistrs is amplified by an amunt equal t Q, and hence, the dynamic range decreases fr higher Q's. The distrtin

106 db On db ^TOjriBGF5!^rarsp^» Hz Experimental results fr five f the pssible 64 prgrammable Q values. Fig Experimental results fr seven f the pssible 64 prgrammable peak gain values.

107 db 2-i HZ at the uiput remains relatively cnstant. Preliminary results indicate a dynamic range f frm db as Q is varied frm ne t 64 fr f-»450 Hz at a 20 khz clck rate. Cmplete dynamic range data will be published at a later dale 61] A Frmant Speech Synthesis System There are many applicatins which require electrically prgrammable filters including adaptive equalizers, and music and speech synthesizers. This sectin will describe an applicatin wherein several swiiched capacitr secnd-rder sectins are dynamically prgrammed t implement a frmant speech synthesis system. The majr advantage f the frmant algrithm is that gd quality speech can be syn thesized with a lw data rate f abut 300 bits/secnd [62] The Vcal Tract Mdel Figure 6.14(a) shws a crss-sectin f the male vcal tract which is a lssy acustic tube abut 17 cm in length. Theretically, this lube has an infinite number Fig Lw Q passband details fr a 20 khz clck rate. f natural frequencies r frmams. In rder t prduce different sunds, the fre quency respnse characteristics f the vcal tract are altered by changing the crsssectinal area f the tube at the tngue, lips r teeth. There are several methds by which the vcal tract respnses can be electri cally simulated 162]. One methd f electrically mdelling the vcal tract is shwn in Fig. 6.14(b). In this mdel, a distributed LC ladder is used in which each LC pair cntributes t a resnant frequency. The main disadvantage f this apprach is that it is very difficult t independently prgram the frmanls. Therefre, it was decided t use a cascade f electrically-prgrammable swiiched capacitr secndrder sectins which allws the gain, Q, and frmant frequencies t be indepen dently cntrlled.

108 A Swiiched Capacitr Frmant Synthesizer A blck diagram f the frmant synthesis system is shwn in Figure It has been shwn experimentally that gd quality speech can be btained by simu lating nly the three lw frequency frmants 162]. These three frmants are imple mented with secnd-rder switched capacitr filters which have their gain, center frequency and selectivity prgrammed by a digital cntrller. In additin, it has been shwn that all f the higher frequency frmants can be empirically mdelled using high-rder ple crrectin with a fixed respnse. In this case, tw ples with center frequencies abve the third frmant are used as crrectin. The respnse f this filter is dynamically prgrammed every 1-10 msec t prduce the synthesized speech. As mentined earlier, the clck frequency can be changed t prgram these filters, and this feature has been explited in the frmant synthesizer. The first frmant stage is clcked at 10/20 khz, the secnd at 30/60 khz, and third at 60/120 khz. Since there are respnses/utput/clck frequency, and since there are five different clck frequencies, there are 3.78 x 1022 pssible different respnses fr this system! At the present time, the English vwels have been synthesized with excellent results. Figure 6.16 shws tw different vcal tract respnses fr the vwels /a/ as in "father", and Id as in "bet", and their crrespnding time wavef"rms. This sys tem is currently being characterized and the cmplete results will be published at a later date [63]. Fig (a) A crss-sectin f the male vcal tract, and (b) a distributed LC ladder electrical mdel.

109 n n 3 ), CLOCK GENERATOR n O" 3 3, r *r VOICED V V V V V 3 a 00 3 * n 0 r 3 r in c? rr 3-09 < 3 r; "* r. * a»* _J n a T UNVOICED INPUT FIRST FORMANT > Oi 3i e2 SECOND FORMANT > THIRD FORMANT f4) e3 > FOURTH FORMANT (FIXED) n. > FIFTH FORMANT (FIXED) G5 A * r r: n a < rr ft 3" f2 PARAMETER INTERPOLATION /v. / s Q. t PARAMETER STORAGE 2. * -a c 8?B R Q \ 3 ^ ^^f^g^p^^i^ r

110 Chapter 7 insensitivity t cmpnent variatins. One circuit verified a new technique fr CONCLUSIONS A new apprach fr designing precisin high-rder switched capacitr filters has been develped which uses state-variable techniques t simulate passive RLC ladder netwrks. Switched capacitr ladder filters have several imprtant advan tages ver ther appraches: (1) The lw sensitivity f the passband respnse f the RLC ladder prttype t cmpnent variatins is retained in the switched capa citr active ladder equivalent netwrk; (2) by simulating cnventinal RLC filters, there are many design tables available which can be used t btain prttypes fr synthesizing switched capacitr filters, and (3) since the switched capacitr respnse depends n mnlithic MOS capacitr ratis and clck frequency as the precisin designing switched capacitr filters using switched weighted capacitr arrays t achieve digitally-prgrammable frequency respnses. There are several areas where future wrk may be directed: (1) Reducing the required number f peratinal amplifiers; (2) high frequency switched capacitr filters; (3) maximum dynamic range filters; (4) N-path filters; (5) minimum area realizatins, and (6) the develpment f bilinear switched capacitr integratrs which are insensitive t parasitic capacitances. cmpnents, very precise respnses can be btained which are insensitive t tem perature and prcessing variatins. The relatinship between the phase shift f the sampled-data integratr and the frequency respnse f the switched capacitr ladder filter has been investigated, and three techniques have been develped fr clcking switched capacitr filters. The type-ii LDI clcking is the simplest and has the additinal advantage that the dependence f the frequency respnse n all parasitic capacitances is eliminated. The fundamental limitatins n dynamic range have been explred, and several new techniques have been presented fr scaling switched capacitr filters. The nise perfrmance f the switched capacitr integratr has been analyzed in terms f the p amp nise, and the switched capacitr resistr nise. Three experimental NMOS prttypes have been designed and fabricated. These filters demnstrated wide dynamic range, lw pwer dissipatin and

111 Appendix 1 NMOS METAL-GATE ENHANCEMENT-DEPLETION PROCESS This appendix details the NMOS prcess used t fabricate the switched capaci tr filters described in this dissertatin. The prcess evlved t its present frm thrugh previus effrts [53],(58). Brn diffusins are used as islatin regins, and the substrate is brn-dped p-type <100> rientatin with hm-cm resistivity. Fabricatin Sequence 1. Initial wafer cleaning: (a). Deinized water DI:HF (9:1), rm temperature dip fr 2 mins. (b). TCE, 60 C fr 10 mins. (c). Acetne, rm temperature fr 2 mins. (d). DI rinse. (e). Clean fr 15 mins. in H2S04:H202 (4:1) at 90 C (piranha cleaning step). (0. DI rinse. (g). N2 blw dry. 2. Inital xidatin: N-type drive-in furnace, 0.92 jun fxide, (a). Wet 02 at 0.5 liters/min, 1150 C, 90 mins. (b). Dry N2 at 0.65 liters/min, 850 C, 10 mins. 3. Negative phtresist step: (p+ islatin diffusin mask) (a). Apply Kdak 747 Micrnegative Phtresist; spin at 5000 rpm fr (b). Air dry fr 15 mins. (c). Prebake at 90 C fr 30 mins. (d). Expse mask, 3.5 sees. (e). Spray develp, 30 sees. (0. Spray rinse, 20 sees. (g). Alchl dip, 7 sees. Ispzpylrmethanl (1:1). (h). Light DI rinse. (i). Light N2 blw dry. (j). Pstbake at 125 C fr 30 min. (k). Oxide etch, NH4F:HF (5:1), rm temperature, 9.5 mins. (0.1 micrns/min.) (1). Phtresist strip, H^O^H^ (4:1), 90 C, 5 mins. 4. Piranha Clean. 5. Brn predepsitin: P-type predepsitin furnace at 950 C. Simultaneus flw fr 15 mins. f the fllwing gases: (a). B2H6, 0.26 liters/min. 1 (b). 02,0.013 liters/min. (c). N2, 1.3liters/min. 6. Etch brn glass: HF:DI (1:3), 1.5 min. dip. 7. Piranha clean. 8. Field xide grwth: N-type drive-in furnace, 1150 C, 0.4 urn f xide ver 30 sees.

112 (a). Wet 02, 0.5 liters/min., 16 mins. Same as steps 3(a)-3(j). (N xide etch)! (b). Dry 02, 1.0 liters/min., 10 mins. 19. Phsphrus depletin implant: 2.1 x 10l2/cm2 at 150 kev. 9. Negative phtresist step: (N+ diffusin mask) Same as step 3 except etch fr 10 mins. 10. Piranha clean. 11. Phsphrus predepsitin: N-type predepsitin furnace, 1100 C. 20. Piranha clean. 21. Brn enhancement implant: 7.8 x 10n/cm2 at 50 kev. 22. Oxide etch: Using Q-tip, etch back f wafer nly. 23. Piranha clean. (a). 02 at 0.1 liters/min. and N2 at 1.25 liters/min. fr 5 mins. 24. Phsphrus gettering step: N-type predepsitin furnace. (b). 02 at 0.1 liters/min., N2 at 1.25 liters/min., and POCI3 at liters/min. fr 20 mins. (a). 02 at 0.1 liters/min. and N2 at 1.25 liters/min. fr 5 mins. at 1000 C. (b). 02 at 0.1 liters/min., N2 at 1.25 liters/min., and POCI3 at (c). N2 at 1.25 liters/min. fr 10 mins liters/min. fr 2 mins. at 1000 C. 12. Etch phsphrus glass: HF:D1 (1:3), 1.5 min. dip. (c). N2 at 1.25 liters/min. fr 10 mins. 13. Piranha clean. 14. Field xide grwth: N-type drive-in furnace, 0.5 *im f xide ver n Etch phsphrus glass: Dip in H2S04:H202 fr 5 mins. 26. Negative phtresist step: (Cntact mask) (a). (b). Wet 02 at 0.5 liters/min., 1100 C fr 34 mins. Dry N2at 1.0liters/min., 900 C fr 10 mins. Same as step 3 except expse fr 1.8 sees, and then shift ne rw and expse fr 1.7 sees, t eliminate pinhles. Oxide etch time is 1 min. 15. Negative phtresist step: (Gate xide mask) Same as step 3 except etch fr 6.5 mins. 16. Piranha clean. 17. Gate xide grwth: N-type drive-in furnace, 0.1 /im f dry xide, 27. Piranha clean. 28. HMDS dry. 29. Evaprate 0.4 t 0.6 micrns f aluminum. 30. Psitive phtresist step: (Metallizatin mask) (a). Dry 02 at 1.5 liters/min., 1000 C fr 110 mins. (a). HMDS dry. (b). Dry N2 at 1.0 liters/min., 900 C fr 10 mins. (b). Apply AZ1350J psitive phtresist and spin at 8000 rpm fr 30 sees. 18. Negative phtresist step: (Depletin-implant mask)

113 (c). Prebake at 90 C fr 45 mins. (d). Expse mask fr 15 sees. (e). Develp with AZ1350J develper: DI (1:1) fr 45 sees. (0. Light DI rinse. (g). Pstbake at90 C fr 30 mins. (h). Aluminum etch with type-a etchant at 60 Cwith light agitatin. (i). DI rinse. 0)- Acetne PR strip fr 5 mins. (k). DI rinse. (1). N2 blwdry Sintering treatment: Sintering ven at 450 C fr 5mins. with N2:H2 (frming gas) (9:1) at 1 liters/min. Appendix 2 NMOS ENHANCEMENT-DEPLETION DEVICE CHARACTERISTICS The NMOS enhancement-depletin metal-gate prcess was described in Appendix 1, and the characteristics f the transistrs fabricated with that prcess are briefly described in this appendix. Figure A2.1 shws aseries f enhancement device characteristics fr adevice with a0.4 mil channel width, and a1.0 mil channel length fr 0and 5vlts f bdy bias. Frm these curves, the zer-bias threshld vltage is fund t be abut 0.5 vlts; Xis abut 0.01 vlts-1, and y is abut 0.6 vlts1''2. Atypical set f I-V curves fr adepletin device with awf 0.4 mils, and an Lf 1.0 mils is shwn in Fig. A2.2. Frm this data, the zer-bias depletin thres hld is fund t be abut -3.5 vlts, and the ther parameters are similar t thse fr the enhancement device abve. The perfrmance parameters f the peratinal amplifier were estimated using the device data abve, and gd agreement was btained between the predicted values and the experimental values using first-rder mdelling equatins. 214

114 > ibheblrn il r: j m 1 a is IVJttl fibbi JBB * " 'ri c? IHDWI (c) O S.0 cr cl Vjl 1 "3 p r- 3 *: r s's- = "H. n I1 II c/j a. r < 3-