HI Bit, 500 MSPS, Flash A/D Converter. Features. Description. Ordering Information. Applications

Transcription

1 August Bit, 500 MSPS, Flash A/D Converter Features Differential Linearity Error ±0.5 LSB Integral Linearity Error ±0.7 LSB Built-In Integral Linearity Compensation Circuit Ultra High Speed Operation with Maximum Conversion ate (Min) MSPS Low Input Capacitance (Typ) pF Wide Analog Input Bandwidth (Min for Full Scale Input) MHz Single Power Supply V Low Power Consumption (Typ) W Low Error ate Capable of Driving 50Ω Loads Direct eplacement for Sony CXA276K Description The HI276 is an 8-bit, ultra-high-speed, flash Analog-to- Digital converter IC capable of digitizing analog signals at a maximum rate of 500 MSPS. The digital I/O levels of this A/D converter are compatible with ECL 00K/0KH/0K. The HI276 is available in the Industrial temperature range and is supplied in a 68 lead ceramic LCC package. Ordering Information PAT NUMBE TEMP. ANGE ( o C) PACKAGE PKG. NO. HI276AIL -20 to Ld CLCC J68.B HI276-EV 25 Evaluation Board Applications adar Systems Communication Systems Digital Oscilloscopes Direct F Down-Conversion Pinout HI276 (CLCC) HEAT SINK UP, ECESSED CAVITY DOWN AGND V T V TS NC LINV O O D0 D0 D D DGND NC 0 NC 2 NC 3 AGND 4 V IN 5 V IN 6 AGND 7 V M 8 AGND 9 V IN2 20 V IN2 2 AGND 22 NC 23 NC 24 NC 25 NC DGND2 59 D2 58 D D3 55 D3 54 DGND2 53 DGND2 52 DGND 5 DGND 50 D4 49 D D5 46 D5 45 NC 44 DGND AGND V B V BS NC MINV D7 D7 D6 D6 DGND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. or Copyright Intersil Corporation File Number

2 Functional Block Diagram MINV V T 6 COMPAATO 37 V TS 5 2 / O 67 O 39 D7 (MSB) 38 D7 4 D6 V IN D6 D5 D5 D4 65 OUTPUT 49 D D3 D3 D2 V M ENCODE LOGIC D2 D D D0 (LSB) D0 9 V IN V BS 3 4 /2 255 V B CLOCK DIVE LINV 4-2

3 Absolute Maximum atings T A = 25 o C Supply Voltage (, ) V to +0.5V Analog Input Voltage (V IN ) to +0.5V eference Input Voltage V T, V B, V M to +0.5V V T - V B V Digital Input Voltage MINV, LINV V to +0.5V,, to +0.5V V V M Pin Input Current (I VM ) mA to +3mA Digital Output Current (ID0 to ID7, IO, ID0 to ID7, IO) mA to 0mA Operating Conditions (Note ) Supply Voltage MIN TYP MAX, V -5.2V -4.95V V 0V 0.05V AGND - DGND V 0V 0.05V Temperature ange (Note 5) T C o C - 00 o C Thermal Information Thermal esistance (Typical) θ o JA C/W θjc o C/W CLCC Package Maximum Junction Temperature o C Maximum Storage Temperature ange (T STG ) o C to 50 o C Maximum Lead Temperature (Soldering 0s) o C eference Input Voltage MIN TYP MAX V T V -2 0.V V B V V Analog Input Voltage, V IN V B - V T CAUTION: Stresses above those listed in Absolute Maximum atings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications T A = 25 o C, = = -5.2V, V T, V TS = 0V, V B, V BS = -2V (Note ) PAAMETE TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PEFOMANCE esolution Bits Integral Linearity Error, INL f C = 500 MSPS - ±0.3 ±0.7 LSB Differential Linearity Error, DNL f C = 500 MSPS - ±0.3 ±0.5 LSB DYNAMIC CHAACTEISTICS Signal to Noise and Distortion atio, SINAD Input = khz, Full Scale db f C = 500 MSPS MS Signal = MS Noise + Distortion Input = 00MHz, Full Scale db f C = 500 MSPS Error ate Input = 00MHz, Full Scale Error > 6 LSB, f C = 400 MSPS Input = 25MHz, Full Scale Error > 6 LSB, f C = 500 MSPS NTSC 40 IE Mod. amp, f C = 500 MSPS TPS (Note 3) TPS (Note 3) Differential Gain Error, DG % Differential Phase Error, DP Degree Overrange ecovery Time ns Maximum Conversion ate, f C MSPS Aperture Jitter, t AJ Input = 50MHz - - ps Sampling Delay, t DS Input = 50MHz ns ANALOG INPUT Analog Input Capacitance, C IN V IN = V V MS pf Analog Input esistance, IN kω Input Bias Current, I IN V IN = -V µa Full Scale Input Bandwidth V IN = 2V P-P MSPS EFEENCE INPUTS eference esistance, EF Ω 4-3

4 Electrical Specifications T A = 25 o C, = = -5.2V, V T, V TS = 0V, V B, V BS = -2V (Note ) (Continued) esidual esistance Note Ω Ω Ω Ω Ω DIGITAL INPUTS Logic H Level, V IH V Logic L Level, V IL V Logic H Current, I IH Input Connected to -0.8V 0-70 µa Logic L Current, I IL Input Connected to -.6V µa Input Capacitance pf DIGITAL OUTPUTS Logic H Level, V OH L = 50Ω V Logic L Level, V OL L = 50Ω V TIMING CHAACTEISTICS Clock Duty Cycle % Output ise Time, t r L = 50Ω, 20% to 80% ns Output Fall Time, t f L = 50Ω, 80% to 20% ns Output Delay, t OD ns POWE SUPPLY CHAACTEISTICS Supply Current, I EE ma Power Consumption, P D Note W NOTES:. Electrical Specifications guaranteed within stated operating conditions. 2. See Functional Block Diagram. 3. TPS: Times Per Sample. ( V T V B ) 2 4. P D = I EEA + I EED EF 5. T A is specified in still air and without heatsink. To extend temperature range, appropriate heat management techniques must be employed (See Figure 2). Timing Diagram PAAMETE TEST CONDITIONS MIN TYP MAX UNITS ANALOG IN t DS N + N + 2 t PW t PW0 DIGITAL OUT N - 20% 80% N 80% N + 20% t OD t r t f FIGUE. 4-4

5 Typical Performance Curves THEMAL ESISTANCE θ JA ( o C/W) 0 SUPPLY CUENT (A) AI FLOW (m/s) FIGUE 2. THEMAL ESISTANCE MOUNTED ON-BOAD CASE TEMPEATUE ( o C) FIGUE 3. SUPPLY CUENT vs TEMPEATUE CHAACTEISTICS HIGH LEVEL VOLTAGE (V) EGISTE STING CUENT (ma) CASE TEMPEATUE ( o C) FIGUE 4. DO PIN HIGH LEVEL VOLTAGE vs TEMPEATUE CHAACTEISTICS CASE TEMPEATUE ( o C) FIGUE 5. EGISTE STING CUENT vs TEMPEATUE CHAACTEISTICS LOW LEVEL VOLTAGE (V) PIN OPEN VOLTAGE (V) CASE TEMPEATUE ( o C) FIGUE 6. D0 PIN LEVEL VOLTAGE vs TEMPEATUE CHAACTEISTICS CASE TEMPEATUE ( o C) FIGUE 7. PIN OPEN VOLTAGE vs TEMPEATUE CHAACTEISTICS 4-5

6 Typical Performance Curves (Continued) SINAD (db) HAMONICS (db) THID HAMONIC SECOND HAMONIC INPUT FEQUENCY (MHz) FIGUE 8. SINAD vs INPUT FEQUENCY CHAACTEISTICS INPUT FEQUENCY (MHz) FIGUE 9. HAMONIC DISTOTION vs INPUT FEQUENCY CHAACTEISTICS 0-6 INPUT FEQUENCY = CLOCK FEQUENCY/4 + khz 6 LSB O MOE EO 0-6 EO ATE (TPS) FEQUENCY (MHz) FIGUE 0. EO ATE vs CONVESION FEQUENCY CHAACTEISTICS EO ATE (TPS) CLOCK FEQUENCY: 500 MSPS INPUT FEQUENCY: 25.00MHz FULL SCALE 6 LSB O MOE EO DUTY CYCLE (%) FIGUE. EO ATE vs CLOCK DUTY CYCLE CHAACTEISTICS 0-3 INPUT FEQUENCY = CLOCK FEQUENCY/ 4 + khz FULL SCALE INPUT EO ATE (TPS) CLOCK FEQUENCY 500 MSPS 550 MSPS 450 MSPS THESHOLD LEVEL (LSB) FIGUE 2. EO ATE vs THESHOLD LEVEL CHAACTEISTICS 4-6

7 Pin Descriptions PIN NUMBE SYMBOL I/O STANDAD VOLTAGE LEVEL EQUIVALENT CICUIT DESCIPTION LINV I ECL DGND Polarity Selection for LSBs (refer to the A/D Output Code Table.) Pulled low when left open. 37 MINV Polarity Selection for MSB (refer to the A/D Output Code Table). Pulled low when left open. LINV O MINV V V T I 0V V T 6 Analog eference Voltage (Top) (0V Typ). 5 V TS O 0V V TS 2 eference Voltage Sense (Top). 5 8 V M I V B/2 eference Voltage Mid Point. Can /2 be used for linearity compensation. 3 V BS O -2V eference Voltage Sense (Bottom). 30 V B I -2V Analog eference Voltage (Bottom). V M 8 3 TO COMPAATOS V BS 3 4 /2 V B , 6 V IN I V TS to V 9, 4, 7, BS Analog Input. All of the pins must V IN 9, 22, 27 AGND be wired externally. 20, 2 V IN V IN2 TO COMP. 0 TO TO

8 Pin Descriptions (Continued) PIN NUMBE SYMBOL I/O STANDAD VOLTAGE LEVEL EQUIVALENT CICUIT DESCIPTION 35 I ECL DGND Input Complementary Input. Pulled down to -.3V when left open , 39 D7, D7 O ECL MSB and Complementary Msb Data Output. DGND2 40, 4 D6, D D to D6: Data output D to D6: Complementary data 46, 47 D5, D5 DI output 49, 50 D4, D4 55, 56 D3, D3 DI 58, 59 D2, D2 63, 64 D, D 65, 66 D0, D0 LSB Data Complementary Output LSB Data Output. 67, 68 O, O Overrange and Complementary Overrange Output. 2, 3, 7, 8, 2, 28, 29, 33, 34 9, 4, 7, 9, 22, 27 42, 48, 57, 62 43, 5, 52, 6 44, 53, 54, 60 AGND DGND DGND V Analog Supply. Internally connected to (resistance: 4Ω to 6Ω). AGND 0V Analog Ground. INTENAL INTENAL ANALOG DIGITAL -5.2V CICUIT CICUIT Digital Supply. Internally connected 4Ω TO 6Ω to (resistance: 4Ω to 6Ω). DGND 0V D D Digital Ground. DGND2 (Note 6) 0V Digital Ground for Output Drive. 4, 0,, 3, 23, 24, 25, 26, 32 NC No-Connect pins. It is recommended to wire these pins to AGND. 45 NC No-Connect pin. It is recommended to wire these pins to DGND. NOTE: 6. V T = V TS = 0V, V M = -V or open, V B = V BS = -2V 4-8

9 A/D OUTPUT CODE TABLE (NOTE ) MINV, LINV 0,, 0 0, 0 V IN STEP O D7 D0 O D7 D0 O D7 D0 O D0 D7 0V V V Test Circuits FUNCTION GENEATO NTSC SIGNAL SOUCE 2 AMP V IN DUT 8 ECL 8 2Ω HI276 LATCH 0 0 HI BIT D/A AMP 2 fms -2V 0V SG (CW) 50 DUTY -4.5V DIVIDE SWITCH POSITION. MAXIMUM CONVESION ATE 2. DG/DP VECTO SCOPE DG/DP OSCILLO- SCOPE MAXIMUM CONVESION ATE FIGUE 3. MAXIMUM CONVESION ATE AND DIFFEENTIAL GAIN/PHASE EO TEST CICUIT +V S2 - + S S : A < B : ON S2 : A > B : ON DVM V IN -V A<B A>B COMPAATO DUT 8 8 A8 B8 HI276 TO TO A B 0 A0 B0 (250 MSPS) CONTOLLE BUFFE FIGUE 4. INTEGAL AND DIFFEENTIAL LINEAITY EO TEST CICUIT TO 0 4-9

10 Test Circuits (Continued) -5.2V A I EED HI V -5.2V A I EEA -V A I IN FIGUE 5. POWE SUPPLY AND ANALOG INPUT BIAS CUENT TEST CICUIT V IN 0V -V -2V 00MHz OSC φ: VAIABLE AMP f OSC2 00MHz V IN ECL BUFFE HI276 8 LOGIC ANALYZE 024 SAMPLES V IN υ t t APETUE JITTE σ (LSB) Aperture jitter is defined as follows: t AJ = σ υ = σ πf, t 2 Where σ (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGUE 6A. FIGUE 6B. APETUE JITTE TEST METHOD FIGUE 6. SAMPLING DELAY AND APETUE JITTE TEST CICUIT 4-0

11 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Sales Office Headquarters NOTH AMEICA Intersil Corporation P. O. Box 883, Mail Stop Melbourne, FL TEL: (407) FAX: (407) For information regarding Intersil Corporation and its products, see web site EUOPE Intersil SA Mercure Center 00, ue de la Fusee 30 Brussels, Belgium TEL: (32) FAX: (32) ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 0 Fu Hsing North oad Taipei, Taiwan epublic of China TEL: (886) FAX: (886)