UC184xA / 284xA / 384xA

Transcription

1 UC14xA / 24xA / 4xA C UENT M ODE PWM C ONTOLLE T HE I NFINITE P OWE OF I NNOVATION P ODUCTION D ATA S HEET DESCIPTION The UC14xA family of control ICs provides all the necessary features to implement off-line fixed-frequency, current-mode switching power supplies with a minimum of external components. The current mode architecture demonstrates improved load regulation, pulseby-pulse current limiting and inherent protection of the power supply output switch. The IC includes: A bandgap reference trimmed to ±1% accuracy, an error amplifier, a current sense comparator with internal clamp to 1V, a high current totem pole output stage for fast switching of power MOSFET's, and an externally programmable oscillator to set frequency and maximum duty cycle. The undervoltage lock-out is designed to operate with 20µA typ. start-up current, allowing an efficient bootstrap supply voltage design. Available options for this family of products, such as startup voltage hysteresis and duty cycle, are summarized below in the Available Options section. The UC14xA family of control ICs is also available in 14-pin SOIC package which makes the Power Output Stage Collector and Ground pins available. IMPOTANT: For the most current data, consult MICOSEMI s website: PODUCT HIGHLIGHT AISON OF UC4XA VS. SG4X DISCHAGECUENT SG4x Min. Limit T A =2C UC4xA SG4x Max. Limit KEY FEATUES LOW STAT-UP CUENT. (0.mA max.) TIMMED OSCILLATO DISCHAGE CUENT. (See Product Highlight) OPTIMIZED FO OFF-LINE AND DC-TO-DC CONVETES. AUTOMATIC FEED FOWAD ENSATION. PULSE-BY-PULSE CUENT LIMITING. ENHANCED LOAD ESPONSE CHAACTEISTICS. UNDE-VOLTAGE LOCKOUT WITH HYSTEESIS. DOUBLE PULSE SUPPESSION. HIGH-CUENT TOTEM POLE. INTENALLY TIMMED BANDGAP EFEENCE. 00KHz OPEATION. LOW O EO AMPLIFIE. KEY FEATUES ECONOMICAL OFF-LINE FLYBACK O FOWAD CONVETES. DC-DC BUCK O BOOST CONVETES. LOW COST DC MOTO CONTOL s Mean +s Discharge Current Distribution - ma Available Options Part# Start-Up Max. Duty Hysteresis Voltage Cycle UCx42A 1V V <100% UCx4A.4V 0.V <100% UCx44A 1V V <0% UCx4A.4A 0.V <0% T A ( C) M Plastic DIP -Pin PACKAGE ODE INFO DM Plastic SOIC -Pin D Plastic SOIC 14-Pin Y Ceramic DIP -Pin ohs Compliant / Pb-free Transition DC: 00 ohs Compliant / Pb-free Transition DC: to 0 UC4xAM UC4xADM UC4xAD to + UC24xAM UC24xADm UC24xAD UC24xAY - to UC14xAY Note: Available in Tape & eel. Append the letters T to the part number. (i.e. UC42ADM-T) ev. 1.2a, L INF INITY M ICOELECTONICS I NC. 111 WESTEN AVENUE, GADEN GOVE, CA. 9241, , FAX:

2 UC14xA/24xA/4xA PODUCT DATABOOK 199/199 P O D U I O N D ATA S H E E T ABSOLUTE MAXIMUM ATINGS (Note 1) Supply Voltage (Low Impedance Source) ( )... 0V Supply Voltage (I CC < 0mA)... Self Limiting Output Current... ±1A Output Energy (Capacitive Load)... µj Analog Inputs ( & ) V to +.V Error Amp Output Sink Current... 10mA Power Dissipation at T A = 2 C (M Package)... 1W Storage Temperature ange... - C to +10 C Lead Temperature (Soldering, 10 Seconds) C Peak Package Solder eflow Temp. (40 second max. exposure)...20 C (+0, -) Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Pin numbers refer to DIL packages only. THEMAL DATA M PACKAGE: THEMAL ESISTANCE-JUNCTION TO AMBIENT, θ JA 9 C/W DM PACKAGE: THEMAL ESISTANCE-JUNCTION TO AMBIENT, θ JA 1 C/W D PACKAGE: THEMAL ESISTANCE-JUNCTION TO AMBIENT, θ JA 120 C/W Y PACKAGE: THEMAL ESISTANCE-JUNCTION TO AMBIENT, θ JA 10 C/W Junction Temperature Calculation: = T A + (P D x θ JA ). The θ JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow PACKAGE PIN OUTS / N.C. N.C. N.C. / / M & Y PACKAGE (Top View) DM PACKAGE (Top View) GND GND N.C. V C GND PW GND D PACKAGE (Top View) ohs / Pb-free 100% Matte Tin Lead Finish 2

3 PODUCT DATABOOK 199/199 P O D U I O N D ATA S H E E T UC14xA/24xA/4xA ELECTICAL CHAACTEISTICS (Unless otherwise specified, these specifications apply over the operating ambient temperatures for UC4xA with 0 C T A 0 C, UC24xA with -40 C T A C, UC14xA with - C T A 12 C; =1V; =10K; =.nf. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.) Parameter Symbol Test Conditions UC14xA/24xA UC4xA Min. Typ. Max. Min. Typ. Max. Units eference Section Output Voltage = 2 C, I L = 1mA Line egulation 12 V IN 2V Load egulation 1 I O 20mA Temperature Stability (Note 2 & ) Total Output Variation Over Line, Load, and Temperature Output Noise Voltage (Note 2) V N 10Hz f 10kHz, = 2 C Long Term Stability (Note 2) T A = 12 C, t = 1000hrs Output Short Circuit Current I SC Oscillator Section Initial Accuracy (Note ) = 2 C Voltage Stability 12 2V Temperature Stability (Note 2) T MIN T A T MAX Amplitude (Note 2) Discharge Current = 2 C, V PIN 4 = 2V V PIN 4 = 2V, T MIN T A T MAX Error Amp Section Input Voltage V PIN 1 = 2.V Input Bias Current I B Open Loop Gain A VOL 2 V O 4V Unity Gain Bandwidth (Note 2) UGBW T j = 2 C Power Supply ejection atio (Note ) PS 12 2V Output Sink Current I OL V PIN 2 = 2.V, V PIN 1 = 1.1V Output Source Current I OH V PIN 2 = 2.V, V PIN 1 = V Output Voltage High Level V OH V PIN 2 = 2.V, L = 1K to ground Output Voltage Low Level V OL V PIN 2 = 2.V, L = 1K to Current Sense Section Gain (Note & 4) A VOL Maximum Input Signal (Note ) V PIN 1 = V Power Supply ejection atio (Note ) PS 12 2V Input Bias Current I B Delay to Output (Note 2) T pd V PIN = 0 to 2V Output Section Output Low Level I V SINK = 20mA OL I SINK = 200mA Output High Level I V SOUCE = 20mA OH I SOUCE = 200mA ise Time (Note 2) T = 2 C, C L = 1nF Fall Time (Note 2) T F = 2 C, C L = 1nF UVLO Saturation V SAT = V, I SINK = 10mA (Electrical Characteristics continue next page.) V mv 2 2 mv mv/ C V 0 0 µv 2 2 mv ma khz % % V ma.... ma V µa db MHz db 2 2 ma ma V V V/V V 0 0 db µa ns V V V V ns ns V

4 UC14xA/24xA/4xA PODUCT DATABOOK 199/199 P O D U I O N D ATA S H E E T Under-Voltage Lockout Section Start Threshold ELECTICAL CHAACTEISTICS (Con't.) Parameter Symbol Test Conditions Min. Operation Voltage After Turn-On PWM Section x42a/4a x4a/a x42a/4a x4a/a Maximum Duty Cycle x42a/a x44a/a Minimum Duty Cycle Total Standby Section Start-Up Current Operating Supply Current I CC Zener Voltage V Z I CC = 2mA Notes: 2. These parameters, although guaranteed, are not 100% tested in production.. Parameter measured at trip point of latch with V VFB = 0. V 4. Gain defined as: A VOL = ; 0 V ISENSE 0.V. V ISENSE. Adjust above the start threshold before setting at 1V.. Output frequency equals oscillator frequency for the UC142A and UC14A. Output frequency is one half oscillator frequency for the UC144A and UC14A. UC14xA/24xA UC4xA Units Min. Typ. Max. Min. Typ. Max V V V V % % 0 0 % ma ma 0 0 V. "Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: Temp Stability = (max.) - (min.) (max.) - (min.) (max.) & (min.) are the maximum & minimum reference voltage measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature." BLOCK DIAGAM * ** GOUND 4V UVLO 1V (142A/4A).4V (14A/A) 2.V UVLO Hysteresis V (142A/4A) 0.V (14A/A) S / V ef Good Logic Internal Bias.0V 0mA V C * / Oscillator Error Amp 2 *** S T CUENT SENSE 1V Current Sense Comparator PWM Latch POWE GOUND ** * - V and V are internally connected for pin packages. CC C ** - POWE GOUND and GOUND are internally connected for pin packages. *** - Toggle flip flop used only in x44a and x4a series. 4

5 PODUCT DATABOOK 199/199 P O D U I O N D ATA S H E E T UC14xA/24xA/4xA CHAACTEISTIC CUVES FIGUE 1. OSCILLATO FEQUENCY vs. TIMING ESISTO Oscillator Frequency - (Hz) 1M 100k 10k = 4.nF = 1nF = 2.2nF / 4 GOUND For > k, f k.0k 10.0k 0.0k 100k Note: Output drive frequency is half the oscillator frequency for the UCx44A/A devices. - (ohms) FIGUE 2. MAXIMUM DUTY CYCLE vs. TIMING ESISTO Maximum Duty Cycle - (%) k.0k 10.0k 0.0k 100k - (ohms)

6 UC14xA/24xA/4xA PODUCT DATABOOK 199/199 P O D U I O N D ATA S H E E T TYPICAL APPLICATION CICUITS FIGUE. CUENT SENSE SPIKE SUPPESSION DC BUS FIGUE 4. MOSFET PAASITIC OSCILLATIONS DC BUS UCx4xA Q1 UCx4xA 1 Q1 CHANGE I PK S C S I PK(MAX) = 1.0V S The C low pass filter will eliminate the leading edge current spike caused by parasitics of Power MOSFET. A resistor ( 1 ) in series with the MOSFET gate will reduce overshoot & ringing caused by the MOSFET input capacitance and any inductance in series with the gate drive. (Note: It is very important to have a low inductance ground path to insure correct operation of the I.C. This can be done by making the ground paths as short and as wide as possible.) FIGUE. EXTENAL DUTY CYCLE CLAMP AND MULTI-UNIT SYNCHONIZATION A 4 B TIME 4 UCx4xA f = (A + 2 B )C 0.01 To other UCx4xA devices f = B A + 2 B Precision duty cycle limiting as well as synchronizing several parts is possible with the above circuitry.

7 PODUCT DATABOOK 199/199 P O D U I O N D ATA S H E E T UC14xA/24xA/4xA TYPICAL APPLICATION CICUITS (continued) FIGUE. SLOPE ENSATION DC BUS UCx4xA (12) V V O (14) UVLO S V EF 2N222A 2.V INTENAL BIAS GOOD LOGIC (11) SLOPE 4() OSCILLATO Q1 From V O i d C F 2() F EO AMP 2 1V C.S. PWM LATCH (10) () 1(1) (9) () C S Due to inherent instability of current mode converters running above 0% duty cycle, slope compensation should be added to either the current sense pin or the error amplifier. Figure shows a typical slope compensation technique. FIGUE. OPEN LOOP LABOATOY FIXTUE 2N2222 UCx4xA A 4.K 100K 1 1K EO AMP ADJUST 4.K K ADJUST 2 0.1µF 0.1µF 1K 4 GOUND GOUND High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected to pin in a single point ground. The transistor and k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin.

8 UC14xA/24xA/4xA PODUCT DATABOOK 199/199 P O D U I O N D ATA S H E E T TYPICAL APPLICATION CICUITS (continued) FIGUE. OFF-LINE FLYBACK EGULATO 4.k 1W TI MB AC INPUT 1N4004 1N4004 1N4004 1N µF 20V 140k 1/2W 4.k 2W 1N49 00pF 400V 1N49 400µF 10V V 2-A 1V.k 20k 10k 100pF UC44A 2 1 OUT 0.01µF 2k 10µF 20V IF0 1N49 20pF 2.k 0.01µF 10k µF / CU SEN GND 1k 40pF 0.k ISOLATION BOUNDAY SPECIFICATIONS Input line voltage: 90VAC to 10VAC Input frequency: 0 or 0Hz Switching frequency: 40KHz ±10% Output power: 2W maximum Output voltage: V +% Output current: 2 to A Line regulation: 0.01%/V Load regulation: %/A* 2 Watts, V IN = 90VAC: 0% V IN = 10VAC: % Output short-circuit current: 2.Amp average * This circuit uses a low-cost feedback scheme in which the DC voltage developed from the primary-side control winding is sensed by the UC44A error amplifier. Load regulation is therefore dependent on the coupling between secondary and control windings, and on transformer leakage inductance.