DATASHEET IPM6220A. Features. Ordering Information. Applications. Related Literature. Pinout

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1 NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT conac our Technical Suppor Cener a 1888INTERSIL or Augus 2004 Advanced Triple PWM and Dual Linear Power Conroller for Porable Applicaions DATASHEET FN9032 Rev 1.00 The IPM6220A provides a highly inegraed power conrol and proecion soluion for five oupu volages required in highperformance noebook PC applicaions. The IC inegraes hree fixed frequency pulsewidhmodulaion (PWM) conrollers and wo linear regulaors along wih monioring and proecion circuiry ino a single 24 lead SSOP package. The wo PWM conrollers ha regulae he sysem main 5V and 3.3V volages are implemened wih synchronousrecified buck converers. Synchronous recificaion and hysereic operaion a ligh loads conribue o high efficiency over a wide range of inpu volage and load variaion. Efficiency is furher enhanced by using he lower MOSFET s r DS(ON) as he curren sense elemen. Inpu volage feedforward ramp modulaion, currenmode conrol, and inernal feedback compensaion provide fas and sable handling of inpu volage load ransiens encounered in advanced porable compuer chip ses. The hird PWM conroller is a boos converer ha regulaes a resisor selecable oupu volage of nominally 12V. Two inernal linear regulaors provide 5V ALWAYS and 3.3V ALWAYS low curren oupus required by he noebook sysem conroller. Ordering Informaion PART NUMBER TEMP. RANGE ( C) PACKAGE PKG. DWG. # IPM6220ACA 10 o Ld SSOP M24.15 IPM6220ACAZ (Noe) IPM6220ACAZT (Noe) IPM6220ACAZAT (Noe) IPM6220EVAL1 10 o Ld SSOP (Pbfree) M o Ld SSOP Tape & Reel (Pbfree) 10 o Ld SSOP Tape & Reel (Pbfree) Evaluaion Board M24.15 M24.15 NOTE: Inersil Pbfree producs employ special Pbfree maerial ses; molding compounds/die aach maerials and 100% mae in plae erminaion finish, which is compaible wih boh SnPb and Pbfree soldering operaions. Inersil Pbfree producs are MSL classified a Pbfree peak reflow emperaures ha mee or exceed he Pbfree requiremens of IPC/JEDEC J Sd020B. Feaures Provides Five Regulaed Volages 5V ALWAYS 3.3V ALWAYS 5V Main 3.3V Main 12V High Efficiency Over Wide Line and Load Range Synchronous Buck Converers on Main Oupus Hysereic Operaion a Ligh Load No CurrenSense Resisor Required Uses MOSFET s r DS(ON) Opional CurrenSense Resisor for More Precision Operaes Direcly From Baery 5.6 o 22V Inpu Inpu Undervolage LockOu (UVLO) Excellen Dynamic Response Volage FeedForward and CurrenMode Conrol Moniors Oupu Volages Synchronous Converers Operae Ou of Phase Separae ShuDown Pins for Advanced Configuraion and Power Inerface (ACPI) Compaibiliy 300kHz Fixed Swiching Frequency on Main Oupus Thermal ShuDown Proecion Pbfree Available Applicaions Mobile PCs HandHeld Porable Insrumens Relaed Lieraure Applicaion Noe AN9915 Pinou VBATT 3.3V ALWAYS BOOT2 UGATE2 PHASE2 5V ALWAYS LGATE2 PGND2 ISEN2 IPM6220A (SSOP) TOP VIEW VSEN2 10 SDWN2 11 PGOOD BOOT1 23 UGATE1 22 PHASE1 21 ISEN1 20 LGATE1 19 PGND1 18 VSEN1 17 SDWN1 16 GATE3 15 VSEN3 14 GND 13 SDWNALL FN9032 Rev 1.00 Page 1 of 14

2 FN9032 Rev 1.00 Page 2 of 14 Block Diagram VSEN3 VSEN2 CLK1 BOOT2 UGATE2 PHASE2 LGATE2 PGND2 VCC HGDR2 LGDR2 EA2 LGATE2 RAMP 2 GATE LOGIC 2 VBATT CLK 200ns LGATE2 BOOST CONTROLLER REF CLK2 OVP2 HYST COMP2 GATE3 PWMMD2 HI LO CLK2 SHUTOFF DEADTIME PWM/HYST PWM ON HYST ON CLK1 RAMP 1 OC COMP2 OC VCC PWM 2.8V LOGIC2 LATCH 2 UVFLT OVP1 OVP2 D Q R > Q OUTPUT VOLTAGE MONITOR GND UVFLT POWERON RESET (POR) PGOOD FIGURE 1. POR PWM VCC LATCH 1 Q D R Q < SDWN LDO2 PWMMD1 VBATT LDO1 3.3VALWAYS OC LOGIC1 REF VOLT SECOND CLAMP PWM MODE 2 PWMMD2 R1 = 20K ISEN2 VOLT SECOND CLAMP GATE LOGIC 1 SHUTOFF DEADTIME PWM/HYST PWM ON HYST ON VSEN1 HI LO OC COMP1 VCC 5VALWAYS EA1 LGATE1 HGDR1 HYST COMP1 VCC LGDR1 PWMMD1 SDWN REF OVP1 CLK1 R1 = 20K POR REFERENCE AND SOFT START 2.5V REF PWM MODE 1 BOOT1 UGATE1 PHASE1 LGATE1 PGND1 ISEN1 LGATE1 SDWN1 SDWN2 SDWNALL VSEN1 IPM6220A

3 Simplified Power Sysem Diagram VBATT VBATT 3.3V ALWAYS 5V ALWAYS LINEAR CONTROLLER LINEAR CONTROLLER PWM1 CONTROLLER Q1 Q2 5V MAIN VBATT IPM6220A VOLTAGE, CURRENT MONITORS PGOOD 12V BOOST 3.3V MAIN Q1 PWM2 CONTROLLER PWM3 CONTROLLER Q2 FIGURE 2. Typical Applicaion V BATT PROCESSOR SDWN1 SDWN2 5V MAIN 3.3V MAIN V CORE P CORE IPM6220A 5V ALWAYS 3.3V ALWAYS VID CODE C V PCM CIA ENABLE SDWN IPM6210 V I/O V CLOCK PGOOD PGOOD I/O CLOCK RESET SDWNALL ON/OFF FIGURE 3. FN9032 Rev 1.00 Page 3 of 14

4 Absolue Maximum Raings Inpu Volage, VBATT V Phase, ISEN and SDWNALL Pins GND 0.3V o 27.0V Boo and UGATE Pins V BOOT1, 2 wih Respec o PHASE1, V All Oher Pins V Operaing Condiions Inpu Volage, VBATT V o 24.0V Ambien Temperaure Range C o 85 C Juncion Temperaure Range C o 125 C Thermal Informaion Thermal Resisance (Typical, Noe 1) JA ( C/W) SSOP Package Maximum Juncion Temperaure (Plasic Package) C Maximum Sorage Temperaure Range C o 150 C Maximum Lead Temperaure (Soldering 10s) C (SSOP Lead Tips Only) CAUTION: Sresses above hose lised in Absolue Maximum Raings may cause permanen damage o he device. This is a sress only raing and operaion of he device a hese or any oher condiions above hose indicaed in he operaional secions of his specificaion is no implied. NOTE: 1. JA is measured wih he componen mouned on a low effecive hermal conduciviy es board in free air. See Tech Brief TB379 for deails. Elecrical Specificaions Recommended Operaing Condiions, Unless Oherwise Noed. Refer o Block and Simplified Power Sysem Diagrams, and Typical Applicaion Schemaic PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Inpu Quiescen Curren I CC SDWN1 = SDWN2 = 5V, SDWNALL = VIN, Oupus open circuied Sandby Curren I CCSB SDWN1 = SDWN2 = 0V, SDWNALL = VIN, Oupus open circuied ma 300 A Shudown Curren I CCSN SDWNALL = 0V <1.0 A Inpu Undervolage Lock Ou UVLO Rising VBATT V Inpu Undervolage Lock Ou UVLO VBATT, Hyseresis 300 mv OSCILLATOR PWM1,2 Oscillaor Frequency F c1, khz REFERENCE AND SOFT START Inernal Reference Volage V REF V Reference Volage Accuracy % SDWN1, SDWN2 Oupu Curren During Sarup I SS 5 A PWM1 CONVERTER, 5V Main Oupu Volage V OUT1 5.0 V Line and Load Regulaion 0.0 < IVOUT1 < 5.0A; 5.6V < VBATT < 22.0V % UnderVolage ShuDown Level V UV1 2 s delay, % Feedback Volage a VSNS1 pin % Curren Limi Threshold I OC2 Curren from ISNS1 Pin Through RSNS A OverVolage Threshold V OVP1 2 s delay, % Feedback Volage a VSNS1 pin % Maximum Duy Cycle DC MAX SDWN1 > 4.0V 94 % PWM2 CONVERTER, 3.3V Main Oupu Volage VOUT2 3.3 V Line and Load Regulaion 0.0 < IVOUT2 < 5.0A; 5.6V < VBATT < 24.0V % UnderVolage ShuDown Level V UV2 2 s delay, % Feedback Volage a VSNS2 pin % Curren Limi Threshold I OC2 Curren from ISNS2 Pin Through RSNS A OverVolage Threshold V OVP2 2 s delay, % Feedback Volage a VSNS2 pin % Maximum Duy Cycle DC MAX SDWN2 > 4.0V 94 % Inernal Resisance o GND on VSNS2 Pin R VSNS2 66K FN9032 Rev 1.00 Page 4 of 14

5 Elecrical Specificaions Recommended Operaing Condiions, Unless Oherwise Noed. Refer o Block and Simplified Power Sysem Diagrams, and Typical Applicaion Schemaic (Coninued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PWM1 and PWM2 CONTROLLER GATE DRIVERS Upper Drive PullUp Resisance R 2UGPUP 5 12 Upper Drive PullDown Resisance R 2UGPDN 4 10 Lower Drive PullUp Resisance R 2LGPUP 6 9 Lower Drive PullDown Resisance R 2LGPDN 5 8 PWM 3 CONVERTER 12V Feedback Regulaion Volage VSEN V 12V Feedback Regulaion Volage Inpu Curren I VSEN A Line and Load Regulaion 0.0 < IV OUT3 < 120mA, 4.9V< 5V Main <5.1V 2 2 % UnderVolage ShuDown Level V UV3 2 s delay, % Feedback Volage a VSNS3 pin % OverVolage Threshold V OVP3 2 s delay, % Feedback Volage a VSNS3 pin % PWM3 Oscillaor Frequency F c khz Maximum Duy Cycle 33 % PWM 3 CONTROLLER GATE DRIVERS PullUp Resisance R3GPUP 6 12 PullDown Resisance R3GPDN V and 3.3V ALWAYS Linear Regulaor Accuracy PWM1, 5V Oupu OFF (SDWN1 = 0V); 5.6V < VBATT < 22V; 0 < I LOAD < 50mA % 5V ALWAYS Oupu Volage Regulaion PWM1, 5V Oupu ON (SDWN1 = 5V); 0 < I LOAD < 50mA % Maximum Oupu Curren Combined 5V ALWAYS and 3.3V ALWAYS 50 ma Curren Limi Combined 5V ALWAYS and 3.3V ALWAYS ma 5V ALWAYS UnderVolage ShuDown 75 % Bypass Swich r DS(ON) PWM1, 5V Oupu ON (SDWN1 = 5V) 1.3 POWER GOOD AND CONTROL FUNCTIONS Power Good Threshold for PWM1 and PWM2 Oupu Volages % PGOOD Leakage Curren I PGLKG VPULLUP = 5.0V 1.0 A PGOOD Volage Low V PGOOD I PGOOD = 4mA V PGOOD Minimum Pulse Widh T PGmin 10 s SDWN1, 2, Low (Off) 0.8 V SDWN1, 2, High (On) 4.3 V SDWNALL High (On) 2.4 V SDWNALL Low (Off) SDWNALL, Hyseresis 40 mv OverTemperaure Shudown 150 C OverTemperaure Hyseresis 25 C FN9032 Rev 1.00 Page 5 of 14

6 Funcional Pin Descripions VBATT (Pin 1) Supplies all he power necessary o operae he chip. The IC sars o operae when he volage on his pin exceeds 4.7V and sops operaing when he volage on his pin drops below approximaely 4.5V. Also provides baery volage o he oscillaor for feedforward rejecion o inpu volage variaions. 3.3V ALWAYS (Pin 2) Oupu of 3.3V ALWAYS linear regulaor. 5V ALWAYS (Pin 6) Oupu of 5V ALWAYS linear regulaor or he 5V Main oupu. If he 5V Main oupu is enabled, i is swiched inernally from he VSEN1 pin o he 5V ALWAYS oupu. This improves efficiency and reduces he power dissipaion in he conroller. BOOT1, BOOT2 (Pins 24 and 3) Power is supplied o he upper MOSFET drivers of PWM1 and PWM2 converers via he BOOT pins. Connec hese pins o he respecive juncions of boosrap capaciors wih he cahodes of he boosrap diodes. Anodes of he boosrap diodes are conneced o pin 6, 5V ALWAYS. UGATE1, UGATE2 (Pins 23 and 4) These pins provide he gae drive for he upper MOSFETs. Connec UGATE pins o he respecive PWM converer s upper MOSFET gae. PHASE1, PHASE2 (Pins 22 and 5) The phase nodes are he juncions of he upper MOSFET sources, oupu filer inducors, and lower MOSFET drains. Connec he PHASE pins direcly o he respecive PWM converer s lower MOSFET drain. ISEN1, ISEN2 (Pins 21 and 9) These pins are used o monior he volage drop across he lower MOSFETs for curren feedback and currenlimi proecion. For more precise curren deecion, hese inpus can be conneced o opional curren sense resisors placed in series wih he sources of he lower MOSFETs. LGATE1, LGATE 2 (Pins 20 and 7) These pins provide he gae drive for he lower MOSFETs. Connec he lower MOSFET gae of each converer o he corresponding pin. PGND1, PGND2 (Pins 19 and 8) These are he lower MOSFET gae drive reurn connecion for PWM1 and PWM2 converers, respecively. Tie each lower MOSFET source direcly o he corresponding pin. VSEN1, VSEN2 (Pins 18, 10) These pins are conneced o he main oupus and provide he volage feedback signal for he respecive PWM conrollers. The PGOOD, overvolage proecion (OVP) and undervolage shudown circuis use hese signals o deermine oupuvolage saus and/or o iniiae undervolage shu down. The VSEN1 inpu is also swiched inernally o he 5V ALWAYS oupu if he 5V Main oupu is enabled. SDWNALL (Pin 13) This pin provides enable/disable funcion for all oupus. The chip is compleely disabled when his pin is pulled o ground. When his pin is pulled high, he 5V ALWAYS and 3.3 ALWAYS oupus are on and he oher oupus are enabled. The sae of 5V Main and 3.3V Main oupus depend on he volage on SDWN1 and SDWN2 respecively. See Table 1. SDWN1 (Pin 17) This pin provides enable/disable funcion and sofsar for he PWM1, 5V Main, oupu. The oupu is enabled when his pin is high and SDWNALL is also high. The 5V oupu is held off when he pin is pulled o he ground. SDWN2 (Pin 11) This pin provides enable/disable funcion and sofsar for PWM2, 3.3V Main, oupu. The oupu is enabled when his pin is high and SDWNALL is also high. The 3.3V oupu is held off when he pin is pulled o he ground. VSEN3 (Pin 15) This inpu pin is he volage feedback signal for PWM3, he boos conroller. The boos conroller regulaes his poin o a volage divided level of VDC. The PGOOD, overvolage proecion (OVP) and undervolage shudown circuis use his signal o deermine oupuvolage saus and/or o iniiae undervolage shu down. This pin can also be used o independenly disable he PWM3 conroller. Connec his pin o 5V ALWAYS if he boos converer is no populaed in your design. GATE3 (Pin 16) This pin drives he gae of he boos MOSFET. PGOOD (Pin 12) PGOOD is an open drain oupu used o indicae he saus of he PWM converers oupu volages. This pin is pulled low when any of he oupus excep PWM3 (12V) is no wihin 10% of respecive nominal volages, or when PWM3 (12V) is no wihin is undervolage and overvolage hresholds. GND (Pin 14) Signal ground for he IC. All volage levels are measured wih respec o his pin. General Descripion The IPM6220A addresses he sysem elecronics power needs of modern noebook and subnoebook PCs. The IC inegraes conrol circuis for wo synchronous buck converers for 5V Main and 3.3V Main buses, wo linear regulaors for 3.3V ALWAYS and 5V ALWAYS, and a 12V boos converer. FN9032 Rev 1.00 Page 6 of 14

7 The wo synchronous converers operae ou of phase o subsanially reduce he inpucurren ripple, minimizing inpu filer requiremens, minimizing baery heaing and prolonging baery life. The 12V boos conroller uses a 100kHz clock derived from he main clock. This conroller uses leading edge modulaion wih he maximum duy cycle limied o 33%. The chip has hree inpu conrol lines SDWN1, SDWN2 and SDWNALL. These are provided for Advanced Configuraion and Power Inerface (ACPI) compaibiliy. They urn on and off all oupus, as well as provide independen conrol of he 3.3V Main and 5V Main oupus. To maximize efficiency for he 5V Main and 3.3V Main oupus, he currensense echnique is based on he lower MOSFET r DS(ON). Lighload efficiency is furher enhanced by a hysereic mode of operaion which is auomaically engaged a ligh loads when he inducor curren becomes disconinuous. 3.3V Main and 5V Main Archiecure These main oupus are generaed from he unregulaed baery inpu by wo independen synchronous buck converers. The IC inegraes all he componens required for oupu volage sepoin and feedback compensaion, significanly reducing he number of exernal componens, saving board space and pars cos. The buck PWM conrollers employ a 300kHz fixed frequency currenmode conrol scheme wih inpu volage feedforward ramp programming for beer rejecion of inpu volage variaions. Figure 4 shows he ouofphase operaion for he 3.3V Main and 5V Main oupus. The phase node is he juncion of he upper MOSFET, lower MOSFET and he oupu inducor. The phase node is high when he upper MOSFET is conducing and he inducor curren rises accordingly. When he phase node is low, he lower MOSFET is conducing and he inducor curren is ramping down as shown. Curren Sensing and Curren Limi Proecion Boh PWM converers use he lower MOSFET onsae resisance, r DS(ON), as he currensensing elemen. This echnique eliminaes he need for a curren sense resisor and he associaed power losses. If more accurae curren proecion is desired, curren sense resisors may be used in series wih he lower MOSFETs source. To se he curren limi, place a resisor, RSNS, beween he ISEN inpus and he drain of he lower MOSFET (or opional curren sense resisor). The required value of he RSNS resisor is deermined from he following equaion: Rcs Vo RSNS = Iocdc 135 A L kHz 5A 0 A, V 5A 0 A, V V IN = 10.8V I L5V (2A/DIV.) 5V PHASE (10V/DIV.) 1 s/div. I L3.3V (2A/DIV.) 3.3V PHASE (10V/DIV.) FIGURE 4. OUT OF PHASE OPERATION where IOCDC is he desired DC overcurren limi; RCS is eiher he r DS(ON) of he lower MOSFET, or he value of he opional currensense resisor, Vo is he oupu volage and L is he oupu inducor. Also, he value of RCS should be specified for he expeced maximum operaing emperaure. The sensed volage, and he resuling curren ou of he ISEN pin hrough RSNS, is used for curren feedback and curren limi proecion. This is compared wih an inernal curren limi hreshold. When a sampled value of he oupu curren is deermined o be above he curren limi hreshold, he PWM drive is erminaed and a couner is iniiaed. This limis he inducor curren buildup and essenially swiches he converer ino currenlimi mode. If an overcurren is deeced beween 26 s o 53 s laer, an overcurren shudown is iniiaed. If during he 26 s o 53 s period, an overcurren is no deeced, he couner is rese and sampling coninues as normal. This curren limi scheme has proven o be very robus in applicaions like porable compuers where fas inducor curren buildup is common due o a large difference beween inpu and oupu volages and a low value of he inducor. LighLoad (Hysereic) Operaion In he lighload (hysereic) mode he oupu volage is regulaed by he hysereic comparaor which regulaes he oupu volage by mainaining he oupu volage ripple as shown in Figure 5. In Hysereic mode, he inducor curren flows only when he oupu volage reaches he lower limi of he hysereic comparaor and urns off a he upper limi. Hysereic mode saves converer energy a ligh loads by supplying energy only a he ime when he oupu volage requires i. This mode conserves energy by reducing he power dissipaion associaed wih coninuous swiching. During he ime beween inducor curren pulses, boh he upper and lower MOSFETs are urned off. This is referred o as diode emulaion mode because he lower MOSFET performs he funcion of a diode. This diode emulaion mode prevens FN9032 Rev 1.00 Page 7 of 14

8 he oupu capacior from discharging hrough he lower MOSFET when he upper MOSFET is no conducing. The gae drive is synchronized o he main clock, so he ouofphase iming is mainained in hysereic mode. Such a scheme insures a seamless ransiion beween he operaional modes. VOUT I L This ransiion echnique prevens jier of he operaion mode a load levels close o boundary. The oher mechanism for changing from hysereic o PWM is due o a sudden increase in he oupu curren. This sep load causes an insananeous decrease in he oupu volage due o he volage drop on he oupu capacior ESR. If he decrease causes he oupu volage o drop below he hysereic regulaion level, he mode is changed o PWM on he nex clock cycle. This insures he full power required by he increase in oupu curren. PHASE COMP I L MODE OF OPERATION PWM HYSTERETIC FIGURE 5. REGULATION IN HYSTERETIC MODE OperaionMode Conrol The modeconrol circui changes he converer s mode of operaion based on he volage polariy of he phase node when he lower MOSFET is conducing and jus before he upper MOSFET urns on. For coninuous inducor curren, he phase node is negaive when he lower MOSFET is conducing and he converers operae in fixedfrequency PWM mode as shown in Figure 6. When he load curren decreases o he poin where he inducor curren flows hrough he lower MOSFET in he reverse direcion, he phase node becomes posiive, and he mode is changed o hysereic. A phase comparaor handles he iming of he phase node volage sensing. A low level on he phase comparaor oupu indicaes a negaive phase volage during he conducion ime of he lower MOSFET. A high level on he phase comparaor oupu indicaes a posiive phase volage. When he phase node is posiive (phase comparaor high), a he end of he lower MOSFET conducion ime, for eigh consecuive clock cycles, he mode is changed o hysereic as shown in Figure 6. The dashed lines indicae when he phase node goes posiive and he phase comparaor oupu goes high. The solid verical lines a 1,2,...8 indicae he sampling ime, of he phase comparaor, o deermine he polariy (sign) of he phase node. A he ransiion beween PWM and hysereic mode, boh he upper and lower MOSFETs are urned off. The phase node will ring based on he oupu inducor and he parasiic capaciance on he phase node and sele ou a he value of he oupu volage. The mode change from hysereic o PWM can be caused by one of wo evens. One even is he same mechanism ha causes a PWM o hysereic ransiion. Bu insead of looking for eigh consecuive posiive occurrences on he phase node, i is looking for eigh consecuive negaive occurrences on he phase node. The operaion mode will be changed from hysereic o PWM when hese eigh consecuive pulses occur. PHASE NODE PHASE COMP MODE OF OPERATION PWM FIGURE 6. MODE CONTROL WAVEFORMS HYSTERETIC Gae Conrol Logic The gae conrol logic ranslaes generaed PWM conrol signals ino he MOSFET gae drive signals providing necessary amplificaion, level shifing and shoohrough proecion. Also, i has funcions ha help opimize he IC performance over a wide range of operaional condiions. Since MOSFET swiching ime can vary dramaically from ype o ype and wih he inpu volage, he gae conrol logic provides adapive dead ime by monioring he gaeosource volages of boh upper and lower MOSFETs. The lower MOSFET is no urned on unil he gaeosource volage of he upper MOSFET has decreased o less han approximaely 1 vol. Similarly, he upper MOSFET is no urned on unil he gaeosource volage of he lower MOSFET has decreased o less han approximaely 1 vol. This allows a wide variey of upper and lower MOSFETs o be used wihou a concern for simulaneous conducion, or shoohrough. 3.3V Main and 5V Main Sof Sar, Sequencing and Sandby See Table 1 for he oupu volage conrol algorihm. The 5V Main and 3.3V Main converers are enabled if SDWN1 and SDWN2 are high and SDWNALL is also high. The sandby mode is defined as a condiion when SDWN1 and SDWN2 are low and he PWM converers are disabled bu SDWNALL is high (3.3V FN9032 Rev 1.00 Page 8 of 14

9 ALWAYS and 5V ALWAYS oupus are enabled). In his power saving mode, only he low power microconroller and keyboard may be powered. TABLE 1. OUTPUT VOLTAGE CONTROL SDWNALL SDWN1 SDWN2 Sof sar of he 3.3V Main and 5V Main converers is accomplished by means of capaciors conneced from pins SDWN1 and SDWN2 o ground. In conjuncion wih 5 A inernal curren sources, hey provide a conrolled rise of he 3.3V Main and 5V Main oupu volages. The value of he sofsar capaciors can be calculaed from he following expression. Where Tss is he desired sofsar ime. 3V AND 5V ALWAYS 5V MAIN 3V MAIN 0 X X OFF OFF OFF ON OFF OFF ON ON OFF ON OFF ON ON ON ON 5 A Tss Css = 3.5V By varying he values of he sofsar capaciors, i is possible o provide sequencing of he main oupus a sarup. Figure 7 shows he sofsar iniiaed by he SDWNALL pin being pulled high wih he Vba inpu a 10.8V and he resuling 3.3V Main and 5V Main oupus. same value of sofsar capaciors, F, hey boh reach regulaion a he same ime, T3. The sofsar capaciors coninue o charge and are compleely charged a T4. 12V Converer Archiecure The 12V boos converer generaes is oupu volage from he 5V Main oupu. An exernal MOSFET, inducor, diode and capacior are required o complee he circui. The oupu signal is fed back o he conroller via an exernal resisive divider. The boos conroller can be disabled by connecing he VSEN3 pin o 5V ALWAYS. The conrol circui for he 12V converer consiss of a 3:1 frequency divider which drives a ramp generaor and reses a PWM lach as shown in Figure 8. The widh of he CLK/3 pulses is equal o he period of he main clock, limiing he duy cycle o 33%. The oupu of a noninvering error amplifier is compared wih he rising ramp volage. When he ramp volage becomes higher han he error signal, he PWM comparaor ses he lach and he oupu of he gae driver is pulled high providing leading edge, volage mode PWM. The falling edge of he CLK/3 pulses reses he lach and pulls he oupu of he gae driver low. REF CLK VSEN3 DIVIDER 3:1 CLK/3 CLK/3 EA3 RAMP GENERATOR PWM COMPARATOR RAMP PWM LATCH 3 S Q R Q GATE3 V IN = 10.8V CLK SDWNALL,10V/DIV. SDWN2, 2V/DIV. 3.3V OUT, 2V/DIV. CLK/3 RAMP VEA3 0V GATE3 SDWN1, 2V/DIV. FIGURE 8. 12V BOOST OPERATION 0V 5V OUT, 2V/DIV. 4ms/DIV. T0 T1 T2 T3 T4 FIGURE 7. SOFTSTART ON 3.3V AND 5V OUTPUTS While he SDWNALL pin is held low, prior o T0, all oupus are off. Pulling SDWNALL high enables he 3.3V ALWAYS and 5V ALWAYS oupus. Wih he 3.3V Main and 5V Main oupus enabled, a T1, he inernal 5 A curren sources sar charging he sof sar capaciors on he SDWN1 and SDWN2 pins. A T2 he oupus begin o rise and because hey boh have he The 33% maximum duy cycle of he converer guaranees disconinuous inducor curren and uncondiional sabiliy over all operaing condiions. The boos converer wih he limied duy cycle and disconinuous inducor curren can deliver o he load a limied amoun of power before he oupu volage sars o drop. When he duy cycle has reached DMAX, he conrol loop is FN9032 Rev 1.00 Page 9 of 14

10 operaing open circui and he oupu volage varies wih he oupu load resisance, Ro, as given by: Vo= Vin Dmax Ro 2LxF Where Vin is he 5V Main volage, Dmax = 0.33, L is he value of he boos inducor, L3, and F = 100kHz. This provides auomaic oupu curren limiing. When he maximum duy cycle has been reached and for a given inducor, a furher reducion in Ro by onehalf will pull he oupu volage down o of nominal and cause an undervolage condiion. The 12V converer sars o operae a he same ime as he 5V Main converer. The rising volage on he 5V Main oupu and he 33% duy cycle limi provides a similar sofsar, as he 5V Main, for he 12V oupu. 3V ALWAYS, 5V ALWAYS Linear Regulaors The 3.3V ALWAYS and 5V ALWAYS oupus are derived from he baery volage and are he firs volages available in he noebook when power on is iniiaed. The 5V ALWAYS oupu is generaed direcly from he baery volage by a linear regulaor. I is used o power he sysem micro conroller and o inernally power he chip and he gae drivers. The 3.3V ALWAYS oupu is generaed from he 5V ALWAYS oupu and may be used o power he keyboard conroller or oher peripherals. The combined curren capabiliy of hese oupus is 50mA. When he 5V Main oupu is greaer han i s undervolage level, i is swiched o he 5V ALWAYS oupu via an inernal 1.3 MOSFET swich. Simulaneously, he 5V ALWAYS linear regulaor is disabled o preven excessive power dissipaion. The rise ime of he 5V ALWAYS is deermined by he value of he oupu capaciance on he 5V and 3.3V ALWAYS oupus. The inernal regulaor is curren limied o abou 180mA, so he sarup ime is approximaely: 5V = C OUT 180mA Where C OUT is he sum of he capaciances on he 5V and 3.3V ALWAYS oupus. Power Good Saus The IPM6220A moniors all he oupu volages excep for he 3.3V ALWAYS. A single powergood signal, PGOOD, is issued when sofsar is compleed and all moniored oupus are wihin 10% of heir respecive se poins. Afer he sofsar sequence is compleed, undervolage proecion laches he chip off when any of he moniored oupus drop below 75% of is se poin. A sofcrowbar funcion is implemened for an overvolage on he 3.3V Main or 5V Main oupus. If he oupu volage goes above 115% of heir nominal oupu level, he upper MOSFET is urned off and he lower MOSFET is urned on. This sofcrowbar condiion will be mainained unil he oupu volage reurns o he regulaion window and hen normal operaion will coninue. This sofcrowbar and monioring of he oupu, prevens he oupu volage from ringing negaive as he inducor curren flows in he reverse direcion hrough he lower MOSFET and oupu capaciors. OverTemperaure Proecion The IC incorporaes an overemperaure proecion circui ha shus all he oupus down when he die emperaure exceeds 150 C. Normal operaion is auomaically resored when he die emperaure cools o 125 C. Componen Selecion Guidelines Oupu Capacior Selecion The oupu capaciors for each oupu have unique requiremens. In general, he oupu capaciors should be seleced o mee he dynamic regulaion requiremens including ripple volage and load ransiens. 3.3V Main and 5V Main PWM Oupu Capaciors Selecion of he oupu capaciors is also dependen on he oupu inducor so some inducor analysis is required o selec he oupu capaciors. One of he parameers limiing he converer s response o a load ransien is he ime required for he inducor curren o slew o is new level. Given a sufficienly fas conrol loop design, he IPM6220A will provide eiher 0% or 94% duy cycle in response o a load ransien. The response ime is he ime inerval required o slew he inducor curren from an iniial curren value o he load curren level. During his inerval he difference beween he inducor curren and he ransien curren level mus be supplied by he oupu capacior(s). Minimizing he response ime can minimize he oupu capaciance required. Also, if he load ransien rise ime is slower han he inducor response ime, as in a hard drive or CD drive, his reduces he requiremen on he oupu capacior. The maximum capacior value required o provide he full, rising sep, ransien load curren during he response ime of he inducor is: L O I TRAN I C OUT TRAN = V IN V OUT 2 DV OUT Where: C OUT is he oupu capacior(s) required, L O is he oupu inducor, I TRAN is he ransien load curren sep, V IN is he inpu volage, V OUT is oupu volage, and V OUT is he drop in oupu volage allowed during he load ransien. High frequency capaciors iniially supply he ransien curren and slow he load raeofchange seen by he bulk capaciors. The bulk filer capacior values are generally deermined by he ESR (Equivalen Series Resisance) and volage raing requiremens as well as acual capaciance requiremens. The FN9032 Rev 1.00 Page 10 of 14

11 oupu volage ripple is due o he inducor ripple curren and he ESR of he oupu capaciors as defined by: V RIPPLE = IL ESR where, I L is calculaed in he Inducor Selecion secion. High frequency decoupling capaciors should be placed as close o he power pins of he load as physically possible. Be careful no o add inducance in he circui board wiring ha could cancel he usefulness of hese low inducance componens. Consul wih he manufacurer of he load circuiry for specific decoupling requiremens. Use only specialized lowesr capaciors inended for swichingregulaor applicaions, a 300kHz, for he bulk capaciors. In mos cases, muliple elecrolyic capaciors of small case size perform beer han a single large case capacior. The sabiliy requiremen on he selecion of he oupu capacior is ha he ESR zero, f Z, be beween 1.2kHz and 30kHz. This range is se by an inernal, single compensaion zero a 6kHz. The ESR zero can be a facor of five on eiher side of he inernal zero and sill conribue o increased phase margin of he conrol loop. Therefore: 1 C OUT = 2 ESR f Z In conclusion, he oupu capaciors mus mee hree crieria: By varying he values of he sofsar capaciors, i is possible o provide sequencing of he main oupus a sarup. 1. They mus have sufficien bulk capaciance o susain he oupu volage during a load ransien while he oupu inducor curren is slewing o he value of he load ransien 2. The ESR mus be sufficienly low o mee he desired oupu volage ripple due o he oupu inducor curren, and 3. The ESR zero should be placed, in a raher large range, o provide addiional phase margin. 3.3V ALWAYS and 5V ALWAYS Oupu Capaciors The oupu capaciors for he linear regulaors insure sabiliy and provide dynamic load curren. The 3.3V ALWAYS and he 5V ALWAYS linear regulaors should have, as a minimum, 10 F capaciors on heir oupus. 3.3V Main and 5V Main PWM Oupu Inducor Selecion The PWM converers require oupu inducors. The oupu inducor is seleced o mee he oupu volage ripple requiremens. The inducor value deermines he converer s ripple curren and he ripple volage is a funcion of he ripple curren and oupu capacior(s) ESR. The ripple volage expression is given in he capacior selecion secion and he ripple curren is approximaed by he following equaion: V IN V OUT V IL OUT = F S L V IN Inpu Capacior Selecion The imporan parameers for he bulk inpu capacior(s) are he volage raing and he RMS curren raing. For reliable operaion, selec bulk inpu capaciors wih volage and curren raings above he maximum inpu volage and larges RMS curren required by he circui. The capacior volage raing should be a leas 1.25 imes greaer han he maximum inpu volage and 1.5 imes is a conservaive guideline. The AC RMS inpu curren varies wih load as shown in Figure 9. Depending on he specifics of he inpu power and is impedance, mos (or all) of his curren is supplied by he inpu capacior(s). Figure 9 also shows he advanage of having he PWM converers operaing ou of phase. If he converers were operaing inphase, he combined RMS curren would be he algebraic sum, which is a much larger value as shown. The combined ouofphase curren is he square roo of he sum of he square of he individual refleced currens and is significanly less han he combined inphase curren. INPUT RMS CURRENT OUT OF PHASE IN PHASE 3.3V V AND 5V LOAD CURRENT FIGURE 9. INPUT RMS CURRENT vs LOAD Use a mix of inpu bypass capaciors o conrol he volage ripple across he MOSFETs. Use ceramic capaciors for he high frequency decoupling and bulk capaciors o supply he RMS curren. Small ceramic capaciors can be placed very close o he upper MOSFET o suppress he volage induced in he parasiic circui impedances. For board designs ha allow hroughhole componens, he Sanyo OSCON series offer low ESR and good emperaure performance. For surface moun designs, solid analum capaciors can be used, bu cauion mus be exercised wih regard o he capacior surge curren raing. These capaciors mus be capable of handling he surgecurren a powerup. The TPS series available from AVX is surge curren esed. 12V Boos Converer Inducor Selecion The inducor value is chosen o provide he required oupu power o he load. Vinmin Lmax 2 Dmax 2 Ro = 2 Vo 2 F where, Vinmin is he minimum inpu volage, 4.9V; Dmax = 1/3, he maximum duy cycle; Ro is he minimum load resisance; 5V FN9032 Rev 1.00 Page 11 of 14

12 Vo is he nominal oupu volage and F is he swiching frequency, 100kHz. 12V Boos Converer Oupu Capacior Selecion The oal capaciance on he 12V oupu should be chosen appropriaely, so ha he oupu volage will be higher han he undervolage limi (9V) when he 5V Main sofsar ime has elapsed. This will avoid riggering of he 12V undervolage proecion. The maximum value of he boos capacior, Comax ha will charge o 9V in he sofsar ime, Tss, is shown below, where L is he value of he boos inducor. Tss Comax = F L The oupu capacior ESR and he boos inducor ripple curren deermines he oupu volage ripple. The ripple volage is given by: V RIPPLE = I L ESR and he maximum ripple curren, I L, is given by: 5V IL = 3.3 L where L is he boos inducor calculaed above, 5V is he boos inpu volage and 3.3 is he maximum on ime for he boos MOSFET. MOSFET Consideraions The logic level MOSFETs are chosen for opimum efficiency given he poenially wide inpu volage range and oupu power requiremens. Two Nchannel MOSFETs are used in each of he synchronousrecified buck converers for he PWM1 and PWM2 oupus. These MOSFETs should be seleced based upon r DS(ON), gae supply requiremens, and hermal managemen consideraions. The power dissipaion includes wo loss componens; conducion loss and swiching loss. These losses are disribued beween he upper and lower MOSFETs according o duy cycle (see he following equaions). The conducion losses are he main componen of power dissipaion for he lower MOSFETs. Only he upper MOSFET has significan swiching losses, since he lower device urns on and off ino near zero volage. 2 I O r DS ON V OUT I P UPPER O V IN SW F S = V IN 2 2 I O r DS ON V IN V OUT P LOWER = V IN The equaions assume linear volagecurren ransiions and do no model power loss due o he reverserecovery of he lower MOSFET s body diode. The gaecharge losses are dissipaed by he IPM6220A and do no hea he MOSFETs. However, a large gaecharge increases he swiching ime, SW, which increases he upper MOSFET swiching losses. Ensure ha boh MOSFETs are wihin heir maximum juncion emperaure a high ambien emperaure by calculaing he emperaure rise according o package hermalresisance specificaions. Layou Consideraions MOSFETs swich very fas and efficienly. The speed wih which he curren ransiions from one device o anoher causes volage spikes across he inerconnecing impedances and parasiic circui elemens. The volage spikes can degrade efficiency, radiae noise ino he circui, and lead o device overvolage sress. Careful componen layou and prined circui design minimizes he volage spikes in he converer. Consider, as an example, he urnoff ransiion of one of he upper PWM MOSFETs. Prior o urnoff, he upper MOSFET is carrying he full load curren. During he urnoff, curren sops flowing in he upper MOSFET and is picked up by he lower MOSFET. Any inducance in he swiched curren pah generaes a volage spike during he swiching inerval. Careful componen selecion, igh layou of he criical componens, and shor, wide circui races minimize he magniude of volage spikes. See he Applicaion Noe AN9915 for he evaluaion board componen placemen and he prined circui board layou deails. There are wo ses of criical componens in a DCDC converer using an IPM6220A conroller. The swiching power componens are he mos criical because hey swich large amouns of energy, and as such, hey end o generae equally large amouns of noise. The criical small signal componens are hose conneced o sensiive nodes or hose supplying criical bias currens. Power Componens Layou Consideraions The power componens and he conroller IC should be placed firs. Locae he inpu capaciors, especially he highfrequency ceramic decoupling capaciors, close o he power MOSFETs. Locae he oupu inducor and oupu capaciors beween he MOSFETs and he load. Locae he PWM conroller close o he MOSFETs. Insure he curren pahs from he inpu capaciors o he MOSFETs, o he oupu inducors and oupu capaciors are as shor as possible wih maximum allowable race widhs. A mulilayer prined circui board is recommended. Dedicae one solid layer for a ground plane and make all criical componen ground connecions wih vias o his layer. Dedicae anoher solid layer as a power plane and break his plane ino smaller islands of common volage levels. The power plane should suppor he inpu power and oupu power nodes. Use copper filled polygons on he op and boom circui layers for he phase nodes, bu do no unnecessarily oversize hese paricular islands. Since he phase nodes are subjeced o very high dv/d volages, he sray capacior formed beween hese islands and he surrounding circuiry will end o couple swiching noise. Use he remaining prined circui layers for small signal wiring. The wiring races from he conrol IC o he MOSFET gae and source should be sized o carry 2A peak currens. FN9032 Rev 1.00 Page 12 of 14

13 Small Componens Signal Layou Consideraions 4. The VSNS1 and VSNS2 inpus should be bypassed wih a 1.0 F capacior close o heir respecive IC pins. 5. A T filer consising of a spli RSNS and a small, 100pF, capacior as shown in Figure 10, may be helpful in reducing noise coupling ino he ISEN inpu. For example, if he calculaed value of RSNS1 is 2.2k, dividing i as shown wih a 100pF capacior provides filering wihou changing he curren limi se poin. For any calculaed value of RSNS, keep he value of he R9 porion o approximaely 200, and he remainder of he resisance in he R19 posiion. The 200 resisor and 100pF capacior provide effecive filering for noise above 8MHz. This filer configuraion may be helpful on boh he 3.3V and 5V Main oupus. 6. The bypass capaciors for VBATT and he sofsar capaciors, C SS1 and C SS2 should be locaed close o heir connecing pins on he conrol IC. Minimize any leakage curren pahs from SDWN1 and SDWN2 nodes, since he inernal curren source is only 5 A. 7. Refer o he Applicaion Noe AN9915 for a recommended componen placemen and inerconnecions. Figure 11 shows an applicaion circui of a power supply for a noebook PC microprocessor sysem. The power supply provides 5V ALWAYS, 3.3V ALWAYS, 5.0V, 3.3V, and 12V from V DC baery volage. For deailed informaion on he circui, including a Bill of Maerials and circui board descripion, see Applicaion Noe AN9915. Also see Inersil s web sie ( for he laes informaion. RSNS = R19 R9 ISEN1 R19 2K R9 200 C12 100pF FROM PHASE NODE FIGURE 10. NOISE FILTER FOR ISEN1 INPUT 5.622V IN GND C4 C3, 6, F 3x1 F D2 BAT54WT1 VBATT 3.3V ALWAYS (50mA) 5V ALWAYS (50mA) 3.3V (5A) C1 100 F C F L1 8.2 H C F C2 10 F D1 BAT54WT1 Q2 HUF76112SK8 Q4 HUF76112SK8 3.3V ALWAYS 5V ALWAYS BOOT2 UGATE2 PHASE2 R10, 11 ISEN2 2.2K LGATE2 PGND2 VSEN2 SDWN2 C F IPM6220A BOOT1 UGATE1 PHASE1 ISEN1 R9, K LGATE1 PGND1 VSEN1 GATE3 VSEN3 SDWN1 Q3 HUF76112SK8 L2 8.2 H Q5 HUF76112SK8 C F C F L4 2.7 H C36 22 F L3 6.8 H D3 Q5 HUF76112SK8 R K 5V (5A) C21, 32 2x330 F R K 12V (120mA) C24, 33 2x47 F PGOOD SDWNALL GND FIGURE 11. APPLICATIONS CIRCUIT FN9032 Rev 1.00 Page 13 of 14

14 Shrink Small Ouline Plasic Packages (SSOP) Quarer Size Ouline Plasic Packages (QSOP) N INDEX AREA e D B 0.17(0.007) M C A M E B A C SEATING PLANE A B S H 0.25(0.010) M B A1 NOTES: 1. Symbols are defined in he MO Series Symbol Lis in Secion 2.2 of Publicaion Number Dimensioning and olerancing per ANSI Y14.5M Dimension D does no include mold flash, prorusions or gae burrs. Mold flash, prorusion and gae burrs shall no exceed 0.15mm (0.006 inch) per side. 4. Dimension E does no include inerlead flash or prorusions. Inerlead flash and prorusions shall no exceed 0.25mm (0.010 inch) per side. 5. The chamfer on he body is opional. If i is no presen, a visual index feaure mus be locaed wihin he crosshached area. 6. L is he lengh of erminal for soldering o a subsrae. 7. N is he number of erminal posiions. 8. Terminal numbers are shown for reference only. 9. Dimension B does no include dambar prorusion. Allowable dambar prorusion shall be 0.10mm (0.004 inch) oal in excess of B dimension a maximum maerial condiion. 10. Conrolling dimension: INCHES. Convered millimeer dimensions are no necessarily exac. GAUGE PLANE 0.10(0.004) A2 M h x 45 L C M LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150 WIDE BODY) INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e BSC BSC H h L N Rev. 2 6/04 Copyrigh Inersil Americas LLC All Righs Reserved. All rademarks and regisered rademarks are he propery of heir respecive owners. For addiional producs, see Inersil producs are manufacured, assembled and esed uilizing ISO9001 qualiy sysems as noed in he qualiy cerificaions found a Inersil producs are sold by descripion only. Inersil may modify he circui design and/or specificaions of producs a any ime wihou noice, provided ha such modificaion does no, in Inersil's sole judgmen, affec he form, fi or funcion of he produc. Accordingly, he reader is cauioned o verify ha daashees are curren before placing orders. Informaion furnished by Inersil is believed o be accurae and reliable. However, no responsibiliy is assumed by Inersil or is subsidiaries for is use; nor for any infringemens of paens or oher righs of hird paries which may resul from is use. No license is graned by implicaion or oherwise under any paen or paen righs of Inersil or is subsidiaries. For informaion regarding Inersil Corporaion and is producs, see FN9032 Rev 1.00 Page 14 of 14