DATASHEET ISL6224. Features. Applications. Related Literature. Ordering Information. Pinout. Single Output Mobile-Friendly PWM Controller

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1 Single Oupu MobileFriendly PWM Conroller NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT conac our Technical Suppor Cener a 1888INTERSIL or DATASHEET FN904 Rev 8.00 The ISL64 provides power conrol and proecion for a single, adjusable oupu volage required o power chipses and memory banks in highperformance noebooks and PDAs. This oupu volage is adjusable in he range from V. The hysereic or PWM conroller regulaes he oupu volage from baery volages ranging from 4V o 4V. Synchronous recificaion and hysereic operaion a ligh loads conribue o a high efficiency over a wide range of inpu volages and loads. Efficiency is even furher enhanced by using MOSFET s r DS(ON ) as a curren sense componen. Feedforward ramp modulaion, average curren mode conrol and inernal feedback compensaion provide fas and firm handling of ransiens when powering advanced chip ses. Twosage conversion using sysem 5V volage is possible a a higher frequency (600kHz) o minimize he oupu filer size. The ISL64 moniors he oupu volage. A PGOOD (power good) signal is issued when sofsar is compleed and he oupu is wihin ±10% of he se poin. A builin overvolage proecion prevens oupu volage from going above 10% of he se poin. Undervolage proecion laches he chip off when he oupu drops below 70% of is seing value afer sofsar sequence is compleed. The PWM conroller s overcurren circuiry moniors he oupu curren by sensing he volage drop across he lower MOSFET. If higher precision sense echnique is required, an opional exernal currensense resisor may be used. Ordering Informaion PART NUMBER PART MARKING TEMP. ( C) PACKAGE PKG. DWG. # ISL64CA ISL64CA 10 o Ld SSOP M16.15A ISL64CAZ (Noe 1) 64CAZ 10 o Ld SSOP (Pbfree) M16.15A NOTES: 1. Inersil Pbfree plus anneal producs employ special Pbfree maerial ses; molding compounds/die aach maerials and 100% mae in plae erminaion finish, which are RoHS complian and compaible wih boh SnPb and Pbfree soldering operaions. Inersil Pbfree producs are MSL classified a Pbfree peak reflow emperaures ha mee or exceed he Pbfree requiremens of IPC/JEDEC J STD00.. Add T for Tape and Reel. Feaures Adjusable oupu volgage: V High efficiency over wide load range Higher efficiency in hysereic mode a ligh load Lossless curren sense scheme Uses MOSFET s r DS(ON) Opional curren sense mehod higher precision Supply operaion mode Wide V IN range: 4V4V Single 5V sysem rail Inpu undervolage lockou on pin (UVLO) Excellen dynamic response Combined volage feedforward and curren mode conrol Powergood indicaor 300/600kHz swiching frequency Thermal shudown Pbfree plus anneal available (RoHS complian) Applicaions Mobile PCs Graphic cards Handheld porable insrumens Relaed Lieraure Applicaion Noe AN9983 Pinou VIN PGOOD EN OCSET VOUT VSEN SOFT ISL64 (SSOP) TOP VIEW FCCM BOOT UGATE ISEN LGATE P FN904 Rev 8.00 Page 1 of 13

2 Absolue Maximum Raings Bias Volage, V CC V o 7V Inpu Volage, Vin V Phase and Isen Pins V o 9.0V BOOT and Ugae Pins V BOOT wih respec o V All oher pins V o 15V ESD Classificaion Class Thermal Informaion Thermal Resisance (Typical, Noe 1) JA ( C/W) SSOP Package Maximum Juncion Temperaure (Plasic Package) C Maximum Sorage Temperaure Range C o 150 C Maximum Lead Temperaure (Soldering 10s) C (SSOP Lead Tips Only) Recommended Operaing Condiions Bias Volage, V CC V ±5% Inpu Volage, Vin V o 4.0V Ambien Temperaure Range C o 85 C Juncion Temperaure Range C o 15 C CAUTION: Sresses above hose lised in Absolue Maximum Raings may cause permanen damage o he device. This is a sress only raing and operaion of he device a hese or any oher condiions above hose indicaed in he operaional secions of his specificaion is no implied. NOTE: 3. JA is measured wih he componen mouned on a high effecive hermal conduciviy es board in free air. See Tech Brief TB379 for deails. Elecrical Specificaions Operaing Condiions: V CC = 5V, T A = 10 C o 85 C, Unless Oherwise Noed. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SUPPLY Bias Curren I CC LGATE, UGATE Open, VSEN forced above regulaion poin A Shudown Curren I CCSN 5 15 A UVLO Rising Vcc Threshold V Falling Vcc Threshold V Vcc UVLO Hyseris V VIN Inpu Volage Pin Curren (Sink) I VIN VIN pin conneced o he inpu volage source A Inpu Volage Pin Curren (Source) I VIN VIN pin conneced o ground A Shudown Curren I VIN 1 A OSCILLATOR PWM Oscillaor Frequency F c1 V IN = 3.5V 4V khz PWM Oscillaor Frequency F c V IN 0.5V khz Ramp Ampliude, pkpk V R1 V IN = 16V, By Design V Ramp Ampliude, pkpk V R V IN 5V, By Design 1.5 V Ramp Offse V ROFF 0.5 V REFERENCE AND SOFTSTART Inernal Reference Volage V REF 0.9 V Reference Volage Accuracy % SofSar Curren During Sarup I SOFT 5 A SofSar Threshold V SOFT 1.5 V PWM CONVERTER Load Regulaion 0.0mA < I VOUT1 < 3.0A; 5.0V < V IN < 4.0V % VSEN pin bias curren I VSEN 80 na FN904 Rev 8.00 Page of 13

3 Elecrical Specificaions Operaing Condiions: V CC = 5V, T A = 10 C o 85 C, Unless Oherwise Noed. (Coninued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VOUT pin inpu impedance I VOUT k Undervolage Shudown Level V UV1 Fracion of he se poin; ~3 s noise filer % Overvolage Proecion V OVP1 Fracion of he se poin; ~1 s noise filer % PWM CONTROLLER GATE DRIVERS Upper Drive PullUp Resisance R UGPUP 8 15 Upper Drive PullDown Resisance R UGPDN 3. 5 Lower Drive PullUp Resisance R LGPUP 8 15 Lower Drive PullDown Resisance R LGPDN POWER GOOD AND CONTROL FUNCTIONS PowerGood Lower Threshold V PG Fracion of he se poin; ~3 s noise filer 14 8 % PowerGood Higher Threshold V PG Fracion of he se poin; ~3 s noise filer % PGOOD Leakage Curren I PGLKG V PULLUP = 5.5V 1 A PGOOD Volage Low I PGOOD = 4mA 0.5 V EN Low (Off) 0.8 V EN High (On).0 V FCCM Hysereic Operaion Enabled Vcc/ V FN904 Rev 8.00 Page 3 of 13

4 FN904 Rev 8.00 Page 4 of 13 Funcional Block Diagram VIN FSET EN SOFT PGOOD POR CLK CLK REFERENCE AND SOFTSTART OUTPUT VOLTAGE MONITOR RAMP SDWN REF POWERON RESET (POR) POR PWM LATCH 1 Q D R Q < FCCM OC LOGIC1 VOLT SECOND CLAMP SHUTOFF GATE LOGIC DEADT PWM/HYST PWM ON HYST ON PWM/HYS LOGIC V OUT HI LO OC COMP1 EA1 FFBK LGATE1 HGDR1 GATE CONTROL LGDR OVP HYST COMP1 REF CLK1 FCCM BOOT UGATE LGATE P VSEN MODE CHANGE COMP LGATE R1=0K ISEN OCSET ISL64

5 Funcional Pin Descripion VIN (Pin 1) Provides baery volage o he oscillaor for feedforward rejecion of he inpu volage variaion. Also, his pin programs frequency of he inernal clock and gain of he ramp generaor. When conneced o he baery, which volage varies from 4V o 4V, he clock frequency is se o 300kHz and he ramp gain is se accordingly o accommodae he wide inpu volage range. For wo sep conversion from he sysem 5V power rail, he Vin pin is conneced o ground via a 150k resisor. This arrangemen changes he gain of he ramp generaor o accommodae he lower inpu volage bu does no change he clock frequency. When he Vin pin is conneced o ground, he clock frequency is se o 600kHz. The ramp generaor gain is also changed accordingly. This circui arrangemen enables he designer o choose smaller oupu filer componens. PGOOD (Pin ) PGOOD is an open collecor oupu used o indicae he saus of he oupu volage. This pin is pulled high when he sysem oupu is wihin 10% of is respecive nominal volage. EN (Pin 3) This pin provides he enable/disable funcion for he chip. The IC is enabled when his pin is pulled over V or lef open. Noe: a pulldown resisance of 100k or less is required o disable he conroller. OCSET (Pin 4) A resisor from his pin o ses he overcurren proecion hreshold. VOUT (Pin 5) This pin is used for feedback of he oupu volage o properly posiion oupu volage during operaional mode change. VSEN (Pin 6) This pin is conneced o he oupu via a resisive divider and provides he volage feedback signal for he PWM conroller. The PGOOD, UVP, and OVP circuis use his signal o repor oupu volage saus. SOFT (Pin 7) This pin provides sofsar of he PWM conroller. When he EN pin is pulled high, he volage on he capacior conneced o he sofsar pin is rising linearly due o he 5 A pullup curren. The oupu volage follows he volage on he capacior unil i reaches he value of 0.9V. The furher rise of he volage on he sofsar capacior does no affec he oupu volage. (Pin 8) Signal ground for he IC. P (Pin 9) This is he power ground connecion for PWM converer. This pin is conneced o he lower MOSFET s source erminal. LGATE (Pin 10) This pin provides he gae drive for he lower MOSFET. (Pin 11) This pin provides power o he chip. ISEN (Pin 1) This pin is used o monior he volage drop across he lower MOSFET for curren feedback and overcurren proecion. For precise curren deecion his inpu can be conneced o an opional curren sense resisor placed in series wih he source of he lower MOSFET. (Pin 13) Connec his pin o he node of he converer. The node is he juncion poin of he upper MOSFET source, oupu filer inducor, and lower MOSFET drain. UGATE (Pin 14) This pin provides he gae drive for he upper MOSFET. BOOT (Pin 15) This pin powers he upper MOSFET drivers of he PWM converer. Connec his pin o he juncion of boosrap capacior wih he cahode of he boosrap diode. Anode of he boosrap diode is conneced o he pin. FCCM (Pin 16) This pin, when pulled o, resrains hysereic operaion in ligh loads. General Descripion Operaional Overview The ISL64 is a singlechannel PWM conroller inended for chipse, DRAM, or oher low volage power needs of modern noebook and subnoebook PCs. The IC inegraes conrol circuis and feedback compensaion for a single synchronous buck converer. The oupu volage is se in he range of V by an exernal resisive divider. The synchronous buck converer can be configured for eiher 300kHz or 600kHz swiching frequencies. When operaed from baery, a swiching frequency of 300kHz is recommended. When operaing from 5V, swiching frequencies of 300kHz or 600kHz are an opion. For 300kHz operaion, pin 1 should be conneced hrough a resisor (150K) o gnd. For 600kHz operaion, pin 1 should simply be FN904 Rev 8.00 Page 5 of 13

6 grounded. Table 1. shows he configuraion for differen modes of operaion. Figure 1 below shows plos of he ramp speed compensaion. 300kHz CLOCK 600kHz CLOCK Vo/4 Vin T Vo/8 Vin 4 T Vin 8 T FIGURE 1. RAMP SPEED COMPENSATION Vo =.5V TABLE 1. CONFIGURATION FOR MODES OF OPERATION OPERATION PIN 1 CONNECTION PIN 1 POTENTIAL Onesage 300kHz Vin V1 > 4V Twosage 300kHz 150K 1V < V1 < V Twosage 600kHz V1 < 0.5V The synchronous converer lighload efficiency is enhanced by a hysereic mode of operaion which is auomaically engaged a ligh loads when he inducor curren becomes disconinuous. As he filer inducor resumes coninuous curren, he PWM mode of operaion is auomaically resored. The ISL64 conrol IC employs an average curren mode conrol scheme wih inpu volage feedforward ramp programming for beer rejecion of inpu volage variaions. Curren Sensing and Curren Limi Proecion The PWM converer uses he lower MOSFET onsae resisance, r DS(ON), as he currensensing elemen. This echnique eliminaes he need for a curren sense resisor and he associaed power losses. If more accurae curren proecion is desired, curren sense resisors may be used in series wih he lower MOSFET s source. A curren proporional signal is used o provide average curren mode conrol and overcurren proecion. The gain in he curren sense circui is se by he resisor conneced from ISEN (pin 1) o he node of he buck converer. The value of his resisor can be esimaed by he following expression: of his resisor can be obained from he following expression: 11 Risen Rocse = Ioc Rdson where Ioc is he value of overcurren. The resuling curren ou of he ISEN pin hrough R ISEN, is used for curren feedback and curren limi proecion. This is compared wih an inernal curren limi hreshold. When a sampled value of he oupu curren is deermined o be above he curren limi hreshold, he PWM drive is erminaed and a couner is iniiaed. This limis he inducor curren buildup and essenially swiches he converer ino currenlimi mode. If an overcurren is deeced beween 6ms o 53ms laer, an overcurren shudown is iniiaed. If during he 6ms o 53ms period, an overcurren is no deeced, he couner is rese and sampling coninues as normal. This curren limi scheme has proven o be very robus in applicaions like porable compuers where fas inducor curren buildup is common due o a large difference beween inpu and oupu volages and a low value of he inducor. LighLoad (Hysereic) Operaion In he lighload (hysereic) mode he oupu volage is regulaed by he hysereic comparaor which regulaes he oupu volage by mainaining he oupu volage ripple as shown in Figure. In hysereic mode, he inducor curren flows only when he oupu volage reaches he lower limi of he hysereic comparaor and urns off a he upper limi. Hysereic mode saves converer energy a ligh loads by supplying energy only a he ime when he oupu volage requires i. This mode conserves energy by reducing he power dissipaion associaed wih coninuous swiching. During he ime beween inducor curren pulses, boh he upper and lower MOSFETs are urned off. This is referred o as diode emulaion mode because he lower MOSFET performs he funcion of a diode. This diode emulaion mode prevens he oupu capacior from discharging hrough he lower MOSFET when he upper MOSFET is no conducing. NOTE: he PWM only operaion can inenionally be forced by ying pin 16, FCCM, o. Risen = Iomax Rdson A where Iomax is he maximum inducor curren. The value of R ISEN should be specified for he expeced maximum operaing emperaure. An overcurren proecion hreshold is se by an exernal resisor conneced from OCSET (pin 4) o ground. The value FN904 Rev 8.00 Page 6 of 13

7 VOUT I L due o he volage drop on he oupu capacior ESR. If he decrease causes he oupu volage o drop below he hysereic regulaion level, he mode is changed o PWM on he nex clock cycle. This insures he full power required by he increase in oupu curren. COMP MODE OF OPERATION PWM HYSTERETIC I L FIGURE. HYSTERETIC OPERATION MODE OperaionMode Conrol The modeconrol circui changes he converer s mode of operaion based on he volage polariy of he phase node when he lower MOSFET is conducing and jus before he upper MOSFET urns on. For coninuous inducor curren, he phase node is negaive when he lower MOSFET is conducing and he converers operae in fixedfrequency PWM mode as shown in Figure 3. When he load curren decreases o he poin where he inducor curren flows hrough he lower MOSFET in he reverse direcion, he phase node becomes posiive, and he mode is changed o hysereic. A phase comparaor handles he iming of he phase node volage sensing. A low level on he phase comparaor oupu indicaes a negaive phase volage during he conducion ime of he lower MOSFET. A high level on he phase comparaor oupu indicaes a posiive phase volage. When he phase node is posiive (phase comparaor high), a he end of he lower MOSFET conducion ime, for eigh consecuive clock cycles, he mode is changed o hysereic as shown in Figure 3. The dashed lines indicae when he phase node goes posiive and he phase comparaor oupu goes high. The solid verical lines a 1,,...8 indicae he sampling ime, of he phase comparaor, o deermine he polariy (sign) of he phase node. A he ransiion beween PWM and hysereic mode boh he upper and lower MOSFETs are urned off. The phase node will ring based on he oupu inducor and he parasiic capaciance on he phase node and sele ou a he value of he oupu volage. NODE COMP MODE OF OPERATION Gae Conrol Logic PWM FIGURE 3. MODE CONTROL WAVEFORMS HYSTERETIC The gae conrol logic ranslaes generaed PWM conrol signals ino he MOSFET gae drive signals providing necessary amplificaion, level shifing and shoohrough proecion. Also, i has funcions ha help opimize he IC performance over a wide range of operaional condiions. Since MOSFET swiching ime can vary dramaically from ype o ype and wih he inpu volage, he gae conrol logic provides adapive dead ime by monioring he gaeosource volages of boh upper and lower MOSFETs. The lower MOSFET is no urned on unil he gaeosource volage of he upper MOSFET has decreased o less han approximaely 1V. Similarly, he upper MOSFET is no urned on unil he gaeosource volage of he lower MOSFET has decreased o less han approximaely 1V. This allows a wide variey of upper and lower MOSFETs o be used wihou a concern for simulaneous conducion, or shoohrough. The mode change from hysereic o PWM can be caused by one of wo evens. One even is he same mechanism ha causes a PWM o hysereic ransiion. Bu insead of looking for eigh consecuive posiive occurrences on he phase node, i is looking for eigh consecuive negaive occurrences on he phase node. The operaion mode will be changed from hysereic o PWM when hese eigh consecuive pulses occur. This ransiion echnique prevens jier of he operaion mode a load levels close o boundary. The oher mechanism for changing from hysereic o PWM is due o a sudden increase in he oupu curren. This sep load causes an insananeous decrease in he oupu volage FN904 Rev 8.00 Page 7 of 13

8 SofSar Operaion Sofsar of he Synchronous Buck Converer is accomplished by means of a capacior conneced from pin 7, SOFT o ground. The sofsar ime can be obained from he following equaion: 1.5V Css Tss = 5.0 A Figure 4 shows he sofsar iniiaed by he ENABLE pin being pulled high wih he VIN inpu a 5.6V and he resuling 3.3V oupu and PGOOD signal. While he ENABLE pin is held low, prior o 0, he oupu is off. When he EN pin is pulled high, a 0, he volage on he capacior conneced o he sofsar pin rises linearly due o he inernal 5 A curren source sars charging he capacior. The oupu volage follows he volage on he capacior ill i reaches he value of 0.9V a 1. A his momen, 1, he oupu volage sared regulaion. The sofsar is complee when PGOOD pin is high a and furher rise of he volage on he sofsar capacior does no affec he oupu volage. This sofcrowbar and monioring of he oupu, prevens he oupu volage from ringing negaive as he inducor curren flows in he reverse direcion hrough he lower MOSFET and oupu capaciors. Componen Selecion Guidelines Oupu Capacior Selecion The oupu capaciors have unique requiremens. In general, he oupu capaciors should be seleced o mee he dynamic regulaion requiremens including ripple volage and load ransiens. Selecion of he oupu capaciors is also dependen on he oupu inducor so some inducor analysis is required o selec he oupu capaciors. One of he parameers limiing he converer s response o a load ransien is he ime required for he inducor curren o slew o is new level. Given a sufficienly fas conrol loop design, he ISL64 will provide eiher 0% or 94% duy cycle in response o a load ransien. The response ime is he ime inerval required o slew he inducor curren from an iniial curren value o he load curren level. During his inerval he difference beween he inducor curren and he ransien curren level mus be supplied by he oupu capacior(s). Minimizing he response ime can minimize he oupu capaciance required. If he load ransien rise ime is slower han he inducor response ime, as in a hard drive or CD drive, his reduces he requiremen on he oupu capacior. The maximum capacior value required o provide he full, rising sep, ransien load curren during he response ime of he inducor is: L O I TRAN I C OUT TRAN = V IN V OUT DV OUT 0 1 FIGURE 4. MODE CONTROL WAVEFORMS Power Good Saus The ISL64 moniors he oupu volage. A single powergood signal, PGOOD, is issued when sofsar is compleed and he oupu is wihin 10% of i s se poin. Afer he sofsar sequence is compleed, undervolage proecion laches he chip off when any of he moniored oupus drop below 70% of is se poin. A sofcrowbar funcion is implemened for an overvolage on he oupu. If he oupu volage goes above 10% of is nominal oupu level, he upper MOSFET is urned off and he lower MOSFET is urned on. This sofcrowbar condiion will be mainained unil he oupu volage reurns o he regulaion window and hen normal operaion will coninue. Where: C OUT is he oupu capacior(s) required, L O is he oupu inducor, I TRAN is he ransien load curren sep, V IN is he inpu volage, V OUT is oupu volage, and DV OUT is he drop in oupu volage allowed during he load ransien. High frequency capaciors iniially supply he ransien curren and slow he load raeofchange seen by he bulk capaciors. The bulk filer capacior values are generally deermined by he ESR (equivalen series resisance) and volage raing requiremens as well as acual capaciance requiremens. The oupu volage ripple is due o he inducor ripple curren and he ESR of he oupu capaciors as defined by: V RIPPLE = IL ESR where, I L is calculaed in he Inducor Selecion secion. High frequency decoupling capaciors should be placed as close o he power pins of he load as physically possible. Be careful no o add inducance in he circui board wiring ha FN904 Rev 8.00 Page 8 of 13

9 could cancel he usefulness of hese low inducance componens. Consul wih he manufacurer of he load circuiry for specific decoupling requiremens. Use only specialized lowesr capaciors inended for swichingregulaor applicaions, a 300kHz, for he bulk capaciors. In mos cases, muliple elecrolyic capaciors of small case size perform beer han a single large case capacior. The sabiliy requiremen on he selecion of he oupu capacior is ha he ESR zero, f Z, be beween 1.kHz and 30kHz. This range is se by an inernal, single compensaion zero a 6kHz. The ESR zero can be a facor of five on eiher side of he inernal zero and sill conribue o increased phase margin of he conrol loop. Therefore: 1 C OUT = ESR f Z In conclusion, he oupu capaciors mus mee hree crieria: 1. They mus have sufficien bulk capaciance o susain he oupu volage during a load ransien while he oupu inducor curren is slewing o he value of he load ransien. The ESR mus be sufficienly low o mee he desired oupu volage ripple due o he oupu inducor curren, and 3. The ESR zero should be placed, in a raher large range, o provide addiional phase margin. Oupu Inducor Selecion The oupu inducor is seleced o mee he oupu volage ripple requiremens. The inducor value deermines he converer s ripple curren and he ripple volage is a funcion of he ripple curren and oupu capacior(s) ESR. The ripple volage expression is given in he capacior selecion secion and he ripple curren is approximaed by he following equaion: V IN V OUT V IL OUT = F S L V IN where F s is he swiching frequency. Inpu Capacior Selecion The imporan parameers for he bulk inpu capacior(s) are he volage raing and he RMS curren raing. For reliable operaion, selec bulk inpu capaciors wih volage and curren raings above he maximum inpu volage and larges RMS curren required by he circui. The capacior volage raing should be a leas 1.5 imes greaer han he maximum inpu volage and 1.5 imes is a conservaive guideline. close o he upper MOSFET o suppress he volage induced in he parasiic circui impedances. For board designs ha allow hroughhole componens, he Sanyo OSCON series offer low ESR and good emperaure performance. For surface moun designs, solid analum capaciors can be used, bu cauion mus be exercised wih regard o he capacior surge curren raing. These capaciors mus be capable of handling he surgecurren a powerup. The TPS series available from AVX is surge curren esed. MOSFET Consideraions The logic level MOSFETs are chosen for opimum efficiency given he poenially wide inpu volage range and oupu power requiremens. One dual NChannel or wo NChannel MOSFETs are used in each of he synchronous recified buck converers for he oupus. These MOSFETs should be seleced based upon r DS(ON), gae supply requiremens, and hermal managemen consideraions. The power dissipaion includes wo loss componens; conducion loss and swiching loss. These losses are disribued beween he upper and lower MOSFETs according o duy cycle (see he following equaions). The conducion losses are he main componen of power dissipaion for he lower MOSFETs. Only he upper MOSFET has significan swiching losses, since he lower device urns on and off ino nearzero volage. I O r DS ON V OUT I P UPPER O V IN SW F S = V IN I O r DS ON V IN V OUT P LOWER = V IN The equaions assume linear volagecurren ransiions and do no model power loss due o he reverserecovery of he lower MOSFET s body diode. The gaecharge losses are dissipaed by he ISL64 and do no hea he MOSFETs. However, a large gaecharge increases he swiching ime, SW which increases he upper MOSFET swiching losses. Ensure ha boh MOSFETs are wihin heir maximum juncion emperaure a high ambien emperaure by calculaing he emperaure rise according o package hermalresisance specificaions. The AC RMS inpu curren varies wih load. Depending on he specifics of he inpu power and i s impedance, mos (or all) of his curren is supplied by he inpu capacior(s). Use a mix of inpu bypass capaciors o conrol he volage ripple across he MOSFETs. Use ceramic capaciors for he high frequency decoupling and bulk capaciors o supply he RMS curren. Small ceramic capaciors can be placed very FN904 Rev 8.00 Page 9 of 13

10 Layou Consideraions MOSFETs swich very fas and efficienly. The speed wih which he curren ransiions from one device o anoher causes volage spikes across he inerconnecing impedances and parasiic circui elemens. The volage spikes can degrade efficiency, radiae noise ino he circui, and lead o device overvolage sress. Careful componen layou and prined circui design minimizes he volage spikes in he converer. Consider, as an example, he urnoff ransiion of one of he upper PWM MOSFETs. Prior o urnoff, he upper MOSFET is carrying he full load curren. During he urnoff, curren sops flowing in he upper MOSFET and is picked up by he lower MOSFET. Any inducance in he swiched curren pah generaes a volage spike during he swiching inerval. Careful componen selecion, igh layou of he criical componens, and shor, wide circui races minimize he magniude of volage spikes. See he Applicaion Noe AN9983 for he evaluaion board componen placemen and he prined circui board layou deails. There are wo ses of criical componens in a DC/DC converer using an ISL64 conroller. The swiching power componens are he mos criical because hey swich large amouns of energy, and as such, hey end o generae equally large amouns of noise. The criical small signal componens are hose conneced o sensiive nodes or hose supplying criical bias currens. Power Componens Layou Consideraions The power componens and he conroller IC should be placed firs. Locae he inpu capaciors, especially he highfrequency ceramic decoupling capaciors, close o he power MOSFETs. Locae he oupu inducor and oupu capaciors beween he MOSFETs and he load. Locae he PWM conroller close o he MOSFETs. A mulilayer prined circui board is recommended. Dedicae one solid layer for a ground plane and make all criical componen ground connecions wih vias o his layer. Dedicae anoher solid layer as a power plane and break his plane ino smaller islands of common volage levels. The power plane should suppor he inpu power and oupu power nodes. Use copper filled polygons on he op and boom circui layers for he phase nodes, bu do no unnecessarily oversize hese paricular islands. Since he phase nodes are subjeced o very high dv/d volages, he sray capacior formed beween hese islands and he surrounding circuiry will end o couple swiching noise. Use he remaining prined circui layers for small signal wiring. The wiring races from he conrol IC o he MOSFET gae and source should be sized o carry A peak currens. Small Componens Signal Layou Consideraions The Vin pin 1 inpu should be bypassed wih a 1.0µF capacior. The bypass capaciors for Vin and he sofsar capacior, should be locaed close o heir connecing pins on he conrol IC. Refer o he Applicaion Noe AN9983 for a recommended componen placemen and inerconnecions. Figures 5, 6 and 7 show applicaion circuis for he hree modes of operaion. Mode 1 is operaing from baery volage and operaing a 300kHz swiching frequency. Mode is operaing off of 5V and operaing a 300kHz swiching frequency. Mode 3 is operaing off of 5V and operaing a 600kHz swiching frequency. Insure he curren pahs from he inpu capaciors o he MOSFETs, o he oupu inducors and oupu capaciors are as shor as possible wih maximum allowable race widhs. FN904 Rev 8.00 Page 10 of 13

11 ISL64 DCDC Converer Applicaion Circuis Figure 5 shows an applicaion circui of a DC/DC converer for a noebook PC. The power supply provides V_5S from eiher 4V 4V DC baery volage or sysem 5V bus. For deailed informaion on he circui, including a bill of maerials and circui board descripion, see Applicaion Noe AN9983. Also see Inersil s web sie (hp:// for he laes informaion. C 1µF C1 56µF 5.64V IN 5.0V CC R OCSET 4 VIN 1 11 CR1 C3 33µF C µF TBD FCCM EN SOFT PGOOD ISL BOOT UGATE ISEN Risen TBD LGATE P VSEN VOUT Q1 1/ FDS691A C6 0.1µF L1 6.4µH C5 330µF Q / FDS691A R3 R4 V_5S (3A) C6 FIGURE 5. APPLICATION CIRCUIT FOR ONESTEP CONVERSION (MODE 1) FN904 Rev 8.00 Page 11 of 13

12 5.0V CC C 0.015µF R OCSET TBD FCCM EN SOFT ISL CR1 BOOT UGATE ISEN Risen TBD LGATE P Q1 1/ FDS691A C4 0.1µF L1 6.4µH C1 33µF C5 Q 330µF / FDS691A R3 V_5S (A) C6 PGOOD VSEN VOUT R4 VIN R5 FIGURE 6. APPLICATION CIRCUIT FOR TWOSTEP 300kHz CONVERSION (MODE ) 5.0V CC C 0.015µF R OCSET TBD FCCM EN SOFT ISL CR1 BOOT UGATE ISEN Risen TBD LGATE P Q1 1/ FDS691A C4 0.1µF L1 6.4µH C1 33µF C5 Q 330µF / FDS691A R3 V_5S (A) C6 PGOOD VSEN VOUT R4 VIN FIGURE 7. APPLICATION CIRCUIT FOR TWOSTEP 600kHz CONVERSION (MODE 3) FN904 Rev 8.00 Page 1 of 13

13 Shrink Small Ouline Plasic Packages (SSOP) Quarer Size Ouline Plasic Packages (QSOP) N INDEX AREA 1 3 e D B 0.17(0.007) M C A M E B A C SEATING PLANE A B S H 0.5(0.010) M B A1 NOTES: 1. Symbols are defined in he MO Series Symbol Lis in Secion. of Publicaion Number 95.. Dimensioning and olerancing per ANSI Y14.5M Dimension D does no include mold flash, prorusions or gae burrs. Mold flash, prorusion and gae burrs shall no exceed 0.15mm (0.006 inch) per side. 4. Dimension E does no include inerlead flash or prorusions. Inerlead flash and prorusions shall no exceed 0.5mm (0.010 inch) per side. 5. The chamfer on he body is opional. If i is no presen, a visual index feaure mus be locaed wihin he crosshached area. 6. L is he lengh of erminal for soldering o a subsrae. 7. N is he number of erminal posiions. 8. Terminal numbers are shown for reference only. 9. Dimension B does no include dambar prorusion. Allowable dambar prorusion shall be 0.10mm (0.004 inch) oal in excess of B dimension a maximum maerial condiion. 10. Conrolling dimension: INCHES. Convered millimeer dimensions are no necessarily exac. GAUGE PLANE 0.10(0.004) A M h x 45 L C M16.15A 16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150 WIDE BODY) INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.05 BSC BSC H h L N Rev. 6/04 Copyrigh Inersil Americas LLC All Righs Reserved. All rademarks and regisered rademarks are he propery of heir respecive owners. For addiional producs, see Inersil producs are manufacured, assembled and esed uilizing ISO9001 qualiy sysems as noed in he qualiy cerificaions found a Inersil producs are sold by descripion only. Inersil may modify he circui design and/or specificaions of producs a any ime wihou noice, provided ha such modificaion does no, in Inersil's sole judgmen, affec he form, fi or funcion of he produc. Accordingly, he reader is cauioned o verify ha daashees are curren before placing orders. Informaion furnished by Inersil is believed o be accurae and reliable. However, no responsibiliy is assumed by Inersil or is subsidiaries for is use; nor for any infringemens of paens or oher righs of hird paries which may resul from is use. No license is graned by implicaion or oherwise under any paen or paen righs of Inersil or is subsidiaries. For informaion regarding Inersil Corporaion and is producs, see FN904 Rev 8.00 Page 13 of 13