High Temperature (>200 C) Isolated Gate Drive Topologies for Silicon Carbide (SiC) JFET

Transcription

1 High Temperaure (>200 C) Isolaed Gae Drive Topologies for Silicon Carbide (SiC) JFET S. Waffler, S.D. Round and J.W. Kolar Power Elecronic Sysems Laboraory ETH Zurich 8092 Zurich, Swizerland Absrac Volume and weigh limiaions for componens in hybrid elecrical vehicle (HEV) propulsion sysems demand highlycompac and highly-efficien power elecronics. The applicaion of Silicon Carbide (SiC) semiconducor echnology in conjuncion wih high emperaure (HT) operaion allows he power densiy of he DC-DC converers and inverers o be increased. Elevaed ambien emperaures of above 200 C also affecs he gae drives aached o he power semiconducors. This paper focuses on he selecion of HT componens and discusses differen gae drive opologies for SiC JFETs wih respec o HT operaion capabiliy, limiaions, dynamic performance and circui complexiy. An experimenal performance comparison of edge-riggered and phase-difference HT drivers wih a convenional room emperaure JFET gae driver is given. The proposed edge-riggered gae driver offers high swiching speeds and a cos effecive implemenaion. Swiching ess a 200 C approve an excellen performance a high emperaure and a low emperaure drif of he driver oupu volage. I. INTRODUCTION High emperaures in he propulsion sysem of Hybrid Elecrical Vehicles (HEV) provide a harsh environmen for power elecronic sysems such as DC-DC converers and inverers. The same environmenal condiions also apply for miliary, space exploraion or energy exploraion applicaions [1] and demand High Temperaure (HT) capable elecronics. Silicon Carbide (SiC) semiconducors are especially valuable in hese fields of applicaion due o he SiC maerial properies. In comparison o silicon, SiC has a larger band gap and hus allows higher juncion emperaure operaion, which minimizes hea sink volume or provides he possibiliy o inegrae he power elecronics wih he engine and he engine coolan of a HEV [2]. The higher sauraed elecron drif speed increases swiching speed [1] and hus allows a reducion of he size and weigh of he converer s passive componens. The only available SiC swich is he normally-on JFET ha offers larger forward curren raings and lower on resisance [3], whereas normally-off devices like SiC-BJT, SiC- MOSFETs and IGBTs are being researched by semiconducor manufacurers for fuure applicaion. Since i is necessary o place he gae drive physically close o a SiC-JFET, operaion a elevaed ambien emperaure of above 200 C is required and a swiching frequency of approximaely 250kHz is desired o benefi from he SiC dynamic properies. Furhermore, for a DC-DC converer applicaion a large duy range is essenial and he capabiliy o saically urn off he normally-on device is required for proecion reasons. A ypical JFET gae drive circui for room emperaure operaion ha provides hese requiremens is shown in Fig. 1. A digial isolaor IC1 is applied o elecrically isolae he PWM signal from he high volage and feeds a subsequen inegraed driver circui IC2 ha generaes he JFET gae volage. IC1 and IC2 are conneced o a ransformer-isolaed auxiliary power supply. Circui exensions can provide beer swiching performance [4] or proecion funcionaliy [5]. The opical or inegraed magneic couplers ha are ypically uilized for IC1 as well as he inegraed circui IC2 are no operable a high emperaure because of aging effecs and/or oher maerial limiaions like maximum juncion emperaure. Only a small number of componens fulfills he requiremens for operaing emperaure range. Therefore, high emperaure operaion of gae drivers ha also have high performance poses a significan challenge in boh componen and opology selecion. Secion II of his paper deals wih maerials and componens for HT operaion. Differen drive opologies ha uilize his componen porfolio are evaluaed in Secion III. Comparaive experimenal resuls for he seleced drive opologies are presened in Secion IV. A. Passive componens II. COMPONENT SELECTION HT resisors are sandard componens wih he maximum allowable power dissipaion as he limiing facor. Since power dissipaion decreases wih emperaure, resisors wih higher power raing mus be chosen. The influence of he emperaure coefficien (TC) is considerably low for a gae drive applicaion. IC1 Isolaion -U drv C b IC2 -U drv Fig. 1. Typical gae driver design using an isolaed power supply, a digial isolaor IC1 and an inegraed driving circui IC2. R g

2 This is differen for capaciors where he emperaure characerisics of ceramic dielecrics like X7R or Y5U are very unsable [6] and induce a capaciance drop of 50% or more a he desired emperaure. The seleced HT SMT capaciors by Advanced Monolihic Capaciors (AMC) wih emperaure sable NPO dielecric are raed for 200 C. Furhermore, suiable magneic maerials are required for he isolaing ransformers. The maximum operaion emperaure for coaed powder, ferrie or srip-wound cores is in he range of C [7] because of he epoxy coaing. Tha is why uncoaed oroidal ferrie cores wih high Curie emperaure T c are preferred. The ransformers used for he gae drivers are consruced from Magenics L maerial [8] cores, which have a T c > 300 C and relaively good magneic and core loss characerisics, and he windings are made wih Polyamidimid coaed grade 2 magne wire. An alernaive is o avoid magneic maerials by he applicaion of coreless ransformers. B. Acive componens Increasing subsrae leakage currens limi he maximum allowable juncion emperaure for silicon inegraed circuis. Alernaives for HT acive componens are SiC or Silicon On Insulaor (SOI) echnology ha provide significan reliabiliy and performance advanages. There is a wide variey of SiC diodes, also for low power applicaions like a HT gae drive bu on he conrary, no discree small signal ransisors or inegraed circuis. However, a very resriced assormen of SOI producs is available. This includes operaional amplifiers, gae logic and discree componens. A promising par for he HT gae driver is a 1A SOI MOSFET by Honeywell (HTNFET). C. Mechanical From a mechanical poin of view, here are wo major concerns. These are he HT subsrae and he packaging of he acive componens. Firsly, epoxy resins are characerized by heir glass ransiion emperaure T g above which he maerial becomes sof. This is one of he reasons why ceramic subsraes like Al 2 O 3 or AlN are preferred o sandard FR-4 (T g 130 C) or High- Tg FR-4 (T g 170 C). A furher reliabiliy-relaed maerial propery is he coefficien of hermal expansion (CTE). The CTE of he base maerial should be similar o ha of he conducor maerial oherwise unequal expansion of subsrae and conducor will crack racks or vias. The FR-4 maerials show a large CTE in z-direcion and can no be used. However, here are special laminaes like Arlon 85N, Isola IS410 or Rogers RO4530B ha can be handled wih a cossaving sandard PCB process and provide high T g and low CTE a he same ime such as T g > 280 C and CTE(z) = 35ppm/ C for he seleced RO4530B subsrae. Secondly, as convenional epoxy packages do no wihsand he emperaure, usually a Muli-Chip Power Module (MCPM) is he packaging echnique of choice. As a maer of coss and handling, HT MOSFETs in a HT ceramic package and SiC componens in sandard packages are o be placed on RO4530B subsrae in a firs sep. III. TOPOLOGY EVALUATION For a cos-opimized gae driver design he number of HT componens, especially of non-sandard acive componens like MOSFETs needs o be minimized. Purely passive drives, simple acive drives and more advanced acive drives are evaluaed in respec o heir suiabiliy for applicaion o SiC JFETs employed in DC-DC converers. A. Transformer Coupled Gae Drive Circuis A simple gae driver wih an isolaion ransformer bu wihou acive componens is depiced in Fig. 2 (a). Since he vol seconds produc of posiive and negaive half-wave of he ransformer secondary volage are forced o be equal, he circui oupu is bipolar. The bipolar signal is he cause of wo problems, firsly, a low duy cycles he ampliude of he negaive half-wave drops and will urn on he JFET when exceeds he hreshold volage U h. Secondly, he posiive JFET gae volage should be kep below he hreshold of he gae juncion o avoid is desrucion when no furher curren limiaion is provided. An addiional capacior C c and a diode D c exends he circui o he DC Resore Circui (Fig. 2 (b)) wih oupu volage eiher or u p,pk pk for a urns raio of 1:1. A consan volage a he ransformer primary sauraes he core. To preven sauraion, a PWM signal u p () mus be applied. Unforunaely, his fac disqualifies boh circuis since he normally-on JFET canno be urned off permanenly. B. High-Frequency Carrier To overcome he drawback of he above circuis and o provide he possibiliy of a permanen JFET urn-off, a high frequency (HF) carrier could be modulaed wih he PWM signal. In order o urn he JFET off, he HF carrier is applied o he primary of a isolaing ransformer and recified a is secondary side o provide a negaive gae bias a C 1 (Fig. 3). Whereas C 1 is charged quickly afer he HF carrier is applied, C 1 has o be discharged by R 1 o urn he JFET on, u p Fig. 2. R gs (a) u p C c D c (b) R gs Transformer Coupled circuis: (a) Simple, (b) DC Resore Circui Fig. 3. C 1 R 1 High-Frequency Carrier Circui

3 R R g 1 +U p -U p +Up u p1 u p1 T 2 u s1 Cg S 2 R 2 -U p 0 V -U s 0 1 p 2 u p2 u p2 Fig. 4. C bias u s2 Phase-Difference Circui Fig. 5. Timing diagram for Phase Difference Circui: Eiher swich or S 2 are swiched o connec C bias or o he oupu respecively. which significanly decreases he swiching speed. Therefore, addiional circuiry is required o acively discharge C 1. A HF carrier gae driver wih a resonanly operaed coreless ransformer (CT) is proposed in [9]. I has been deermined by using simulaion and measuremens ha he addiional ime o build up a seady oscillaion a he CT secondary is oo long o achieve shor rise and fall imes of and herefore high swiching frequency operaion. Furhermore, i should be noed ha he recificaion of a very high frequency carrier signal wih HT SiC diodes is poor since he available power diodes have large juncion capaciances. C. Phase-Difference Circui In order o provide coninuous negaive gae bias for he JFET, o overcome he duy-cycle limiaions ha are unavoidable wih passive driving circuis and o achieve high swiching speeds a he same ime, acively conrollable swiches like MOSFETs are required in he gae driver. A basic principle ha also applies o inegraed gae drivers is o use an sorage capacior C bias in connecion o a halfbride srucure, S 2 conneced o he JFET gae (Fig. 4). By applying appropriae conrol signals o he gaes of he wo half-bridge swiches eiher zero vols or he bias capacior volage U bias is swiched o he JFET gae. When isolaion of he conrol signals 1 and 2 is provided by ransformers and T 2 he problem of he duy cycle limiaion exising wih passive drivers is shifed o he auxiliary swiches and S 2. For an assumed 50% duy cycle ha means if u p1 is swiching and u p2 = 0 he half bridge oupu is changing beween U bias ( on) and high impedance (S 2 off) and in case ha u p1 = 0 and u p2 is swiching he halfbridge oupu is changing beween and high impedance. The acual JFET gae volage is preserved during he high impedance sae due o he JFET inpu capaciance and an opional exernal capacior as indicaed in Fig. 5. By coninuous pulsing of S 2 he circui is able o generae a saic negaive gae volage a he JFET and hus urn he JFET off permanenly. Due o he mehod of operaion he drive concep is known as a Phase-Difference Drive [10]. The bias capacior C bias iself is charged by recificaion of he carrier signals u p1 or u p2 wih he diodes or. In conclusion, he circui provides unlimied off-ime, has no duy cycle limiaion and fas swiching ransiens of he JFET because of he acive componens and S 2. D. Boosrap Power Supply To drive a JFET bridge leg, a novel Boosrap Power Supply concep is proposed for he Phase Difference Driver o simplify he bias volage generaion. Taking he negaive oupu volage ino accoun, he boosrap diodes D bs for he high-side JFET driver needs o be conneced o a volage source U P referenced o he posiive DC supply rail and charge he boosrap capaciors C bs. The capaciors C bias of he low-side JFET drives are conneced o a volage source U N referenced o he negaive DC supply rail. E. Edge-Triggered Circui A driving circui of less complexiy ha provides he same funcionaliy as he Phase-Difference Circui is he proposed Edge-Triggered Drive Circui depiced in Fig. 7. The circui basically consiss of a single pulse ransformer, an auxiliary MOSFET swich, he diode and he capacior and Fig. 6. U P U N D bs C bs C bias U P U N L 1 60 Boosrap Power Supply for he Phase Difference Driver u p u s1 u s2 Fig. 7. R1 R g Edge-Triggered Circui

4 hus only needs half he componens compared o he Phase- Difference drive wihou loss of performance as will be shown in Secion IV. The number of urns on he secondary winding 1 is seleced o achieve a peak oupu volage U s1 of a leas he JFET hreshold volage U h and he number of urns on he secondary winding 2 o provide an appropriae gae volage o. To urn he JFET off, a shor negaive volage pulse of widh T PW is applied o he ransformer primary. In his case is urned off because of he negaive gae volage u s2. The secondary volage u s1 causes o block, conducs and is charged o U s1 < U h (Fig. 8 (b)). A he end of he pulse (u p = u s1 = u s2 = ) urns off, isolaes he JFET from he pulse ransformer and hus prevens discharging hrough he ransformer secondary winding (Fig. 8 (c)). Coninuous negaive pulses can be used o permanenly urn off he JFET like depiced in Fig. 9 for a < < 0. To urn he JFET on, a posiive pulse of widh T PW is applied o he ransformer primary. Since u s2 > 0, is urned on and is discharged. The posiive volage is clamped by so ha he circui oupu volage is = (Fig. 8 (a)). For high-speed operaion care mus be aken wih he selecion of he componens. The capaciance of is a criical parameer because large values increase he rise and fall ime of he drive oupu volage. On he oher hand, he oupu capaciance C oss1 of mus be aken ino accoun: Once he volage u p1 reurns o zero afer a negaive pulse ha previously urned off he JFET, charge is drawn from in order o charge C oss1 (Fig. 8 (c)). Therefore, low values would cause an uninenional drop of he drive oupu volage. The shor pulse widh T PW is a furher advanage ha resuls in a low vol seconds produc for he ransformer and hus a minimal ransformer core size. This is imporan for minimal ransformer parasiics like leakage inducance L σ and primary o secondary coupling capaciance C c. Small L σ leads o high swiching speeds and a small C c ensures low commonmode currens resuling from he high dv/d levels of he JFET Drain-Source volage. Furhermore, i should be noed ha in pracice a volage overshoo U ov (Fig. 15) a urn-off of he JFET is observed due o he resonan circui formed by he secondary-side leakage inducance L σ of he ransformer and he sorage capacior. This behavior also has a posiive effec on he swiching speed as will be shown laer on. IV. EXPERIMENTAL RESULTS As purely passive drivers or DC resore circuis canno urn off he JFET permanenly and he HF carrier circuis lack swiching performance, he Phase-Difference and Edge- Triggered drivers are considered as candidae opologies in spie of he higher componen effor. For furher invesigaion differen versions of hese wo circuis and a sandard low emperaure gae driver (Fig. 1) were buil and esed by swiching an inducive load L wih a SiCED SiC JFET (130, 4A, U h = -25V) and a Cree CSD10060 SiC Schoky diode (120, 10A) ha are conneced o a DC link capacior C DC (Fig. 10). A. Topology Comparison For a firs performance comparison, he differen drivers were buil wih sandard componens and operaed a room emperaure. To ensure idenical measuremen condiions, each gae drive opology is roued on a separae inerchangeable PCB. Furhermore, he ransformers and T 2 of he Phase- Difference Circui and of he Edge-Triggered Circui share he same core and winding geomery. Gae resisors of R g = 10Ω, Cree SiC diodes CSD04060 in a TO package and Zeex ZVN4206G MOSFETs wih gae resisors of R 1 = R 2 = 47Ω are used in each opology. The PWM and differen drive conrol signals are generaed by a DSP and a FPGA. IC1 and IC2 of he Sandard Drive are an Analog Devices ADuM1100BR magneic coupler and an IXYS IXDN404SI MOSFET driver respecively. A capacior = 2.2nF is uilized in he Edge-Triggered Circui as a compromise beween swiching speed, gae drive losses and he volage drop in ha is encounered when C oss1 is charged. A pulse widh T PW of 130ns was found o be he minimum value o ransfer he necessary gae charge. The carrier frequency for he Phase Difference Drive is se o 1MHz wih a dead ime of 250ns when swiching beween he wo carrier signals u p1 and u p2 o preven a shor circui of he half-bridge, S 2 and oscillaions in he drive oupu. The ransformers of Phase Difference and Edge-Triggered Circui are inerfaced o he PWM FPGA by IXYS IXDN404SI driver ICs. U s1 U s1 (a) (b) C oss1 Fig. 8. Modes of Operaion of edge-riggered drive circui: (a) posiive volage pulse applied o he ransformer primary, (b) negaive volage pulse applied, (c) no volage applied o he ransformer primary. +U s1 a b 0 1 p Fig. 9. Timing diagram for Edge-Triggered Circui: Shor pulses are applied o charge or discharge he oupu capacior. u s (c)

5 Isolaed Gae Drive SiC-Diode Cree CSD10060 SiC-JFET SiCED, 6A L 150μH i L CDC 14μF 60 Fig. 10. Tes seup wih gae drive and power sage consising of a SiC JFET, a SiC diode, DC-link capacior C DC and inducor L CH1 10 CH2 10 CH Sandard 2 Phase-Difference 3 Edge-Triggered M 25ns Fig. 11. Comparison of he JFET Drain-Source volage rise imes (JFET urn-off) for differen driver opologies a room emperaure. The inducive load L is consruced using hree E30 cores, each wih a single layer winding o minimize he parasiic capaciance and C DC consiss of four 3.3µF film capaciors in parallel wih wo 220nF HV ceramic capaciors. For each driver a swiching cycle wih i L = 5A a urn-on of he JFET o i L = 6A a urn-off (Fig. 14) was iniiaed a a DC link volage of 60. The fall ime f and rise ime r (Fig. 11) measuremens of he drain source volage show no drop in swiching performance for he wo HT opologies. On he conrary, he resonan volage overshoo U ov (Fig. 15) of for he Edge-Triggered Driver improves he volage slopes. The resuling rise and fall imes are lised in Table I. Wih he Edge-Triggered Driver, which performed bes in he comparison, maximum dv/d levels of -60.0kV/µs a urn-on and 38.1kV/µs a urn-off are achieved. Therefore, high JFET swiching frequencies of 250kHz and above are feasible. B. dv/d Immuniy High dv/d levels of he JFET Drain-Source volage resul in a common mode curren hrough he parasiic coupling capaciance C c of he elecrical isolaors of a gae drive. A robus gae drive should provide a good immuniy o his curren and herefore a low C c. The ransformers for he presened drives (15:15:7 urns on a R9.5 oroid) have a C c of 12pF. The common mode rejecion of he Edge-Triggered drive is verified wih a swiched volage (60, dv/d = - 60kV/µs) ha is applied beween he shored primary winding of and he source connecor a he oupu of he drive. A disurbance of no more han 50mV is measured a he drive oupu volage during he swiching insans during nonswiching of he driver ( is blocking, C c conneced in series wih C oss1 ). Furher measuremens during he ime a conrol pulse is applied o he ransformer primary ( is conducing) will be conduced. C. High Temperaure Operaion Due o he promising performance of he Edge-Triggered Driver a room emperaure he circui was buil wih HT componens, including he ransformer (Magneics L maerial, HT wire), (Honeywell HTNFET), (SiC diode Cree CSD04060, sandard package), (AMC NPO capaciors) and HT resisors (Fig. 12). The componens are assembled on RO4530B subsrae wih HMP solder. The resisors R p, R s1 and a suppressor diode were added for proecion of he HTNFET, bu are no required for nominal operaion. The driver PCB is plugged ono a es circui according o Fig. 10 ha was buil wih X7R HV ceramic capaciors C DC and a inducive load L made of an air-gapped Meglas AMCC 25 core and silicon wire and is operaed inside a heaing oven as shown in Fig. 13. An FPGA ouside he oven and IXYS diver ICs ha are enclosed inside a box and cooled wih air from ouside he oven generae he conrol pulses. The operaion of he driver was verified wih swiching cycles as shown in Fig. 14 for a emperaure of 200 C. A 200 C and a load curren of i L = 6A he measured rise and fall imes were r = 10.7ns and f = 14.3ns according o dv/d levels of -57.1kV/µs and 41.7kV/µs. As shown in Fig. 15, no significan change in he swiching characerisics is observed when he emperaure is raised o 200 C. However, due o he emperaure dependence of he semiconducor parameers, a minor drop of he gae driver R1 D1 TABLE I SIC JFET SWITCHING TIMES AT ROOM TEMPERATURE Topology f (ns) Turn on Slope (kv/µs) r (ns) Turn off Slope (kv/µs) Sandard Phase-Difference Edge-Triggered Fig. 12. Rp T1 Rs1 S1 Cg Rg Prooype PCB of he 200 C Edge-Triggered Driver

6 Driver Box 1 -U s U ov + T Fig. 13. Gae Driver Half Bridge Inducor Tes seup inside he heaing oven for inducive load swiching ess oupu volage from -25.1V a room emperaure o -23.8V a 200 C is observed, equivalen o a low emperaure drif of 7.4mV/K for he driver circui. V. CONCLUSION In his paper differen SiC JFET gae drive opologies for use in a SiC DC/DC converer and High Temperaure (HT) operaion are evaluaed. The candidae drive circuis are seleced considering he aspecs of HT componen availabiliy and coss, gae drive performance and addiional requiremens like he abiliy o permanenly urn off a normally-on JFET. Furhermore, he passive and acive HT componens as well as he magneic and subsrae maerials for he consrucion of hese drives are invesigaed. A Phase Difference Driver and he proposed Edge-Triggered Driver are compared experimenally wih a convenional room emperaure driver in regard o performance whereas he Edge- Triggered Driver shows excellen swiching speeds and a coseffecive design due o a minimal HT componen coun CH1 25V CH2 20 i L CH3 2A M 100ns Fig. 14. Swiching cycle for he High-Temperaure Edge-Triggered Driver a 200 C and U D C =60, 5A< i L < 6A 2 CH1 25V CH C 100 C 200 C M 100ns Fig. 15. Temperaure dependence of Edge-Triggered circui oupu volage (resonan volage overshoo U ov) and he JFET drain source volage. The HT operaion of he proposed Edge-Triggered Driver is verified by swiching ess a a maximum emperaure of 200 C wihou a drop in he swiching performance. The maximum measured dv/d levels of he JFET Drain-Source volage of -57.1kV/µs and +41.7kV/µs demonsrae a very high performance of he HT Edge-Triggered Driver and he usabiliy for high swiching frequencies above 250kHz. Furhermore, he driver oupu volage shows a low emperaure drif of only 7.4mV/K. REFERENCES [1] J. Hornberger, A.B. Loseer, K.J. Olejniczak, T. McNu, S.M. Lal, and A. Manooh, Silicon-Carbide (SiC) Semiconducor Power Elecronics for Exreme High-Temperaure Environmens, in IEEE Aerospace Conference, vol. 4, Mar. 2004, pp [2] F. Renken, G. Ehbauer, V. Karrer, R. Knorr, S. Ramminger, N. Seliger, and E. Wolfgang, Reliabiliy of High Temperaure Inverers for HEV, in Power Conversion Conference 2007, Apr. 2007, pp [3] R. Kelley and M.S. Mazzola, SiC JFET Gae Driver Design for Use in DC/DC Converers, in Applied Power Elecronics Conference (APEC 2006), Mar. 2006, pp [4] S. Round, M. Heldwein, J.W. Kolar, I. Hofsajer, and P. Friedrichs, A SiC JFET Driver for a 5 kw, 150 khz Three-Phase PWM Converer, in Indusry Applicaions Sociey Annual Meeing 2005, vol. 1, Oc. 2004, pp [5] A. Orellana and B. Piebenbreier, Fas Gae Drive for SiC-JFET using a Convenional Driver for MOSFET and Addiional Proecions, in 30h annual Conference of IEEE (IECON), vol. 1, Nov. 2004, pp [6] E. Cilio, J. Garre, J. Fraley, B. McPherson, J. Hornberger, M. Schupbach, and A. Loseer, High Temperaure Elecronics (>485 C) For Venus Exploraion, in 4h Inernaional Planeary Probe Workshop, Pasadena, California, Jun [7] M. Swihar, Designing High Temperaure Magneics, in 47h European Power Elecronics Conference (PCIM), May 2003, pp [8] R. Spyker, J. Huh, I. Mehdi, and A. Brockschmid, 300C ferrie maerial for high emperaure magneics, in Power Elecronics Specialiss Conference (PESC), Jun. 2004, pp [9] S.Y. Hui, S.C. Tang, and H. Chung, Opimal Operaion of Coreless PCB Transformer-Isolaed Gae Drive Circuis wih Wide Swiching Frequency Range, IEEE Trans. Power Elecron., vol. 14, no. 3, pp , May [10] D. C. Hopkins, D. W. Kellerman, R. A. Wunderlich, C. Basaran, and J. Gomez, High-emperaure, high-densiy packaging of a 60kW converer for >200 C embedded operaion, in Applied Power Elecronics Conference (APEC), Mar. 2006, pp