VLSI Design at Intel. Dr. Steve Haynal. Formerly with Strategic CAD Labs, Intel

Transcription

1 VLSI Design at Intel Dr. Steve Haynal Formerly with Strategic CAD Labs, Intel

2 Outline Marching to Make Moore's Law True Manufacturing Design Please Ask Questions!

3 Pop Quiz Order the following in order of size (smallest first) Grains of sand Influenza A virus Transistor in high volume microprocessor in 2007 Water molecule

4 4004 First microprocessor (1971) For Busicom calculator Characteristics 10 µm process 2300 transistors khz 4-bit word size 16-pin DIP package Masks hand cut from Rubylith Drawn with color pencils 1 metal, 1 poly (jumpers) Diagonal lines (!) CSE477 L01 Introduction.4 Irwin&Vijay, PSU, 2003

5 Oliver-Smithies Lecture 1, 2007

6 Moore s Law In 1965, Dr. Gordon Moore, co-founder of Intel, extended a line on a lin-log paper plotting the number of transistors in each integrated circuit generation (4 at the time) The slope indicated a doubling of the number of transistors every year. In the article, Dr Moore expected this to go on for a few more generations and then taper off In 1975, Dr. Moore revised the curve New slope predicted doubling every 2 years. Again Dr. Moore expected this to continue for a few more generations and then taper off. For the next 30 years, Dr. Moore revisited the topic regularly The slope stayed constant at doubling every months He always thought it would continue a few more generations and then taper off.

7 Popularization of Moore s Law: The Definition of Moore s Law has come to refer to almost anything related to the semiconductor industry that when plotted on semi-log paper approximates a straight line Dr. Gordon Moore Plenary Talk February 19, 1995 E-Beam, X-Ray, EUV and I-beam Lithography for Manufacturing V Santa Clara, CA, USA

8 What He Actually Said I wanted to get across the idea that integrated circuits were a way to make electronics cheap. You could see the technology was going to let you make more complex things and the costs were going to go down. That was really the message I wanted to get across Dr. Gordon Moore San Jose Mercury News April 2, 2005

9 Moore s Law in Practice:

10 Exponential Cost Reduction Cost per transistor Number of transistors The progress has been staggering. In 1955, the annual production of transistors could be measured in the millions. In 2003, production came to around a quintillion, or a trillion million. In 1954, the average price of a transistor cost $5.52. In 2004, the average cost was 191 nanodollars, or 191 billionths of a dollar.

11 The Result

12 The Blessing/Curse of Moore s Law We know where to go, what is needed and when it is needed. "More than anything, once something like [Moore s Law] gets established, it becomes more or less a self-fulfilling prophecy. The Semiconductor Industry Association puts out a technology road map, which continues this generation [turnover] every three years. Everyone in the industry recognizes that if you don't stay on essentially that curve they will fall behind. So it sort of drives itself. (Moore, 1996) We have to get to the next generation when the law says we should no matter how hard it is

13 Through the Next Decade and Beyond Bipol ar 10µm 1µm PM NMOS OS CMOS Voltage Energy EffNew NanoScaling Scaling structures 100nm 10nm Data (Moore) Memory Microprocessor 1010 Transistors/Die 109 Carbon Nanotube FET S 10 D S 5 G Kilo Xtor 101 Mega Xtor Giga Xtor Tera Xtor Future options subject to change III-V

14 Warning! Moore s Law has been declared about to die regularly for the last 40 years. [Moore] was right, more or less. But soon, Moore's law will collide with a much less flexible set of laws the laws of physics. Within the next decade [optical lithography] probably won't be dexterous enough to shrink transistors smaller than 50 nanometers. Article published in 2005 "The price per transistor will bottom out sometime between 2003 and From that point on, there will be no economic point to making transistors smaller. So Moore's Law ends in seven years." Forbes, March 25, 1995 So far, all wrong! [Intel] use innovative design rules and advanced mask techniques to extend the use of 193nm dry lithography to manufacture its 45nm processors [in which transistors are] 20nm wide Press release Intel Corp. Jan. 27, 2007

15 Moore s law will continue to drive the semiconductor industry However... Design challenges must be overcome to fully utilize the transistor availability!

16 Manufacturing

17 In the Beginning Polycrystalline silicon (sand) is made ultra-clean Starting from a seed crystal, a large silicon ingot (single crystal) is slowly pulled from melted silicon using the Czochralski process ~300mm in diameter ~1-2 meter in length Thin wafers (~0.75 mm) are cut (sliced) Wafers are polished to mirror likeness

18 Fabrication ICs on Wafer Patterning that creates shapes for processing Lithography using masks and photoresist oxidation optical mask Modification of electrical properties Diffusion and ion implantation Deposition of various materials Physical/chemical vapor deposition, molecular beam epitaxi and/or atomic layer deposition Removal of unwanted material stepper exposure Wet/dry etching, chemical-mechanical planarization Total number of steps to make a modern microprocessor IC: ~350 photoresist removal (ashing) photoresist coating photoresist development process step spin, rinse, dry acid etch

19 Photolithography Photoresist Silicon dioxide Silicon wafer Oxidation Photoresist (PR) coating Exposure Photoresist development and bake Acid etching Unexposed (negative PR) Exposed (positive PR) Spin, rinse, and dry Mask

20 Mask Making Start with extremely clean and smooth glass plate Deposit a layer of chrome Using a laser or e-beam to draw (by removing) the desired pattern Use a stepper to expose the mask at every location. Extreme position accuracy is needed! This sounds fairly simple. HOWEVER Laser/ E-beam

21 What Happens in Reality? Illuminate mask with 193nm wavelength light (UV) Consider the result for various sizes of patterns The feature sizes are much smaller than the wavelength of the light diffraction destroys the pattern Mask 0.25µ 0.18µ 0.13µ 90-nm 65-nm Source: Synopsys Inc.

22 What is going on? Assume we use 193nm coherent (laser) light Assume a simplistic photoresist model Simple threshold model If we plot the intensity and resist response for a single small opening in the mask for a typical manufacturing lens configuration, we get:

23 What is going on? Part 2 With two holes we get:

24 In More Detail Plotting the electrical field as well:

25 Potential Solutions Reduce the wavelength of the light Extreme-UV (13.5nm) is being explored using reflective optics and reflective masks - Incredibly complex and expensive process Change what you try to pattern Make a mask that after exposure yields the desired pattern on silicon wafer Some approaches: - Optical proximity correction - Phase shifting masks - Immersion lithography

26 Using Optical Tricks With two holes, but using opposite phase, we get:

27 Complex example: If we want the pattern: 30nm we can use the mask: which yields:

28 Manufacturing Challenges Enable Moore's law with new engineering feats Design rule complexity Variation Low power Fab costs

29 Design

30 The Design Process at 10,000 ft Architect MicroArchitect Design Engineer Mask Designer Test Engineer Ideas Development Architecture Development Mapping of mask Analysis of micro- of RTL to that yield MAS architecture RTL + transistors Schematicstransistors Layout/ and wires Original Product Target Making Silicon Mask Stepping(s) Chip Validation MAS: Micro-Architecture Specification RTL: Register-Transfer Language This is the theory

31 In Practice MicroArchitect Architect Design Engineer Mask Designer Test Engineer Original Product Target Target Repainted to fit Reality ~2-3 years ~1 year

32 Effort over Time Other+Misc+Training Logic Ver Effort PV/Timing Supervision+ Recruiting+ Training Layout + Plan+Pcells Debug Circuit Dsgn + Power SV FaultGrade + Test Writing RTL Validation Testing+MAS Circuit Definition DA First P4 Architecture Development Effort

33 Architecture Analysis Development Architecture Development Mapping Analysis of micro- of RTL to MAS architecture RTL Making Silicon of mask + that yield Schematics transistors Layout/ transistorsmask Original Product Target Stepping(s) Chip and wires Validation Example: Single-core or dual-core microprocessor?

34 Processor Architecture 101 Delivered Performance ~ Instructions per cycle (IPC) * Frequency Goal is higher performance and lower power Power consumption ~ Cdynamic * V * V * Frequency Cdynamic is roughly a product of area and activity: area ~ how many transistors * how big transistors activity ~ how often do they change from on to off and back V = voltage

35 Processor Architecture 101 Delivered Performance ~ Instructions per cycle (IPC) * Frequency Power consumption ~ Cdynamic * V * V * Frequency + For Silicon: Frequency ~ V

36 Processor Architecture 101 Delivered Performance ~ IPC * V Power consumption ~ Cdynamic * V * V * V Performance Power Single +20% -20% Dual Conclusion: Dual-core gives better performance and performance/watt!

37 Micro-Architecture Development Development Architecture Development Mapping Analysis of micro- of RTL to MAS architecture RTL Making Silicon of mask + that yield Schematics transistors Layout/ transistorsmask Stepping(s) Chip and wires Validation Examples: Floor planning & Accumulator design Original Product Target

38 Floorplanning & µ-architecture Function Decomposition Architectural Breakdown A B A-align B-add C-normalize D-round D C Flopped Repeater A Pick a frequency F B D Layout Floorplan #1 A C C B Piped interconnect distance 1 Tick D Layout Floorplan #2

39 Accumulator Design How to design a fast, but power-efficient, accumulator supporting back-to-back additions? The circuit reads a 64-bit quantity every clock cycle The circuit adds the input to a running sum The output of the sum is delayed by one clock cycle

40 Alternative 1 r[63:0] i[63:0] + s[63:0] o[63:0] Pros: Simple to model Output arrives very early in the clock cycle Cons: 64 bit adder is very difficult to make fast and power-efficient Inputs are needed very early in the clock cycle

41 Alternative 2 i[63:0] j[63:0] + s[63:0] o[63:0] Pros: Simple to model Input can arrive very late in the clock cycle Output arrives very early in the clock cycle Cons: 64 bit adder is very difficult to make fast and power-efficient

42 Alternative 3: Split & Stagger Add rl[31:0] i[63:0] i[31:0] + o[31:0] sl[31:0] cout o[63:0] cin rh[63:32] i[63:32] j[63:32] + sh[63:32] Pros: Only need to create a 32-bit addition in one cycle (plenty of time->low power) Most significant inputs can arrive late in the clock cycle Outputs arrive early in the clock cycle Cons: Least significant inputs are needed fairly early in the clock cycle.

43 Mapping to Transistors Development Architecture Development Mapping Analysis of micro- of RTL to MAS architecture RTL Making Silicon of mask + that yield Schematics transistors Layout/ transistorsmask and wires Validation Example: How to design a 32-bit adder? Stepping(s) Chip Original Product Target

44 Alternative 1: Serial Adder Pros: Very small Very power efficient Cons: Extremely slow 700ps 720µm2

45 Alternative 2: Kogge-Stone Adder Pros: Minimum logic depth Very fast Cons: Very large Very power hungry Difficult to route (many wires) 120ps 2900µm2 200ps 2700µm2

46 Alternative 3: Sklansky Adder Pros: Minimum logic depth Fairly power efficient if not pushed for speed Cons: High fanout of some gates Large, if pushed for speed 225ps 1270µm2 150ps 2100µm2

47 Layout Creation Development Architecture Development Mapping Analysis of micro- of RTL to MAS architecture RTL Making Silicon of mask + that yield Schematics transistors Layout/ transistorsmask Original Product Target Stepping(s) Chip and wires Validation Example: How to make the mask for a CMOS inverter?

48 Simplified CMOS Inverter cut line

49 P-Well Mask

50 Active Mask

51 Poly Mask

52 P+ Select Mask

53 N+ Select Mask

54 Contact Mask

55 Metal Mask

56 Layout Editor

57 The Challenge in Mask Design Design Rules are used to ensure only well behaved transistors/wires/ are produced Design rules have been added to ensure reliability and/or manufacturability 500 As feature sizes have become smaller and smaller, the number and complexity of the design rules have increased enormously 200 Checking for violation (DRC) is now extremely time consuming Number of design rules in each process generation um 0.25um 180nm 150nm 130nm 90nm

58 Making of Silicon + Testing Development Architecture Development Mapping Analysis of micro- of RTL to MAS architecture RTL Making Silicon of mask + that yield Schematics transistors Layout/ transistorsmask Original Product Target Stepping(s) Chip and wires Validation How to get, test and check first/second/ silicon?

59 Making of Silicon + Testing The layout masks (the desired masks) are sent through the maskgeneration program that computes the needed masks to get the desired results Extremely compute intensive Extremely large amounts of data Once chips are manufactured, testing is started First ½ hour on tester yields more cycle run than total number of cycles simulated pre-silicon! Testing is often done without heat sink so we use a lot of liquid Nitrogen!

60 Validation Development Architecture Development Mapping Analysis of micro- of RTL to MAS architecture RTL Making Silicon of mask + that yield Schematics transistors Layout/ transistorsmask Original Product Target Stepping(s) Chip and wires Validation How to: 1) check we captured what we wanted 2) check that we did not make a mistake along the way

61 What Needs to be Validated? Functionality +?? Performance Power & Thermal Physical form Documentation Reliability Testing procedure Goal Actual

62 Coverage 100 % Covered Pro Con Formal Verification 100% coverage Requires special skills Proves absence of bugs Constrained by complexity Directed Random Tests Targets areas most likely to be of concern Requires strong uarch knowledge Greatly reduces cycle requirements Develops strong uarch knowledge Generic Random Tests After generator created, easy to write Requires almost cycles / time Requires little uarch knowledge Difficult / impossible to avoid broken features Can create things no one would ever think of Low % Covered Directed Tests Easy to write Easy to understand Easy to reuse Requires almost number of tests Difficult to hit uarch conditions

63 Design Productivity Trends 100,000 Logic Tr./Chip 1,000 10,000 Tr./Staff Month ,000 58%/Yr. compounded Complexity growth rate x 0.1 x x 0.01 xx x 1 21%/Yr. compound Productivity growth rate x x Productivity (K) Trans./Staff - Mo. Logic Transistor per Chip (M) Complexity 10, Complexity outpaces design productivity CSE477 L01 Introduction.63 Courtesy, ITRS Roadmap Irwin&Vijay, PSU, 2003

64 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT Vin Vout G S n+ CSE477 L01 Introduction.64 DEVICE D n+ Irwin&Vijay, PSU, 2003

65 Design Challenge: Validation The designs are getting increasingly complex The real logic definition is a very low-level description of the design and is constantly changing Too many design models that need to be verified against each other Source: Synopsys Today 1/3-1/2 of design team is devoted to validation for ASICs >50% validation! Source: Synopsys

66 Design Crisis Pentium Processor: In-order Pentium 4 Processor: OO, TraceCache, Complexity of design Multi-objective convergence Timing, power, area, etc. feedback way too late in design schedules PSC P5 Plan P6 WMT NHM? Analyze Design weeks/months Bottom line: Existing design approaches inadequate for the design of future processors/chips Increasing rate (~4x per lead) 486 Tapeout # Pre-silicon bugs NWD WMT P Trillions of simulation cycles on a rapidly changing model P P Bug rate rising 4x per lead Validation of design , Files 6000 Checked In 5000 #Total Lines 4000 Lines Changed 3000 Column E Column D Multi-million line RTL ,000, Performance, ERTL, GRTL, Schematics, ,500, ,000, Number & size of models 2,500, More transistors More functionality More design effort Lines of RTL 0

67 Mind the Gap! Ever higher abstraction levels needed to capture system functionality Major research topic! Opposing Forces driving System Design Increased attention to details of physical & manufacturing realities

68 Answer to Pop Quiz Order the following in order of size (smallest first) ~100nm ~30nm ~1nm ~100,000nm Grains of sand Influenza A virus 3 Transistor in high volume microprocessor in Water molecule 1 4

69 Questions