Chapter 2 Silicon Planar Processing and Photolithography

Transcription

1 Chapter 2 Silicon Planar Processing and Photolithography The success of the electronics industry has been due in large part to advances in silicon integrated circuit (IC) technology based on planar processing, which involves the fabrication of fine structures on semiconductor wafers via a sequence of steps, layer-by-layer. What began as silicon microfabrication has now developed into nanofabrication: As shown in Fig. 2.1, feature sizes of silicon ICs reached the nanoscale over a decade ago, propelled by Moore s Law 1 or the continued exponential increase in the number of transistors per IC over the past 50 years. 2 Virtually all the electronics technology in use today (digital and/or analog) is built upon silicon ICs created using planar processing methods, as described in this chapter. The main steps used to create and process a silicon wafer for IC fabrication are listed below 1. Crystal growth and wafer formation. 2. Patterning. 3. Dopant deposition. 4. Dielectric formation. 5. Etching. 6. Metal deposition. 7. Formation of interconnect layers. 8. Packaging and testing. Steps 2 6 create the various device structures on a semiconductor wafer surface and are collectively referred to as the front-end processing of an integrated circuit, whereas the interconnection of the various components to form a functional electric circuit in step 7 is known as the back-end processing and consists of several levels (e.g., up to 10 or more) of metallic wiring in modern ICs. We can immediately see 1 For the genesis of Moore s Law see G.E. Moore, Electronics 38, 114 (1965). 2 At present silicon electronics can contain upwards of 1 billion transistors per IC or chip. The Author(s) 2016 C. Papadopoulos, Nanofabrication, SpringerBriefs in Materials, DOI / _2 7

2 8 2 Silicon Planar Processing and Photolithography Fig. 2.1 Minimum feature size (nominal) of integrated circuits versus year of commercial production (Intel Corp.) the hybrid nature of the IC fabrication process where bottom-up or additive approaches (steps 1, 3, 4, 6 and 7) are combined with top-down or subtractive methods (steps 2 and 5). 3 The order of steps 2 7 may vary somewhat depending on the particular IC devices and functions but the overall approach and process flow is very well-established Photolithographic Patterning From a nanofabrication standpoint, once a single crystal cylindrical ingot of silicon is grown and cut into circular wafers (roughly 12 inches in diameter and 0.5 mm thick at present and most often covered with a sub-micron layer of silicon dioxide or other dielectrics), the principal patterning step (2) that generates nanoscale features in the lateral dimension is photolithography. 5 Building upon earlier photoengraving and chemical etching techniques used for printed circuit boards, photolithography employs a photosensitive polymer, or photoresist, 6 which is exposed to light that has traveled through a predefined mask or reticle, and subsequently developed to allow very fine features to be printed across the surface of a wafer, thus defining the patterns that result in the very high density of devices in an integrated circuit. The chemical and physical properties of the photoresist itself must meet stringent requirements in order to produce the required patterns with sufficient yields, such as optical absorbance at the required exposure wavelength, etch resistance of unexposed regions, photochemical sensitivity, etc., and many 3 Steps 2 7 are essentially applied in a parallel manner across the surface of a wafer, which leads to a roughly constant manufacturing cost per unit area regardless of the number of components created from individual discrete devices to chips containing billions of devices. 4 Multiple planarization polishing steps are also included at various points during processing. 5 The term lithography originates from the traditional stone printing surfaces used for writing/transferring patterns and thus lithos the Greek word for stone. 6 Also known simply as resist.

3 2.1 Photolithographic Patterning 9 different resists have been developed and improved over time in order to meet the needs of IC manufacturing technology. 7 The schema in Fig. 2.2 outlines the overall photolithographic patterning process flow: Wafers are first spin-coated (a.k.a. spin-casting) with a thin layer of (positive or negative) photoresist solution that is subsequently baked or cured into a thin solid film (Fig. 2.2a). The resist layer is then exposed to light (Fig. 2.2b) that is a focused optical projection of the pattern contained in a mask (typically a glass/quartz substrate coated with a patterned metal film, e.g., chromium). The regions exposed to light (or their complement if a negative resist is used) are then removed chemically or dissolved using an appropriate solvent (i.e., developer solution) and thus the desired pattern is printed (Fig. 2.2c). At this point the photoresist pattern is typically transferred into the underlying wafer substrate wherein further processing occurs (see Sect. 2.2) before finally being stripped away or removed completely once it is no longer needed. This type of photolithographic patterning step is repeated several times for the various devices and levels of an IC. The resolution of lens-based optical lithography described above is subject to diffraction (analogous to an optical microscope), i.e., the spatial spreading of light when it is constrained to small dimensions compared to its wavelength. The minimum feature size or resolution, R min, is given by the so-called Rayleigh equation 8 k R min ¼ k R NA ; ð2:1þ where λ is the wavelength of light illumination, NA is the numerical aperture 9 of the optical imaging system, and k R is a coefficient whose value is typically between 0.25 and 0.8, which depends on the particular optics, mask and photoresist technology used. The wavelength dependence on resolution arises from a Fourier analysis (in the spatial domain) of a finite width light beam, which leads to an uncertainty relation between wavevector and the extent of beam confinement that ultimately results in diffraction (more confinement causes a larger dispersion in wavevector and thus more beam spreading). Since wavevector is inversely proportional to wavelength, larger magnitude wavevectors (i.e., shorter wavelength lightwaves) are less affected by diffraction effects or, mathematically, we can say that beam spreading can only be ignored if λ/w 1, where w is the width of the beam. According to Eq. (2.1), reducing wavelength is one way to define finer features and today 193-nm photolithography (deep UV) is standard in industry for creating the highest density structures on silicon ICs. The illumination can also be optimized to achieve better resolution via off-axis illumination (OAI), which improves the 7 See, e.g., G.M. Wallraff, W.D. Hinsberg, Chem. Rev. 99, 1801 (1999). 8 Lord Rayleigh, Phil. Mag. S. 5 8, 261 (1879). 9 The numerical aperture is defined as n sin h, where n is the incident refractive index and h is the angular aperture of the lens or the half-angle of the maximum light cone that can be collected.

4 10 2 Silicon Planar Processing and Photolithography Fig. 2.2 Patterning via projection photolithography. a Photoresist application. Note that in general optical anti-reflection coatings can also be added to the top (TARC) and bottom (BARC) of the resist film in order to improve imaging contrast. b The mask pattern (top) is focused via optical lenses onto the semiconductor wafer in order to expose the photoresist layer. Process is repeated over the entire wafer by stepping its location underneath the mask, which is then typically scanned over each exposure field (step and scan process). c Photoresist is developed in order to reveal mask pattern (positive resist shown) (a) (b) (c)

5 2.1 Photolithographic Patterning 11 sharpness of the projected mask image by allowing the capture of some light that would otherwise be lost via diffraction with normal incidence illumination (the angle of the incident light away from the normal essentially redirects one side of the diffracted beam back into the imaging system). Illumination enhancements such as OAI must be designed in unison with the particular mask pattern. In addition to the light source, photolithographic resolution can also be improved by directly modifying the photomask material itself. In particular, phase-shift masks (PSMs) allow sharper features to be defined by modifying the optical path length of light as it travels through the mask via the addition (or removal) of material in order to produce destructive interference of light waves for adjacent patterns through a 180 difference in phase (see Fig. 2.3). Optical proximity correction (OPC) is another photomask modification technique that involves changing the mask pattern from the ideal or desired layout to one that tries to compensate for the various optical limits on resolution to produce a final printed image that is as close as possible to the ideal one. OPC typically either involves applying certain design rules to the mask design or an iterative mask optimization process involving multiple computational simulations. More recent innovations include: (i) Immersion lithography, which results in an effective reduction in photolithographic wavelength by placing the mask projection system within a fluid with larger refractive index than air; and (ii) Multiple patterning, which employs 2 or more offset mask exposure processes per layer in order to create a higher density of patterns. These developments and improvements in state-of-the-art photolithography approaches have resulted in IC feature sizes that are now approaching 10 nm. Lastly, we mention photolithography based on 13.5 nm radiation (Extreme UV) incorporating reflective optics has been under development for several years and could be in place for electronics manufacturing within 5 10 years as minimum feature sizes likely dip well below 10 nm. Fig. 2.3 Comparison between a standard (or binary) photomask and phase-shift mask. The destructive interference of light waves for adjacent features in the phase-shift mask results in sharper images

6 12 2 Silicon Planar Processing and Photolithography 2.2 Thin Film Deposition Once the mask pattern has been printed into the photoresist layer, the subsequent semiconductor processing steps involve either etching away exposed layers (in the simplest case, a selective wet chemical etch can be used but more typically a dry chemical etch process such as reactive ion-etching (RIE) results in better control for high-resolution features), or adding material such as dopant atoms 10 selectively on the exposed Si regions to create the device structures and various junctions required for the IC. Thin film deposition is a general term used to describe the growth (typically in the vertical dimension or perpendicular to the wafer surface, although non-planar conformal coating is also possible), usually from a vapor or liquid phase, of thin (down to a nanometer or less) two-dimensional layers of material. Thin film growth is combined with photolithographic patterning to create the various layers (insulating, semiconducting, metallic) that are necessary for the isolation, operation and interconnection of the various devices on an integrated circuit. Several thin film deposition techniques are available depending on material/process requirements, which can be broadly classified as either chemical vapor deposition (CVD) or physical vapor deposition (PVD). 11 In CVD, a gas or vapor reacts at the surface of a substrate to form a thin film. Thermal oxidation of silicon wafers via exposure to oxygen gas (or water vapor) at elevated temperatures in a furnace is one very commonly used example of a CVD technique for IC electronics and discrete devices. It is also possible to have similar thin film growth processes occur from the liquid phase, with the most important for planar processing coming in the form of electrochemical deposition of copper for the metallic interconnects/electrodes in modern ICs, which replaced aluminum for most applications over a decade ago. In PVD on the other hand, there is generally no chemical reaction and the thin film is directly deposited by vaporizing solid source material which condenses on the substrate. This typically involves heating a crucible containing the material to be deposited via resistive methods (current flow) or direct heating by exposure to a focused electron beam. 12 Sputter deposition (or simply sputtering) on the other hand, employs ions such as from a plasma to strike a target surface in order to release or sputter material onto the desired substrate. The appropriate PVD method for a specific application will usually be dictated by the properties of the material(s) to be deposited, film thickness/quality and required deposition rate. Epitaxy is a special type of thin film deposition whereby atoms self-assemble on an existing crystal substrate into a crystalline film, atomic layer-by-atomic layer. 10 Dopants are usually added from the vapor phase using either a thermal diffusion process, or electric field-assisted ion-implantation for more accurate placement near the semiconductor surface. 11 Most types of thin film deposition from the vapor phase occur inside an enclosed chamber that is either under vacuum or filled with appropriate gas species. 12 See Chap. 3 for details on electron beams; formation and focusing.

7 2.2 Thin Film Deposition nm Fig. 2.4 Integrated circuit cross-section showing 8 copper interconnect levels on top of silicon wafer. Inset shows individual transistor structure at wafer surface (45 nm process) (source Intel Corp.) An epitaxial film can be grown via either CVD or PVD processes but requires an underlying single crystal substrate to act as the seed or template in order for epitaxy to occur. The quantum wells shown in Fig. 1.2 of the previous chapter are one very common application of epitaxial growth. Quantum wells are widely used in optoelectronics, particularly semiconductor lasers. Epitaxy is also very important for modern electronics with state-of-the-art IC transistors employing epitaxial growth of SiGe alloy contacts in order to introduce strain at the silicon wafer surface, which leads to improved device performance. IC technology based on different types of epitaxial semiconductor thin films grown on top of silicon is also under development in order to further enhance device properties and allow scaling or Moore s Law to continue in the future. The example in Fig. 2.4 displays a cross-section transmission electron microscope image of an IC created using the planar processing sequence(s) described above. Zooming in on the surface of the wafer shows the individual nanoscale device (and interconnect) structures that are possible via this nanofabrication technology. 2.3 Summary Silicon planar processing has been refined to a degree perhaps unmatched by any other technology in history. The ability to combine billions of nanoscale devices monolithically onto a single piece of semiconductor has largely been enabled by advances in photolithographic patterning. The great growth and success of electronics (and the resulting information technology) based on fabrication via planar processing has evolved over the last 50 years both in terms of complexity (leading to tremendous performance gains, e.g., in computational/information processing

8 14 2 Silicon Planar Processing and Photolithography power and memory density) and also cost: A well-equipped modern semiconductor fabrication facility (or fab) typically requires on the order of several billion USD investment, 13 and the industry is now consolidated into a select few leading manufacturers and foundries that can be contracted to produce ICs for various customers. Even for small volume production or research, high-resolution projection lithography tools and the ancillary fabrication equipment will run into the tens of millions of dollars. References 1. D.P. Sanders, Chem. Rev. 110, 321 (2010) 2. J.D. Plummer, M.D. Deal, P.B. Griffin, Silicon VLSI Technology (Prentice Hall, New Jersey, 2000) 3. S.A. Campbell, The Science and Engineering of Microelectronic Fabrication, 2nd edn. (Oxford University Press, New York, 2001) 4. International Technology Roadmap for Semiconductors, ; 13 This will depend on the particular fabrication technology node at present 14 nm, with 10 nm next on the horizon.

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