CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom

Transcription

1 CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom

2 ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in former series International Series in Engineering and Computer Science: SIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONING Philips, K., van Roermund, A.H.M. Vol. 874, ISBN CALIBRATION TECHNIQUES IN NYQUIST A/D CONVERTERS van der Ploeg, H., Nauta, B. Vol. 873, ISBN ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIP Fayed, A., Ismail, M. Vol. 872, ISBN WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS Doris, Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES Pastre, Marc, Kayal, Maher Vol. 870, ISBN: HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: X DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifânio da Franca, José Vol. 867, ISBN: DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, José (Eds.) Vol. 860, ISBN: ANALOG DESIGN ESSENTIALS Sansen, Willy Vol. 859, ISBN: , DESIGN OF WIRELESS AUTONOMOUS DATALOGGER IC S Claes and Sansen Vol. 854, ISBN: MATCHING PROPERTIES OF DEEP SUB-MICRON MOS TRANSISTORS Croon, Sansen, Maes Vol. 851, ISBN: LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS Leroux and Steyaert Vol. 843, ISBN: SYSTEMATIC MODELING AND ANALYSIS OF TELECOM FRONTENDS AND THEIR BUILDING BLOCKS Vanassche, Gielen, Sansen Vol. 842, ISBN: LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENT REDUCTION van der Meer, van Staveren, van Roermund Vol. 841, ISBN: WIDEBAND LOW NOISE AMPLIFIERS EXPLOITING THERMAL NOISE CANCELLATION Bruccoleri, Klumperink, Nauta Vol. 840, ISBN: CMOS PLL SYNTHESIZERS: ANALYSIS AND DESIGN Shu, Keliu, Sánchez-Sinencio, Edgar Vol. 783, ISBN: SYSTEMATIC DESIGN OF SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS Bajdechi and Huijsing Vol. 768, ISBN: OPERATIONAL AMPLIFIER SPEED AND ACCURACY IMPROVEMENT Ivanov and Filanovsky Vol. 763, ISBN: STATIC AND DYNAMIC PERFORMANCE LIMITATIONS FOR HIGH SPEED D/A CONVERTERS van den Bosch, Steyaert and Sansen Vol. 761, ISBN: DESIGN AND ANALYSIS OF HIGH EFFICIENCY LINE DRIVERS FOR Xdsl Piessens and Steyaert Vol. 759, ISBN:

3 CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom Error Analysis and Practical Design By R. del Ro í F. Medeiro B. Pérez-Verdú J.M. de la Rosa and Á. Rodríguez-Vázquez Spanish Microelectronics Center IMSE-CNM and University of Seville, Spain

4 A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN (HB) ISBN (HB) ISBN (e-book) ISBN (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. Printed on acid-free paper All Rights Reserved 2006 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed in the Netherlands

5 CONTENTS List of Abbreviations xi Preface xv CHAPTER 1 ADCs: Principles, Architectures, and State of the Art Analog-to-Digital Conversion: Fundamentals Sampling Quantization Oversampling ADCs: Fundamentals Oversampling Noise-shaping Basic architecture of oversampling ADCs Performance metrics Ideal performance Single-Loop Architectures st-order modulator nd-order modulator High-order modulators Stability concerns Optimized NTFs High-order topologies Non-linear stabilization techniques Cascade Architectures Multi-Bit Architectures Influence of DAC errors Element trimming and analog calibration Digital correction Dynamic element matching Dual-quantization Leslie-Singh architecture Single-loop Ms Cascade Ms v

6 vi Contents 1.6. Parallel Architectures Frequency division multiplexing Time division multiplexing Code division multiplexing State of the Art in ADCs Summary CHAPTER 2 Non-Ideal Performance of Modulators Integrator Leakage Leaky integrator Single-loop modulators st-order loop nd-order loop Lth-order loops Cascade modulators Capacitor Mismatch Single-loop modulators nd-order loop Lth-order loops Cascade modulators Integrator Settling Error Model for the transient response of SC integrators SC integrator model Transient during integration Transient during sampling Integration-sampling process Validation of the proposed model Comparison with experimental results Comparison with traditional models Effect of the amplifier finite gain-bandwidth product Single-loop modulators Cascade modulators Effect of the amplifier finite slew rate Effect of the switch finite on-resistance Effect on an ideal integrator Effect on the amplifier GB Effect on the amplifier SR Circuit Noise Noise in track-and-holds Track component

7 Contents vii Sampled-and-held component Folding-back effect Noise in SC integrators Switches controlled by Switches controlled by Opamp noise Noise in the references Total noise Circuit noise in modulators Fully-differential circuitry Clock Jitter Sources of Distortion Distortion due to the non-linear capacitors Distortion due to the amplifier non-linear gain Distortion due to the switch non-linear on-resistance Distortion due to the non-linear settling Summary CHAPTER 3 A Wideband Modulator in 3.3-V m CMOS Design Methodology Topology Selection Switched-Capacitor Implementation Specifications for the Building Blocks Modulator sizing Fast modulator sizing Fine-tuning of blocks specs Integrator scaling Design of the Building Blocks Amplifiers Front-end amplifier Remaining amplifiers Comparators Switches Capacitors Programmable A/D/A converter A/D converter D/A converter Control circuitry Clock phase generator

8 viii Contents 3.6. Layout and Prototyping Experimental Results Performance of the A/D/A converter Influence of jitter noise Influence of settling errors Influence of switching noise Performance Summary Performance Comparison with the State of the Art Summary CHAPTER 4 A Modulator in 2.5-V m CMOS for ADSL/ADSL Topology Selection Switched-Capacitor Implementation Specifications for the Building Blocks Design of the Building Blocks Amplifiers Front-end amplifiers Back-end amplifiers Non-linearities Comparators Switches Capacitors A/D/A converter A/D converter D/A converter Clock phase generator Auxiliary blocks Reference voltage generator Master current generator Anti-aliasing filter Layout and Prototyping Experimental Results Performance Summary Performance Comparison with the State of the Art Summary

9 Contents ix CHAPTER 5 A Modulator with Programmable Signal Gain for Automotive Sensor Interfaces Basic Design Considerations Architecture Selection and High-Level Sizing Modulator architecture SC implementation High-level sizing and building-block specifications Design of the Building Blocks Amplifiers Comparators Switches Capacitor arrays Auxiliary blocks Layout and Prototyping Experimental Results Summary APPENDIX A An Expandible Family of Cascade Modulators A.1. Topology Description A.2. Non-Ideal Performance APPENDIX B Power Estimator for Cascade Modulators B.1. Dominant Error Mechanisms B.2. Estimation of Power Consumption REFERENCES Index

10 LIST OF ABBREVIATIONS M A/D, A-to-D ADC ADSL AFE AGC BiCMOS BP M CAD CDMA CLA CMFB CMOS CPE CPU CT D/A, D-to-A DAC DC DDS DEM DMT DNL DOR DR DSL DSP DT DWA EDGE ENOB ESD Parallel Sigma-Delta Sigma-Delta Sigma-Delta Modulator Analog-to-Digital Analog-to-Digital Converter Asymmetric Digital Subscriber Line Analog Front-End Automatic Gain Control Bipolar and Complementary Metal-Oxide-Semiconductor Band-Pass Sigma-Delta Modulator Computer Aided Design Code Division Multiple Access Clocked Averaging Common-Mode Feedback Complementary Metal-Oxide-Semiconductor Customer Premises Equipment Central Processing Unit Continuous-Time Digital-to-Analog Digital-to-Analog Converter Direct Current Data Directed Scrambling Dynamic Element Matching Discrete Multi-Tone Differential Non-Linearity Digital Output Rate Dynamic Range Digital Subscriber Line Digital Signal Processing Discrete-Time Data Weighted Averaging Enhanced Data-rates for Global Evolution Effective Number Of Bits Electrostatic Discharge xi

11 xii List of Abbreviations FFT FIR FOM FS GB GPS GSM HD HDSL IBE IC IIR ILA INL IO ISDN LNA LP M LSB MASH MEMS MiM MOS MOSFET, MOST MSB MTPR nmos NTF Opamp OS OSR OTA PCB PDF PDM PLC Fast Fourier Transform Finite Impulse Response Figure Of Merit Full Scale Gain-Bandwidth Product Global Positioning System Global System for Mobile-Communications Harmonic Distortion High-data-rate Digital Subscriber Line In-Band Error Integrated Circuit Infinite Impulse Response Individual Level Averaging Integral Non-Linearity Input/Output Integrated Services Digital Network Low-Noise Amplifier Low-Pass Sigma-Delta Modulator Least Significant Bit Multi-Stage Noise Shaping Micro-Electro-Mechanical System Metal-insulator-Metal Metal-Oxide-Semiconductor Metal-Oxide-Semiconductor Field-Effect Transistor Most Significant Bit Multi-Tone Power Ratio N-channel MOS Noise Transfer Function Operational Amplifier Output Swing Oversampling Ratio Operational Transconductance Amplifier Printed Circuit Board Probability Density Function Pulse-Density Modulated Power Line Communications

12 List of Abbreviations xiii PLL pmos PROM PSD RAM RF ROM S/H SC SDLS SFDR SI SNR SNDR SoC SR STF THD TI UMTS UWB VDSL VLSI WLAN WMAN xdsl Phase-Locked Loop P-channel MOS Programmable Read-Only Memory Power Spectral Density Random Access Memory Radio Frequency Read-Only Memory Sample-and-Hold Switched-Capacitor Symmetrical Digital Subscriber Line Spurious-Free Dynamic Range Switched-Current Signal-to-Noise Ratio Signal-to-(Noise+Distortion) Ratio System-on-Chip Slew Rate Signal Transfer Function Total Harmonic Distortion Time-Interleaved Sigma-Delta Universal Mobile Telecommunications System Ultra-Wide Band Very-high-data-rate Digital Subscriber Line Very Large Scale of Integration Wireless Local Area Network Wireless Metropolitan Area Network All/any Digital Subscriber Line

13 PREFACE The rapid evolution experimented by microelectronics during the last decades has propitiated the birth and spread of lots of electronic systems with increasing presence in different aspects of our everyday life: consumer electronics, information technology, communications, automotion, medicine, leisure, etc. Probably, communications has been one of the areas with largest expansion; many applications have been developed, both for wireline systems DSL technologies for broadband access to the Internet, PLC technology, etc. [Gagn97] and for wireless systems mobile telephony, GPS, WLAN, WMAN, UWB, etc. [Abidi95]. No doubt, the continuous scaling of VLSI technologies has been a determinant factor for this rapid evolution. Technology scaling has allowed miniaturization, portability, increased functionality, and cost reduction of these systems. Nowadays, it is possible to integrate millions of transistors in a single chip using submicron CMOS processes and, simultaneously, the speed of digital circuits has increased up to the gigahertz range. This technological advances have enabled monolithic integration of complete electronic systems on a single chip (SoC), in which digital signal processing (DSP) techniques are extensively used for robust implementation of complex algorithms within reduced computational times. In these systems, the present trend is to move the border between the analog and digital parts, usually called interface, as close as possible to the point where information is received or emitted. In this way, most of the SoC functionalities are implemented in the digital domain, where the system benefits from the reduction of silicon area, supply voltage, and power consumption, and from the increased operation speed that are peculiar to the progressive technology scaling. The application of analog circuits is then restricted, in most cases, to interface tasks: signal conditioning, filtering, and analog-to-digital (A-to-D) and digital-to-analog (D-to-A) conversion. In addition, the trend to massive digital processing and to an earlier digitalization of signals leads to an increase of the dynamic range and bandwidth requirements in the interface circuits. On the other hand, the design of high resolution, high bandwidth converters is greatly involved when they are integrated together with the DSP circuits, mainly because the designers must use mainstream digital CMOS processes, in which analog primitives are not fully optimized [Bult00] [Malo01]. Thus, these converters have to operate with low voltage supply and transistors whose threshold voltages are comparatively high, with no use of extra process steps to improve the linearity or the matching of the devices, and, above all, in an hostile environment full of noisy digital circuits. Among the existing techniques to perform the A-to-D conversion, those based on modulation [Inose62] offer key advantages for their implementation in SoCs. Unlike traditional converters, which require high accuracy in their building blocks in order to xv

14 xvi Preface achieve overall high accuracy, the oversampling and noise-shaping techniques employed in converters allow to trade speed for accuracy. In this way, an operation that is relatively insensitive to imperfections on the analog circuit can be obtained at the cost of increased complexity and speed in the associated digital circuitry (needed for post-processing) [Nors97]. These demanding requirements on the digital part, which were a handicap for the integration of converters before the development of VLSI technologies, now relax the implementation of the analog section, whose requirements are more difficult to achieve in processes with a clear digital orientation. This has motivated that, although being originally conceived for low-frequency, high-resolution applications like audio [Candy85] [Adams86] [Boser88] [Bran91a] and precision measurement [Sign90] [Yama94], the usage of converters has progressively spreaded across medium- and high-frequency applications [Bran91b] [OptE91] [Yin94] [Broo97]. Fig. 1 illustrates the state of the art in A-to-D converters in CMOS technologies reported up to year 2000 and places them in the resolution bandwidth plane. The ranges of the specifications for the main applications are depicted on this plane in an approximated way. It can be observed that modulation-based A-to-D converters cover a wide frequency FIGURE 1 State of the art in A-to-D converters in CMOS technologies reported up to year (The ranges of the applications shown are approximated).

15 Preface xvii interval, ranging from 100Hz to 10MHz. Higher speed applications are still dominated by Nyquist-type converters (especially, pipeline, folding-interpolative, and flash) [Plas94] [Raza95]. Oversampling techniques are little efficient in these applications, because of the excessive operation speed that is required in the analog blocks. However, converters are clearly dominant in measurement, voice, and audio systems, and coexist with algorithmic, subranging, and pipeline converters in systems for mobile communications and broadband wireline applications like ADSL. Furthermore, it is commonly accepted that whenever an industrial application can be covered by using a converter, the simpler the better, this solution should be considered as the optimum one, for feasibility, yield, robustness, and time-to-market reasons [Rivo03]. In these applications, the implementation of Nyquist converters gets involved as the technology scales down: calibration techniques that consume considerable area and power are required in order to achieve resolutions larger than 13 bits [Mayes96] [Opris00] [Guil01]. As an alternative, the use of converters has gained ground and architectures that are oriented to high-frequency applications have been successfully implemented. In these architectures, the weakened benefits of oversampling (necessarily moderate) are compensated by resorting to high-order topologies either in a single loop [Geer00] or in a multi-stage cascade [Yin94] [Feld98] [Marq98] [Geer99] [Mori00], which often incorporate multi-bit quantization either pure [Geer00] [Fuji00] or by means of dual- quantization techniques [Bran91b] [Broo97] [Mede99]. Nevertheless, the prototypes implemented so far demonstrate the viability of converters for high-frequency applications ( 1MHz ), but not that their incorporation to SoCs is still robust in deep-submicron processes. Indeed, only a few prototypes [Geer99] [Fuji00] [Mori00] have been integrated in modern deep-submicron CMOS technologies, but they are mixed-signal oriented they offer better device matching and supply voltages of 3.3V, or even 5V, together with low-vt transistors [Fuji00]. In this scenario, the work presented in this book tries to demonstrate the viability of robust high-frequency, high-resolution converters using deep-submicron CMOS technologies oriented to the development of SoCs. This encompasses an adequate selection of architectures, techniques, and building blocks that allow, not only to obtain highperformance modulators, but also to solve the problems associated to their practical implementation in digital-oriented VLSI technologies (low supply voltage, poor linearity and matching of devices, etc.). The results of this work are demonstrated through two prototypes for broadband applications that are integrated in deep-submicron CMOS technologies. They have been developed in the frame of the EU ESPRIT Project (MIXMODEST) and the Spanish CICYT Projects TIC and TIC (ADAVERE), devoted to the investigation of architectures and techniques for the implementation of A-to-D converters in last generation CMOS technologies.

16 xviii Preface The first prototype is a wideband cascade with dual quantization of 1 and 4 bits, which has been implemented in a m standard digital CMOS process with epitaxial (low-ohmic, conductive) substrate. The modulator operates with an oversampling ratio of 16 and exhibits a differential full-scale range of 4V using the 3.3-V nominal supply voltage. It achieves an effective resolution of 13bit at 4MS/s and consumes 78mW, while operated at 64-MHz internal clock frequency. The second design is conceived to be incorporated to a CPE modem for ADSL and ADSL+ in a 2.5-V m CMOS process. The selected topology is a cascade with quantization of 1 and 3 bits, which operates with an oversampling ratio of 32 or 16, and exhibits a differential full-scale range of 3V. The prototype achieves an effective resolution of 13.8bit at 2.2MS/s and 12.7bit at 4.4MS/s, with a power consumption of 66mW, while operating with a sampling frequency of 70.4MHz. The book also presents the design of a third prototype to be included in an automotive sensor interface in a 3.3-V m CMOS process. The modulator topology is a 2-1 single-bit cascade that can be digitally programmed to yield four gain values 0.5, 1, 2, and 4 in order to obtain a better fitting to the different sensor outputs. This prototype has been developed in the frame of the EU ESPRIT Project (TAMES-2), whose objective is to improve the industrial testability of high-resolution A-to-D interfaces embedded in SoCs. The modulator achieves an effective resolution of 18bit at 40kS/s and consumes 14.7mW, while operated at 5.12-MHz internal clock frequency. The three prototypes presented in the book avoid the use of calibration techniques, non-standard transistors, or on-chip voltages larger than the nominal supply, and their performances are competitive to the current state of the art. The contents of the book are organized in five chapters. Chapter 1 presents an introduction to A-to-D converters, showing the principles of operation, the basic architectures, and the ideal performance of modulators. Topologies for their practical implementation are introduced and their pros and cons are discussed. The state of the art in low-pass modulators in CMOS technologies is then revised, showing existing trends in present designs. Chapter 2 is dedicated to the exhaustive analysis of the main non-idealities that affect the performance of modulators. System considerations, behavioral models, and closed expressions are obtained for the impact of the different non-idealities, which can be used as estimable guidelines for practical implementation of modulators. Chapters 3 and 4 describe the design of the two modulators intended for broadband applications, whereas Chapter 5 describes the design of the modulator with programmable gain for automotive sensor interfaces. The topology selection, the requirements of the building blocks, and their design at the transistor level are deeply

17 Preface xix discussed. The measured performance for the prototypes is presented and compared with the state-of-the-art modulators. The considerations presented through the book for the design of cascade modulators in deep-submicron CMOS are extended in Appendixes A and B. Appendix A proposes a family of cascade modulators that is easily expandible to high order, while preserving a low systematic loss of resolution and a high overload level. An analytical method to estimate its power consumption is presented in Appendix B.

18 xx Preface References to the Preface [Abidi95] A.A. Abidi, Low-Power Radio-Frequency ICs for Portable Communications. Proceedings of the IEEE, vol. 83, pp , April [Adams86] [Boser88] [Bran91a] [Bran91b] B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation Analog-to-Digital Converters. IEEE Journal of Solid-State Circuits, vol. 23. pp , December B. Brandt, D.W. Wingard, and B.A. Wooley, Second-Order Sigma-Delta Modulation for Digital-Audio Signal Acquisition. IEEE Journal of Solid- State Circuits, vol. 23. pp , April B.P. Brandt and B.A. Wooley, A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2-MHz A/D Conversion. IEEE Journal of Solid-State Circuits, vol. 26, pp , December R.W. Adams, Design and Implementation of an Audio 18-bit Analog- to-digital Converter Using Oversampling Techniques. Journal of Audio Engineering Society, vol. 34, pp , March [Broo97] T.L. Brooks, D.H. Robertson, D.F. Kelly, A. Del Muro, and S. W. Harston, A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 db SNR. IEEE Journal of Solid-State Circuits, vol. 32, pp , December [Bult00] [Candy85] [Feld98] [Fuji00] [Gagn97] [Geer99] [Geer00] [Guil01] K. Bult, Analog Design in Deep Sub-Micron CMOS. Proc. of the IEEE European Solid-State Circuits Conference, pp , J.C. Candy, A Use of Double Integration in Sigma-Delta Modulation. IEEE Transactions on Communications. vol. 33, pp , March A.R. Feldman, B.E. Boser, and P.R. Gray, A 13-Bit, 1.4-MS/s Sigma-Delta Modulator for RF Baseband Channel Applications. IEEE Journal of Solid- State Circuits, vol. 33, pp , October I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S.-L. Chan, A 90-dB SNR 2.5-MHz Output-Rate ADC Using Cascaded Multibit Delta-Sigma modulation at 8x Oversampling Ratio. IEEE Journal of Solid- State Circuits, vol. 35, pp , December M. Gagnaire, An Overview of Broad-band Access Technologies. Proceedings of the IEEE, vol. 85, pp , December Y. Geerts, A. Marques, M. Steyaert, and W. Sansen, A 3.3-V, 15-bit, Delta- Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL Applications. IEEE Journal of Solid-State Circuits, vol. 34, pp , July Y. Geerts, M. Steyaert, and W. Sansen, A High-Performance Multibit CMOS ADC. IEEE Journal of Solid-State Circuits, vol. 35, pp , December J. Guilherme, P. Figueredo, P. Azevedo, G. Minderico, A. Leal, J. Vital, and J. F ranca, A Pipeline 15-b 10Msample/s Analog-to-Digital Converter for ADSL Applications. Proc. of the IEEE International Symposium on Circuits and Systems, vol. 1, pp , May 2001.

19 Preface xxi [Inose62] [Malo01] [Marq98] [Mayes96] [Mede99] [Mori00] [Nors97] [Opris00] H. Inose, Y. Yasuda, and J. Murakami, A Telemetering System by Code Modulation - Modulation. IRE Transactions on Space Electronics and Telemetry, vol. 8, pp , September F. Maloberti, Analog Design for CMOS VLSI Systems. Kluwer Academic Publishers, A.M. Marques, V. Peluso, M.S.J. Steyaert, and W. Sansen, A 15-b Resolution 2-MHz Nyquist Rate ADC in a 1- m CMOS Technology. IEEE Journal of Solid-State Circuits, vol. 33, pp , July M.K. Mayes and S.W. Chin, A 200 mw, 1 Msample/s 16-b Pipelined A/D Converter with On-Chip 32 b Microcontroller. IEEE Journal of Solid-State Circuits, vol. 31, pp , December F. Medeiro, B. Perez-Verdú, and A. Rodríguez-Vázquez, A 13-bit, 2.2-MS/s, 55-mW Multibit Cascade Modulator in CMOS 0.7- m Single-Poly Technology. IEEE Journal of Solid-State Circuits, vol. 34, pp , June J.C. Morizio, M. Hoke, T. Kocak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, M.H. Hood, G. Lynch, H. Kondoh, T. Kumamoto, T. Okuda, H. Noda, M. Ishiwaki, T. Miki, and M. Nakaya, 14-bit 2.2-MS/s Sigma-Delta ADC s. IEEE Journal of Solid-State Circuits, vol. 35, pp , July S.R. Norsworthy, R. Schreier, and G.C. Temes (Editors), Delta-Sigma Data Converters: Theory, Design and Simulation. IEEE Press, I.E. Opris, B.C. Wong, and S.W. Chin, A Pipeline A/D Converter Architecture with Low DNL. IEEE Journal of Solid-State Circuits, vol. 35, pp , February [OptE91] F. Op t Eynde, G.M. Yin, and W. Sansen, A CMOS Fourth-order 14b 500ksample/s Sigma-delta ADC Converter. Proc. of IEEE International Solid- State Circuit Conference, pp , [Plas94] R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, [Raza95] B. Razavi, Principles of Data Converter System Design. IEEE Press, [Rivo03] [Sign90] [Yama94] [Yin94] R. Rivoir, Nyquist-rate Converters: An Overview, Chapter 1 in CMOS Telecom Data Converters (A. Rodríguez-Vázquez, F. Medeiro, E. Janssens, Editors). Kluwer Academic Publishers, B.P. del Signore, D.A. Kerth, N.S. Sooch, and E.J. Swanson, A Monolithic 20-b Delta-Sigma A/D Converter. IEEE Journal of Solid-State Circuits, vol. 25, pp , December K. Yamamura, A. Nogi, and A. Barlow, A low power 20 bit instrumentation delta-sigma ADC. Proc. of the IEEE Custom Integrated Circuits Conference, pp , G. Yin and W. Sansen, A High-Frequency and High-Resolution Fourth-Order A/D Converter in BiCMOS Technology. IEEE Journal of Solid-State Circuits, vol. 29, pp , August 1994.