Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

Transcription

1 Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

2 Alonso Morgado Rocío del Río José M. de la Rosa Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio 2123

3 Alonso Morgado Instituto de Microelectrónica de Sevilla Centro Nacional de Microelectrónica IMSE-CNM (CSIC/Universidad de Sevilla) Parque Tecnológico de la Cartuja C/Américo Vespucio s/n Sevilla, Spain Rocío del Río Instituto de Microelectrónica de Sevilla Centro Nacional de Microelectrónica IMSE-CNM (CSIC/Universidad de Sevilla) Parque Tecnológico de la Cartuja C/Américo Vespucio s/n Sevilla, Spain José M. de la Rosa Instituto de Microelectrónica de Sevilla Centro Nacional de Microelectrónica IMSE-CNM (CSIC/Universidad de Sevilla) Parque Tecnológico de la Cartuja C/Américo Vespucio s/n Sevilla, Spain ISBN e-isbn DOI / Springer New York Dordrecht Heidelberg London Library of Congress Control Number: Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (

4 A Ania A Juanan y a Mario A Visi, José Manuel, María y Jaime A nuestros padres

5 Preface This book represents a contribution to the design of sigma-delta ( ) modulators intended for the A/D conversion in multi-standard multi-mode wireless transceivers, implemented in nanometer CMOS technologies. In these transceivers, ADCs are key parts because they need to operate with a wide spread of their specifications; namely, effective resolution and signal bandwidth. modulators are very suited for the implementation of reconfigurable ADCs in highly integrated transceivers. On the one hand, the key principles of modulators (oversampling and noise shaping) determine the dynamic range of the ADC, so that their adjustment contributes to adapt the converter performance to different specifications with large hardware reuse. On the other, both principles make them robust with respect to non-idealities of an integrated implementation. In spite of the advantages mentioned above, the design of nanometer CMOS ADCs is not easy, specially when considering adaptability and reconfigurability features. It involves a number of practical issues and trade-offs at both architectural and circuit level that must be taken into account for optimizing performance in terms of power dissipation (device portability and autonomy), silicon area (cost) and time-to-market deployment. In this context, the work in this book presents innovative solutions for the implementation of flexible modulators intended for the next generation of wireless hand-held mobile terminals, implemented as a SoC in nanometer CMOS processes. Novel adaptive and reconfigurable modulator topologies based on the combination of resonation, unity signal transfer function, and a new type of cascade with extra inter-stage feedback loops and simplified digital cancellation logic are presented. These strategies allow to reduce the requirements of the embedded amplifiers in terms of finite DC gain, non-linearity and output swing. This makes them very suited for the implementation of low-voltage low-power wideband ADCs. At the circuit level, different strategies are applied to adapt the performance of the modulators to the different sets of specifications with adaptable power consumption. A number of architectures, circuit techniques and design procedures presented in this book are demonstrated through the design, implementation and experimental characterization of three IC prototypes. The first one implemented in a 130-nm CMOS technology consists of an expandable cascade topology that comprises vii

6 viii Preface a 2nd-order front-end stage followed by 1st-order stages, with the last one being switchable and also incorporating multi-bit quantization. The chip reconfigures the modulator loop filter order, the sampling frequency and the number of bits of the internal (back-end) quantizer, and scales the power consumption of internal building blocks in order to adapt the performance to the specifications of 2G/3G standards, considering a direct conversion receiver. Measurement results show a correct operation for GSM/Bluetooth/WCDMA standards, featuring a dynamic range of 86.7/81.0/63.3 db for signal bandwidths of 200 khz/1 MHz/4 MHz, respectively. The power consumption is 25.2/25.0/44.5 mw, of which 11.0/10.5/24.8 mw corresponds to the analog part of the circuit. The second chip implemented in a 90-nm CMOS process consists of a twostage (2 2) topology with 3-level quantization and unity signal transfer function in both stages. The chip reconfigures its loop filter, clock frequency and scales power according to the required specifications for different standards included in B3G wireless telecom, covering: GSM, Bluetooth, GPS, UMTS, DVB-H and WiMAX. Measurement results feature a dynamic range of 78/70/71.5/66/62/52 db within bandwidths of 100 khz/500 khz/1 MHz/2 MHz/4 MHz/10 MHz, while consuming 4.6/5.35/6.2/8/8/11 mw, respectively. The third chip is a cascade made up of unity-stf stages. Similarly to the second chip, a 1.2-V 90-nm CMOS technology is employed. The chip can reconfigure its loop filtering order from 6 to 4 or 2 by switching off one or two stages in the cascade, respectively. The quantization in each stage can be selected to 3 or 5 levels. Every stage can work concurrently or as part of a cascade, so this modulator can process up to three standards in parallel. The employed architecture incorporates programmable resonation in the last two stages. The bias currents of main modulator building blocks are adjustable on-chip. Also, the sampling frequency can be adapted to the requirements of each operation mode. Experimental characterization of this chip indicates a correct operation for most of the reconfiguration techniques implemented; namely, adaptation of the in-loop filtering order, programmability of the bias currents in the modulator building blocks, variation of the internal quantization and concurrency. The work in this book demonstrates the feasibility of using modulators for the efficient implementation of multi-standard telecom systems and shows the way for the practical deployment of the software defined radio paradigm. Sevilla March 2011 Alonso Morgado Rocío del Río José M. de la Rosa

7 Acknowledgments The authors would like to express their gratitude to Prof. Ángel Rodríguez-Vázquez, Prof. Belén Pérez-Verdú, Dr. Fernando Medeiro (IMSE-CNM, CSIC/University of Sevilla), Prof. Maurits Ortmanns (University of Ulm), Dr. Ana Rusu (Royal Institute of Technology, KTH, Stockholm), Dr. Geert Van der Plas and Dr. Julien Ryckaert (IMEC, Leuven), for the review of this text. Specially, the authors wish to thank Dr. Geert Van der Plas and Dr. Julien Ryckaert for their valuable inputs and help in the design of the second chip presented in Chap. 5 of this book, and also to Mr. José G. García-Sánchez, Mr. Luis I. Guerrero-Linares and Mr. Sohail Asghar for their support with the design and layout of the third prototype described in Chap. 6. This work was supported in part by the Spanish Ministry of Innovation and Science (with support from the European Regional Development Fund) under Contract TEC C02-01/MIC and Contract TEC /MIC, and in part by the Regional Ministry of Innovation, Science and Enterprise under Contract TIC ix

8 Table of Contents 1 Introduction Overview of Wireless Standards and Mobile Systems Towards 4G Mobile Terminals Circuits and Systems for 4G: Challenges and Innovations Multi-Standard Wireless Transceivers Flexible CMOS Analog Baseband Circuits for 4G Telecom Channel Selection Programmable Baseband Filtering Reconfigurable ADCs for SDR-Based Mobile Terminals ADCs: Basic Concepts, Topologies and State of the Art Fundamentals of the A/D Conversion Sampling Quantization White Noise Approximation of Quantization Error Oversampling Quantization Noise Shaping Basics of A/D Converters Signal Processing in a Modulator Performance Metrics of Modulators Ideal Performance of Modulators Classification of Modulators Single-Loop Architectures Second-Order Modulator High-Order Modulators Cascade Architectures Multi-bit Architectures Impact of DAC Non-linearities Dynamic Element Matching Dual-Quantization Techniques xi

9 xii Table of Contents 2.7 State of the Art in ADCs Summary New Cascade Modulators for the Next Generation of Wireless Telecom Strategies for Efficient Cascade Ms in Multi-Mode Applications Modulator Order Reconfiguration and Concurrency Expandable Cascade Ms Unity-STF Cascade Architectures Previously Reported Resonation-Based Ms SMASH Architectures Novel Cascade Architectures Based on Previous Strategies Proposed Resonation-Based Architectures Novel Unity-STF SMASH-Based Architecture Novel SMASH Ms with Resonation Practical Timing Issues of the Novel Architectures Implementation and Timing of USTF Ms Timing Problems in Unity-STF Cascade Ms Alternative SMASH- and Resonation-Based Architectures Summary A 130-nm CMOS Reconfigurable Cascade SC M for GSM/BT/UMTS Receiver Considerations and ADC Specifications Selection of the Modulator Architecture Expandable Cascade Architecture Exploration of Cascade Candidates Final Modulator Architecture Selection SC Implementation of the Reconfigurable Modulator Electrical Design of the Modulator Blocks Amplifiers Capacitors Switches Comparators Multi-bit Quantizer Auxiliary Blocks Complete Modulator Simulation Results Layout and Area Distribution Experimental Results Summary

10 Table of Contents xiii 5 A 1.2-V 90-nm CMOS Reconfigurable 2-2 Cascade SC M for GSM/BT/GPS/UMTS/DVB-H/WiMAX Modulator Architecture Architecture Selection System-Level Parameters Modulator In-Loop Coefficients Initial Modulator Sizing SC Implementation and Related Issues Practical Implementation of Analog Adders Timing High-Level Synthesis Electrical Design of the Building Blocks Amplifiers Capacitors Switches Comparators A/D/A Conversion Clock Phase Generator Bias Current Adaptation Common-Mode Generation Layout and Prototyping PCB Experimental Results Timing Capturing Issue Test Set-Up and Experimental Results Summary A 1.2-V 90-nm CMOS Adaptive Concurrent Resonation-Based Cascade M for SDR Architecture and Strategies for Flexibility Architecture Modulator Order Reconfigurability and Concurrency Resonation Strategies Summary of All Flexible Strategies SC Implementation Implementation of Reconfiguration Strategies at Circuit Level Adaptability and Concurrency at Circuit Level Implementation of Resonation Reconfiguration Implementation of Multi-rating Control Signals Generation Electrical Design: Reuse and Improvements of Previously Designed Building Blocks Amplifiers Comparators

11 xiv Table of Contents Switches Clock Phase Generators DAC and ROM Layout, PCB and Test Set-up Layout PCB Test Set-up Experimental Results Reconfiguration of the Internal Quantization Adjustable Modulator Order Concurrency Adaptive Biasing Summary Performance of the Prototypes and Comparison with the State of the Art Performance of the Designed Prototypes Comparison with the State of the Art Appendix A Study of Optimum Resonation Appendix B Design of Electrical Blocks for the Practical Implementation of SMASH Ms References Index

12 List of Abbreviations 1G 2G 3G 4G M A/D, A-to-D AAF AC ADC AMPS B3G BE BPSK BT BW CDMA CMFB CMOS CPE CPU CQFP CR CT D/A, D-to-A DAC db dbfs DC DCL DCR First Generation Second Generation Third Generation Fourth Generation Sigma-Delta Sigma-Delta Modulator Analog-to-Digital Anti-Aliasing Filter Alternating Current Analog-to-Digital Converter Advanced Mobile Phone System Beyond 3G Backward Euler Binary Phase Shift Keying Bluetooth Bandwidth Code Division Multiple Access Common-Mode Feedback Complementary Metal Oxide Semiconductor Customer Premises Equipment Central Processing Unit Ceramic Quad Flat Pack Cognitive Radio Continuous-Time Digital-to-Analog Digital-to-Analog Converter Decibels Decibels Full Scale Direct Current Digital Cancellation Logic Direct Conversion Receiver xv

13 xvi List of Abbreviations DEM DFF DNL DOR DR DRC DSP DT DUT DVB-H DWA EDGE ENOB ESD FDD FDMA FE FFT FIR FM FoM FS GB GMSK GPRS GPS GSM HiperLAN2 HD IBE IC IF IIR ILA INL IO LNA LO LPF LSB LTE MASH MiM MIMO Dynamic Element Matching D Flip-Flop Differential Non-Linearity Digital Output Rate Dynamic Range Design Rule Checking Digital Signal Processing Discrete-Time Device Under Test Digital Video Broadcasting Handheld Data Weighted Averaging Enhanced Data-rates for Global Evolution Effective Number Of Bits Electrostatic Discharge Frequency Division Duplex Frequency Division Multiple Access Forward Euler Fast Fourier Transform Finite Impulse Response Frequency Modulation Figure of Merit Full Scale Gain-Bandwidth Product Gaussian Minimum Shift Keying General Packet Radio Service Global Positioning System Global System for Mobile-Communications High performance radio Local Area Network Harmonic Distortion In-Band Error Integrated Circuit Intermediate Frequency Infinite Impulse Response Individual Level Averaging Integral Non-Linearity Input/Output Low-Noise Amplifier Local Oscillator Low-Pass Filter Least Significant Bit Long Term Evolution Multi-Stage Noise Shaping Metal-insulator-Metal Multiple Input Multiple Output

14 List of Abbreviations xvii MoM MOS MOSFET MSB NMOS NTF OFDM Opamp OS OSR OTA PCB PDF PDM PGA PLL PMOS PSD QAM QFP QPSK QoS RAM RF ROM S/H SAW SC SDR SFDR SI SMASH SNR SNDR SPR SoC SR STF TDMA THD UMTS USTF UWB VLSI Metal-oxide-Metal Metal-Oxide-Semiconductor Metal-Oxide-Semiconductor Field Effect Transistor Most Significant Bit N-channel MOS Noise Transfer Function Orthogonal Frequency Division Multiplexing Operational Amplifier Output Swing Oversampling Ratio Operational Transconductance Amplifier Printed Circuit Board Probability Density Function Pulse-Density Modulated Programmable Gain Amplifier Phase-Locked Loop P-channel MOS Power Spectral Density Quadrature Amplitude Modulation Quad Flat Pack Quadrature Phase Shift Keying Quality of Service Random Access Memory Radio Frequency Read-Only Memory Sample-and-Hold Surface Acoustic Wave Switched-Capacitor Software Defined Radio Spurious-Free Dynamic Range Switched-Current Sturdy Multi-Stage Noise Shaping Signal-to-Noise Ratio Signal-to-(Noise+Distortion) Ratio Serial-to-Parallel Register System-on-Chip Slew-Rate Signal Transfer Function Time Division Multiple Access Total Harmonic Distortion Universal Mobile Telecommunications System Unity Signal Transfer Function Ultra-Wide Band Very Large Scale of Integration

15 xviii Vpd Vpp WCDMA WiMAX WLAN WMAN List of Abbreviations Differential peak-to-peak Voltage Peak-to-peak Voltage Wideband Code Division Multiple Access Worldwide interoperability for Microwave Access Wireless Local Area Network Wireless Metropolitan Area Network