Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/57

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1 Gábor C. Temes School of Electrical Engineering and Computer Science Oregon State University 1/57

2 Switched-Capacitor Circuit Techniques ORIGIN : "SC" replacing "R"; 1873, James Clerk Maxwell, "A TREATISE ON ELECTRICITY AND MAGNETISM", PP IC Context: 1972, D. L. Fried. Low-, high- and bandpass (n-path!) SC filters. Application as ADCs: 1975, Mccreary and Gray. 1977, UC Berkeley, BNR, AMI, U. of Toronto, Bell labs., UCLA, etc.: Design of high-quality SC filters and other analog blocks. Liou, Brglez, Tsividis et al.: CAD tools for SC. temes@ece.orst.edu 2/57

3 Switched-Capacitor Circuit Techniques BASIC PRINCIPLE: Signal entered and read out as voltages, but processed internally as charges on capacitors. Since CMOS reserves charges well, high SNR and linearity are possible. IMPORTANCE: Replaces absolute accuracy of R & C (10-30%) with matching accuracy of C ( %); Can realize accurately and tunably large RC time constants; Can realize high-order circuits with high dynamic range; Allows medium-accuracy data conversion without trimming; Can realize large mixed-mode systems for telephony, audio, aerospace, physics etc. applications on a single CMOS chip. Tilted the MOS VS. BJT contest decisively. temes@ece.orst.edu 3/57

4 Switched-Capacitor Circuit Techniques COMPETING TECHNIQUES: Switched-current circuitry: Can be simpler and faster, but achieves lower dynamic range & much more THD. Needs more power. Can use basic digital technology; now SC can too! Continuous-time filters: much faster, less linear, less accurate, lower dynamic range. FUTURE: Continues to be bright in low & medium-speed applications: lowpower, low-voltage, digital CMOS operation possible. 4/57

5 LCR Filters to Active-RC Filters 5/57

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8 Typical Applications of SC Technology (1) Line-Powered Systems: Telecom systems (telephone, radio, video, audio) Digital/analog interfaces Smart sensors Instrumentation Neural nets. Music synthesizers 8/57

9 Typical Applications of SC Technology (2) Battery-Powered Micro-Power Systems: Watches Calculators Hearing aids Pagers Implantable medical devices Portable instruments, sensors Nuclear, biomedical, environmental array sensors (micro-power, may be battery powered). 9/57

10 New SC Circuit Techniques To improve accuracy: Oversampling, noise shaping Dynamic matching Digital correction Self-calibration Offset/gain compensation To improve speed, selectivity: GaAs technology BiCMOS technology N-path, multirate circuits 10/57

11 Typical SC Stages Amplifiers: programmable, precision, AGC, buffer, driver, sense amplifiers Filters S/H and T/H stages MUX and demux stages PLLs VCOs Modulators, demodulators Precision comparators Attenuators ADC/DAC blocks 11/57

12 Active - RC Integrator Can be transformed by replacing R1 by an SC branch. temes@ece.orst.edu 12/57

13 SC Integrator (Analog Accumulator) Stray insensitive version: 13/57

14 SC Integrator (Analog Accumulator) 14/57

15 Low-Q Tow-Thomas SC Biquad (1) 15/57

16 Low-Q SC Biquad (2) 16/57

17 Low-Q SC Biquad (3) Approximate design equations for ω 0 T << 1: >1, temes@ece.orst.edu 17/57

18 Low-Q SC Biquad (4) For b 0 = 1, matching coefficients: Preliminary C i values. Scaling to follow! temes@ece.orst.edu 18/57

19 High-Q Biquad (1) Figure (a) High Q switched-capacitor biquad; (b) clock and signal waveform temes@ece.orst.edu 19/57

20 High-Q Biquad (2) Approximate design equations : temes@ece.orst.edu 20/57

21 Exact equations: High-Q Biquad (3) For b 2 = 1, matching gives C spread & sensitivities reasonable even for high Q & f c /f o, since C 2, C 3, C 4 enter only in products temes@ece.orst.edu 21/57

22 Linear Section (1) Original φ i : pole/zero btw 0 & 1. Parenthesized: zero > 1. For differential circuit no restrictions. temes@ece.orst.edu 22/57

23 Linear Section (2) To achieve negative zero or pole, at. C st effect is usually small. Nonlinearity! Stray insensitive branch (cannot be used as feedback branch!). Figure Switched-capacitor linear section: (a) complete circuit; (b) and (c) alternative input branches. temes@ece.orst.edu 23/57

24 Cascade Design (1) 24/57

25 Cascade Design (2) Easy to design, layout, test, debug, Passband sensitivities moderate ; db/% in passband. Stopband sensitivites good. Pairing of num. & denom., ordering of sections affect S/N, element spread and sensitivities. Rules of thumb or search for optimum. (Put high-q pole in middle, aim for flat gain in each stage.) (See Sedra & Brackett book.) temes@ece.orst.edu 25/57

26 Cascade Design (3) Choose Cascade Order The next decision is to order the biquads (and maybe a first-order term) in the situation to best meet chip specifications. Many practical factors influence the optimum ordering. A few examples (John Khouri, personal communication): 1. Order the cascade to equalize signal swing as much as possible for dynamic range considerations 2. Choose the first biquad to be a lowpass or bandpass to reject high frequency noise, to prevent overload in the remaining stages. 3. lf the offset at the filter output is critical, the last stage should be a highpass or bandpass to reject the DC of previous stages temes@ece.orst.edu 26/57

27 Cascade Design (4) 4. The last stage should NOT in general be high Q because these stages tend to have higher fundamental noise and worse sensitivity to power supply noise 5. In general do not place allpass stages at the end of the cascade because these have wideband noise. It is usually best to place allpass stages towards the beginning of the filter. 6. If several highpass or bandpass stages are available one can place them at the beginning, middle and end of the filter. This will prevent input offset from overloading the filter, will prevent internal offsets of the filter itself from accumulating (and hence decreasing available signal swing) and will provide a filter output with low offset. 7. The effect of thermal noise at the filter output varies with ordering; therefore, by reordering several db of SNR can often be gained. (John Khouri, unpublished notes) temes@ece.orst.edu 27/57

28 Ladder Filter For optimum passband matching, for nominal V o / x ~ 0 since V o is maximum x values. x: any L or C. Use doubly-terminated LCR filter prototype, with 0 flat passband loss. State equations: temes@ece.orst.edu 28/57

29 The Exact Design of SC Ladder Filters Purpose: H a (s a ) H(z), where Then, gain response is only frequency warped. Example: State equations for V 1,I 1 &V 3 ; Purpose of splitting C 1 : has a simple z-domain realization. temes@ece.orst.edu 29/57

30 S a -domain block diagram Realization of input branch: Q in =V in /s a R s, which becomes, This relation can be rewritten in the form or, in the time domain Δq in (t n ) : incremental charge flow during t n-1 < t < t n, in SCF temes@ece.orst.edu 30/57

31 Alternative realization a. Simple, but stray sensitive: b. Stray insensitive: Hence, it remains a capacitor C 2 in the z domain. temes@ece.orst.edu 31/57

32 Central block implementation (1) Hence, it contributes a charge To the adders at the input terminals of the first and third integrators. Replacing s a with (2/T)[(z-1)/(z+1)], we get The z-transform of the incremental charge Δq(t n ), ΔQ(z), is thus which can be rewritten in the form temes@ece.orst.edu 32/57

33 Central block implementation (2) 33/57

34 Damping resistors in input & output stages (1) The input branch can be used here, but it is easier to take 34/57

35 Damping resistors in input & output stages (2) Using bandpass realization tables to obtain low-pass response gives an extra op-amp, which can be eliminated: Sixth-order bandpass filter: LCR prototype and SC realization. 35/57

36 Scaling for Optimal DR and Chip Area (1) To find voltage swings, compute histograms or frequency responses. To modify V o kv o ; Y i /Y f ky i /Y f i. Hence, change Y f to Y f /k or Y i to ky i. (It doesn't matter which; area scaling makes the results the same.) To keep all output currents unchanged, also Y a Y a /k, etc. Noise gain : temes@ece.orst.edu 36/57

37 Scaling for Optimal DR and Chip Area (2) Hence,. The output noise currents are also divided by k, due to Y a = Y a /k, etc. Hence, the overall output noise from this stage changes by a factor where : the signal gain. temes@ece.orst.edu 37/57

38 Scaling for Optimal DR and Chip Area (3) The output signal does not change, so the SNR improves with increasing k. However, the noise reduction is slower than 1/k, and also this noise is only one of the terms in the output noise power. If V o > V DD, distortion occurs, hence k k max is limited such that Y o saturates for the same V in as the overall V out. Any k > k max forces the input signal to be reduced by k so the SNR will now decrease with k. Conclusion: k max is optimum. temes@ece.orst.edu 38/57

39 Scaling of SCF's. (1) Purposes : effects. 1. Maximum dynamic range 2. Minimum C max / C min, C / C min 3. Minimum sens. to op-amp dc gain 1. Dynamic range Opamps have eq. input noise v 2 n, max. linear range V max. For optimum dynamic range V in max / V in min, each opamp should have the same V imax (f), so they all saturate at the same V in max. Otherwise, the S/ N of the op-amp is not optimal. temes@ece.orst.edu 39/57

40 Scaling of SCF's. (2) To achieve V 1 max = V 2 max = = V out max, amplitude scaling: temes@ece.orst.edu 40/57

41 Scaling of SCF's. (3) Multiply h(z)& g 1,2,3 by k i ; then Y i becomes Y i /k i, but ΔQ 1,2,3 will not change. Choose k i = V i max / V out max. Since g & h are proportional to the C j in the branch, multiply all C j connected or switched to the output of opamp i by k i! temes@ece.orst.edu 41/57

42 Scaling of SCF's. (4) 2. Minimum C max /C min If all f n (z) & h(z) are multiplied by the same l i : will not change. Choose l i = C min / C i min where C i min is the smallest C connected to the input of op-amp i, and C min is the smallest value of cap. permitted by the technology (usually 0.1 pf C min 0.5 pf for strayinsensitive circuits). Big effect on C max / C min! 3. Sensitivities The sens. of the gain to C k remain unchanged by scaling; the sens. to op-amp gain effects are very much affected. Optimum dynamic-range scaling nearly optimal for dc gain sens. as well. temes@ece.orst.edu 42/57

43 Scaling of SCF's. (5) 43/57

44 Scaling of SCF's. (6) GAIN / db FREQUENCY / Hz temes@ece.orst.edu 44/57

45 Scaling of SCF's. (7) GAIN / db FREQUENCY / Hz temes@ece.orst.edu 45/57

46 Scaling of SCF's. (8) GAIN / db FREQUENCY / Hz temes@ece.orst.edu 46/57

47 SC Filters in Mixed-Mode System Two situations; example: Situation 1: Only the sampled values of the output waveform matter; the output spectrum may be limited by the DSP, and hence V RMS,n reduced. Find V RMS from charges; adjust for DSP effects. Situation 2: The complete output waveform affects the SNR, including the S/H and direct noise components. Usually the S/H dominates. Reduced by the reconstruction filter. temes@ece.orst.edu 47/57

48 Direct-Charge-Transfer Stage (1) Advantages: Opamp does not participate in charge transfer no slewing distortion, clean S/H output waveform. Finite DC gain Ao introduces only a scale factor K = 1/[1+1/A o ]. Feedback factor = 1. temes@ece.orst.edu 48/57

49 Direct-Charge-Transfer Stage (2) Analysis gives where is the ideal lowpass filter response. Applications: SC-to-CT buffer in smoothing filter for D-S DAC (Sooch et al., AES Conv., Oct. 1991) DAC + FIR filter + IIR filter (Fujimori et al., JSSC, Aug. 2000). temes@ece.orst.edu 49/57

50 Double Sampled Data Converter (1) 50/57

51 Double Sampled Data Converter (2) -DAC +DAC 51/57

52 Double Sampled Data Converter (3) 52/57

53 Double Sampled Data Converter (4) 53/57

54 Double Sampled Data Converter (5) DAC 54/57

55 Double Sampled Data Converter (6) Mismatch in C 1 & C 2 affects only CM charge, which is effectively rejected by differential structure. No extra factor enters the loop transfer function Modulator stability and coefficients are preserved. temes@ece.orst.edu 55/57

56 Double Sampled Data Converter (7) [1] K. Lee et al., EL 2007 [2] D. Senderowicz et al., JSSC nd order, OSR=64, 3-bit quantizer and 0.1% DAC mismatch (MATLAB simulation) temes@ece.orst.edu 56/57

57 Parallel Pipeline A/D Converter 57/57

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/25

Gábor C. Temes. School of Electrical Engineering and Computer Science Oregon State University. 1/25 Gábor C. Temes School of Electrical Engineering and Computer Science Oregon State University temes@ece.orst.edu 1/25 Noise Intrinsic (inherent) noise: generated by random physical effects in the devices.