New Results on Opto-Electronics

Transcription

1 New Resuts on Opto-Eectronics K.K. Gan The Ohio State University June 18, 2002 K.K. Gan ATLAS Pixe Week 1

2 Outine Introduction VCSEL Anneaing Pan for Opto-board IV Resut on VDC/DORIC-I3 Improvements in VDC/DORIC-I4 Summary K.K. Gan ATLAS Pixe Week 2

3 VCSEL Driver Chip (VDC): P convert LVDS signa into singe-ended signa appropriate to drive VCSEL Digita Opto-Receiver Integrated Circuit (DORIC): P Introduction decode cock and command signas from PIN diode K.K. Gan ATLAS Pixe Week 3

4 Opto-eectronics Team The Ohio State University: P Kregg Arms, K.K. Gan, Mark Johnson, Harris Kagan, Richard Kass, Chuck Rush, Rouben Ter-Antonian, Michae Zoeer Siegen University: P Adrian Nicuae, Michae Kraemer, Joachim Hausmann, Martin Hoder, Micha Ziokowski K.K. Gan ATLAS Pixe Week 4

5 VCSEL Anneaing of 20 ma AC vs DC Mrad Power (mw) ma AC 20 ma DC 5.0 Mrad 15.5 Mrad 22.1 Mrad Mrad Hours AC and DC currents produce simiar anneaing 36.8 Mrad K.K. Gan ATLAS Pixe Week 5

6 Opto-Board Prototype IV design for 4-channe VDC/DORIC-I4 contain 7 opto-inks for use in barre and disk use 8-channe opto-packs use 80-pin connector satisfy PP0 constraints design for BeO but tested in FR4 u FR4 submission next week u BeO submission in Fa 2002 K.K. Gan ATLAS Pixe Week 6

7 Opto-Board Prototype IV K.K. Gan ATLAS Pixe Week 7

8 VDC-I3 Bright Currents vs I set I (ma) 10 5 VDC-I1O (simuation) VDC-I2 (simuation) VDC-I3 (simuation) VDC-I1O VDC-I1D VDC-I2 VDC-I I set (ma) turning over at high I set is due to 10 W in series used in measurement dependence of bright current vs I set is as expected K.K. Gan ATLAS Pixe Week 8

9 Current Consumption of VDC-I I (ma) VDC-I1O VDC-I1O (simuation) VDC-I2 VDC-I2 (simuation) VDC-I3 VDC-I3 (simuation) VDC-I4 (simuation) VDC-I1D I set (ma) VDC-I3 current consumption is consistent with expectation VDC-I3 consumes ess current than VDC-I2 K.K. Gan ATLAS Pixe Week 9

10 Rise/Fa Time vs I set Rise Time Fa Time I2 1.2 I3 1.2 Time (nsec) 0.8 I2 Time (nsec) 0.8 I I set (ma) I set (ma) rise times somewhat above spec. (1 ns) fa times is better than VDC-I2 K.K. Gan ATLAS Pixe Week 10

11 Cock Duty Cyce vs I set Duty Cyce (%) ma I3 I I set (ma) cock duty cyce coser to 50% than VDC-I2 K.K. Gan ATLAS Pixe Week 11

12 DORIC-I3 first impementation of singe-ended pre-amp + PIN bias votage (up to 10 V) moved off die PIN current threshod for no bit errors are ow: u ma for 7 inks on opto-board with SCT opto-packs u ma for 4 inks on opto-board with PIN array opto-packs u no need to bond the dummy channe in pre-amp for noise canceation P confirmed with HSPICE simuations K.K. Gan ATLAS Pixe Week 12

13 Jitter of Recovered Cock in DORIC-I3 0.6 Threshod 40 ma 200 ma Cock Jitter (nsec) Chip cock jitter is typicay ~ 150 ps cock jitter decreases with higher PIN current K.K. Gan ATLAS Pixe Week 13

14 Duty Cyce of Recovered Cock in DORIC-I3 60 Duty Cyce (%) Chip duty cyce is cose to 50% K.K. Gan ATLAS Pixe Week 14

15 Period of Recovered Cock in DORIC-I Period (nsec) Chip cock period is very cose to 25 ns K.K. Gan ATLAS Pixe Week 15

16 Status of VDC-I4 first impementation for use with common cathode VCSEL array impemented a improvements presented at February Pixe Week u oversight in impementing faster rise/fa time + maximum bright current is 18 ma instead of 22 ma + to be fixed in next submission with arger transistors submitted both singe and four channes as MPW run in Apri u VDC/DORIC-I2: no increase in PIN current threshod for no bit errors when a four VDC channes are running expect dice deivery near end of June K.K. Gan ATLAS Pixe Week 16

17 Four-Channe VDC-I4 each channe individuay powered K.K. Gan ATLAS Pixe Week 17

18 Status of DORIC-I4 first impementation for use with common anode PIN array impemented the arge number of improvements presented at February Pixe Week first impementation of four-channe DORIC submitted both singe and four channes as MPW run in Apri expect dice deivery near end of June K.K. Gan ATLAS Pixe Week 18

19 Four-Channe DORIC-I4 a channes powered from singe power suppy u impement separate power for each channe in next submission? one channe contains spy circuits for probing K.K. Gan ATLAS Pixe Week 19

20 Open Dummy Channe in DORIC-I4? DORIC-I1/I2: differentia pre-amp DORIC-I3/I4: singe-ended pre-amp + add dummy channe before differentia gain stage for noise canceation Faster fast/rise time DORIC-I3: dummy channe is open + no difference in PIN current threshod for no bit errors DORIC-I4: may need to bond to dummy trace to pick up stray capacitance K.K. Gan ATLAS Pixe Week 20

21 Summary AC and DC currents produce simiar VCSEL anneaing performance of VDC/DORIC-I3 is satisfactory u principe of singe-ended pre-amp demonstrated VDC-I4 for common-cathode VCSEL array designed/submitted DORIC-I4 for common-anode PIN array designed/submitted K.K. Gan ATLAS Pixe Week 21