Using NEC Optocouplers as Gate Drivers in IGBT and Power MOSFET Applications

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1 A p p l i c at i o n Note AN 3007 Using NEC Optocouplers as Gate Drivers in IGBT and Power MOSFET Applications by Van N. Tran Staff Applications Engineer, CEL Opto Semiconductors Table 1-1 NEC Gate Driver Optocouplers for IGBT/MOSFET Part No. 1. Introduction Rising concern for environmental issues and energy savings is driving growth in the use of dynamic power control and inverters throughout the industrial, power, and home appliance markets. In the U.S. and Europe, the use of general-purpose inverters and AC servos is expanding rapidly, especially in the BRICs market. There has also been steady growth in the use of these devices in power-related fields like wind and solar generation, two markets that are expected to grow well into the future. Power semiconductors such as Insulated Gate Bipolar Transistors (IGBT) and Power MOSFETs are being used in large quantities in the inverters employed in power-related equipment in all these fields. NEC s PS9552, PS9553, PS9301 and PS are high-speed optocouplers designed specifically for gate driving these IGBTs and Power MOSFETs. Package ABSOLUTE MAXIMUM RATINGS BV VCC IO(PEAK) ICCH/ICCL IFLH tplh/tphl PWD CMH/CML (Vr.m.s.) (V) (A) (ma) (ma) (µs) (µs) (kv/µs min.) PS DIP / / /25 PS9301 SDIP / / /15 PS SSOP / / /15 PS9553 DIP / / /15 NOTES 1. Built-in UVLO function 2. Two channel version In this application note, NEC s PS9552 Insulated Gate Driver optocoupler is used as an example to describe the characteristics, the internal gate drive circuits, the external gate resistance requirements, and the details of gate driver optocoupler power dissipation in relation to the MOSFET/IGBT gate charge, based on the desired switching frequency to turn on and off the MOSFET / IGBT. 2. PS9552 Overview Figure 2-1 shows the equivalent circuit of the PS9552, an 8-pin DIP digital, high-speed optocoupler that incorporates a GaAlAs Infrared emitting diode (IRED) on the input side and a single-chip IC on the output side. A photodiode (PD), signal processing circuit, and large-current output circuit are also integrated into the device. NC ANODE CATHODE NC LED PD Shield UVLO Signal Processing Circuit Figure 2-1 PS9552 Equivalent Circuit Output Drive Circuit VCC VO VO VEE A newly developed BiCMOS process enables the lightreceiving IC to provide a large output current (IO = 2.5A max) with low operating circuit current (ICC = 2 ma typ). It also enables hightemperature operation (Ta = 100 C max). Moreover, a transparent conductive shield between the IRED and the light receiving IC provides for superb noise resistance characteristics between input and output. An Under-Voltage Lock Out (UVLO) function protects both the PS9552 and the IGBT when input signal drops or in other conditions where the IGBT could be damaged. PS9552 Features Large output peak current (IO = 2.5A max) High-speed switching (tplh/ tphl = 0.5µs max) Large operating voltage range (VCC VEE = V) Built-in UVLO (Under-Voltage Lock Out) function High instantaneous common mode rejection voltage (CMH, CML = ±15 kv/µs min.) A PS9552 Truth Table is provided on the next page. More details and a data sheet are available at

2 Output Voltage (V) Table 2-1 PS9552 Truth Table VCC VEE VCC VEE IRED Voltage Rise Voltage Drop Output (Turn-On) (Turn-Off ) (VO) OFF 0 to 30V 0 to 30V L ON 0 to 11V 0 to 9.5V L ON 11 to 13.5V 9.5 to 12V Transition ON 13.5 to 30V 12 to 30V H 3. UVLO Under-Voltage Lock Out Function When gate voltage to the IGBT drops, power dissipation increases and the IGBT heats up, which can lead to breakdown. When the VCC VEE power supply voltage to the PS9552 is insufficient to protect the IGBT, the UVLO function in the PS9552 maintains a low level Vo output to protect both devices. When the VCC VEE power supply voltage to the PS9552 is low (when the VCC VEE power supply voltage rises from 0 V), the VO output is maintained at a low level up to VUVLO+, even if the IRED +5V is on (Figure 3-1). Conversely, when the VCC VEE drops (changes to a negative voltage), the VO output is held at a high level until VUVLO, but when it drops lower than VUVLO, the VO output is lowered to the low output level even if the IRED is on. Based on this characteristic, if the VCC VEE power supply voltage of the PS9552 drops below VUVLO (9.5 to 12 V) due to some anomaly in the IGBT drive circuit, the VO output of the PS9552 becomes low level in approximately 0.6µs even if the IRED is on. Thereafter, if the VCC VEE power supply voltage exceeds VUVLO+ (11 to 13.5V), the VO output returns to high level in approximately 0.8µs (when IRED on). Figure 3-1 Output vs. Power Supply Voltage VUVLO (10.7V) UVLOHYS VUVLO+ (12.3V) Power Supply Voltage VCC VEE (V) 4. Designing an IGBT Gate Drive Circuit Using the PS9552 Electronic control of motors and AC circuits gives an intelligent power system a wide range of dynamic flexibility. Computer algorithms can take charge of systems and operate them with a fine degree of control. The basic circuit shown in Figure 4-1 below outlines the fundamental hardware connections, from the system control input on the left to the three-phase output on the right. The PS9552 as shown serves as the optical isolation and driver for one of the power transistors, shown ranked in pairs for each phase of the output. One PS9552 Isolated Gate Driver is required for each power transistor. The control system on the left is shown with a +5V supply. The output of the PS9552 is shown with +15V and 5V, which are electrically independent from the driving data input supply. The power transistors can have voltages of over +600V connected to them from a separate supply. 0.1 uf VCC = 15V VEE = 5V RG Figure 4-1 Example of an IGBT drive circuit using the PS9552. The gate resistance settings described in 4.1 and 4.2 are implemented. This Isolated Gate Driver solution enables a multi-supply system to work, providing data flow from the input to action at the output. Besides optical isolation between the power supply and power transistor, the PS9552 also provides the gate drive, eliminating the need for any additional drive components Calculation of Minimum Value of IGBT external Gate Resistance RG From the perspective of the optocoupler: The external gate resistance RG must be selected so the peak output current IOL(PEAK) of the PS9552 does not exceed its maximum rating. The minimum value of RG can be approximated using the following equation: RG {(VCC VEE) VOL}/IOL(PEAK) (Equation 4.1) VCC VEE is the difference between the power supply voltages of the PS9552. (When negative voltage is not used, VEE = 0V) +HV DC (P Line) Three Phase Output HV DC (N Line)

3 VOL equals the low-level output voltage of the PS9552. The minimum value of the external gate resistance RG is calculated based on the following conditions: VOL (V) VGS Gate Source Voltage (V) IOL(PEAK) = 2.5 A VCC VEE = 20 V VOL = 2 V Voltage drop at IOL = 2.5 A Refer to curves in Figure 4-2 VOL vs. IOL Characteristics. From Equation 4.1: RG {(VCC VEE) VOL}/IOL(PEAK) = (20 2)/2.5 = 7.2W 100 C 25 C 40 C Qgs Qgd IOL (A) Figure 4-2 VOL vs. IOL Characteristics at Temperature From the perspective of the MOSFET/IGBT Refer to the gate charge curve provided in the MOSFET or IGBT data sheet for your application. This data is required to calculate the value of total gate resistance. Typically, the gate charge curve will be similar to Figure 4-3 below: Qg VDR Peak Drive Voltage Where: Qgs = the gate- source charge Qgd = the gate-drain charge Qg = the total gate charge at which VGS equals the peak drive voltage VDR or the charge that must be applied to the gate, either to swing it by a given amount or to achieve full switching. The equation for the gate charge is: Q = C x V Where Q is the total charge The relationship between gate capacitance, switching time, and the gate driver current is: dq/dt = C x dv/dt = IG Or the current to be delivered to the gate is: IG = Qg / ts Where ts is the switching time required by the system. Since a constant voltage drive is used, the relationship between the peak value of the gate current IG and the total gate resistance RG would be: RG = VDR / IG Where RG is the sum of the driver s output impedance, the external gate resistance, and the series resistance of the gate itself, and VDR is the peak driver voltage. As a result, to match an optocoupler to a MOSFET / IGBT in a particular application, the total gate resistance calculated for the MOSFET / IGBT should be greater than the external gate resistance required by the optocoupler. 4.2 Allowable Dissipation Verification and RG Adjustment for the PS9552 The total power dissipation PT of the PS9552 is the sum of the power dissipation PE of the IRED on the input (primary) side plus the power dissipation PO of the light receiving IC on the output (secondary) side. PT = PE + PO (Equation 4.2) Power dissipation of IRED The power dissipation of the IRED can be found by using the following equation: PE = IF x VF x Duty Ratio (Equation 4.3) Q Gate Charge (nc) Figure 4-3 Gate Charge vs. Gate Source Voltage Characteristics

4 4.2.2 Power Dissipation of the Light Receiving IC Figure 4-5 Switching Loss per Cycle The power dissipation PO of the light receiving IC can be calculated as follows: PO = PO(Circuit) + PO(Switching) (Equation 4.4) PO(Circuit) = Circuit power dissipation of the light receiving IC (power dissipation by ICC.) PO(Switching) = Power output of the light receiving IC charging/discharging gate capacitance (power dissipation by IO). (1) Circuit power dissipation of the light receiving IC: ESW (µj) RG Gate Resistance ( ) 1000nC 500nC 100nC PO (Circuit) = ICC x (VCC VEE) (Equation 4.5) ICC = Circuit supply current of the light receiving IC. VCC VEE = Difference between the power supply voltages of the light receiving IC. (2) Output power of the light receiving IC charging/discharging IGBT gate capacitance. PO (Switching) = ESW (RG, Qg) x fsw (Equation 4.6) ESW (RG, Qg) = Unit power dissipation per cycle of IGBT gate capacitance charge/discharge. (Refer to Figures 4-4 and 4-5) fsw = Switching Frequency (3) Power dissipation of the light receiving IC: From equations 4.4, 4.5 and 4.6, the power dissipation of the light receiving IC is: PO = PO(Circuit) + PO(Switching) = ICC x (VCC VEE) + ESW (RG, Qg) x fsw (Equation 4.7) Allowable dissipation verification and RG adjustment of the PS9552 The power dissipation of the PS9552 is calculated using RG = 7.2W, Duty Ratio (max) = 80%, Qg = 500nC, fsw= 20kHz, IF (max) = 16mA, and TA = 85 C. From the graph in Figure 4-5, ESW = 4.8µJ(@ RG = 7.2W). VO IO (1) The power dissipation PE at the input side can be calculated from Equation 4.3: PE = IF x VF x Duty Ratio = 16 ma x 2.1 V x 0.8 = 27 mw (2) The power dissipation PO at the output side can be calculated From Equation 4.7: PO = ICC x (VCC VEE) + ESW (RG, Qg) x fsw PO = VO x IO Esw (Qg, Rg) = Esw (on) + Esw (off ) Figure 4-4 Power Dissipation Waveform during switching of PS9552 = (5mA x 20 V) + (4.8 µj x 20 khz) = 100 mw + 96 mw = 196 mw 196mW is greater than the absolute maximum rating of 178mW power dissipation at 85 C for the detector side of the PS9552 (Figure 4-6). Therefore it s NOT an allowable value. Circuit values MUST be changed to prevent damage to the device in this operating condition.

5 Detector Power Dissipation PC (mw) Total Power Dissipation PT (mw) C Ambient Temperature TA ( C) Figure 4-6 Detector Power Dissipation vs. Ambient Temperature In making your calculations, note that the Input Power Dissipation, PE, is dependent on input driving conditions. The Detector Power Dissipation, PO, is dependent on the power dissipation of the internal detector IC itself, as well as factors from the load being driven: PO = PO(Circuit) + PO (Switching) (3) Total Power Dissipation, PT, is the sum of PE + PO: PE + PO = PT 27mW mw = 223mW A PT of 223mW is less than the derated device total of 225mW at 85 C (Figure 4-7) and this appears to be an allowable figure. But even though the total may be allowed, the Detector Power Dissipation PO component of this total exceeds its allowed value, so the design s values will need to be adjusted Ambient Temperature TA ( C) +85 C Figure 4-7 Total Power Dissipation vs. Ambient Temperature (4) Adjustment of the Gate Resistance: RG The value of RG must be set so that the power dissipation of the PS9552 does not exceed the absolute maximum rating of allowable dissipation. From Equation 4.4 ( With RG = 7.2W, see Data Sheet): PO (Switching) = PO (max) PO (Circuit) = 178 mw 100 mw = 78 mw From Equation 4.6: ESW (max) = PO(Switching)/fSW = 78 mw/20 khz = 3.9 µj From Figure 4-5, when Qg = 500nC, RG = 10.2W at 3.9µJ. Selection of a suitable value for gate resistance RG is extremely important during design of the gate driving circuit as it has major impact on the performance of the IGBTs. The smaller the RG, the faster the switching speed for the IGBT input capacitance charge/discharge, and the smaller the switching loss. However, a small RG can also result in large voltage fluctuation (dv/dt) and current fluctuation (di/dt) during switching. Therefore, the gate resistance must be optimized per the IGBT s technical documents (as mentioned in section 4.1.2) and verified in actual operation. 5. PS9552 Peripheral Circuit 5.1 Layout (1) Minimize the stray capacitance between the primary and secondary sides (input-output) by designing the layout so the pattern wiring of the primary and secondary sides are not contiguous on the PCB. The wiring should also not cross on a multilayer board. (2) Minimize the effect of transient noise on the PS9552 by separating the circuit pattern of the collector/emitter of the IGBT and the DC lines (P and N lines) of the inverter circuit, as these often pass large amounts of current. Provide as much separation as possible between the LED drive circuit and the VCC and VO lines of the PS9552. (3) Position the bypass capacitor (0.1µF or higher) between the VCC VEE on the secondary (output) side of the PS9552 so that its pins are as close as possible to the VEE (pin 5) and the VCC (pin 8).

6 5.2 IRED Drive Circuit Design the circuit so that the current IF and voltage VF that are applied to the IRED fall within these recommended ranges: Item Symbol MIN TYP MAX Unit Input Voltage (OFF) VF (OFF) V Input Current (ON) IF (ON) ma Table 5-1 Recommended Operating Conditions for PS9552 IRED For IRED OFF: To ensure the OFF state of the IRED when common-mode transient immunity is at low level output (CML), a reverse bias should be applied to the IRED within these recommended operating condition ranges (Table 5-1). For IRED ON: To ensure the ON state when the commonmode transient immunity is at high level output (CMH), IRED current should be set to the maximum value within these recommended operating condition ranges. 6. Setting Dead-Time The inverter control circuit provides output to drive its load by switching IGBT1 (Upper Arm) and IGBT2 (Lower Arm) alternately on and off as shown in Figure 6-1. If the dead-time is insufficient, IGBT1 and IGBT2 could both switch on, causing a short-circuit current and breakdown of the IGBTs as shown in Figure 6-2. PS9552 No. 1 PS9552 No. 2 IGBT No.1 ON +HV DC (P Line) Upper Arm Output Lower Arm HV DC (N Line) IGBT No.2 OFF Dead-time, TDEAD, should be set so that IGBT1 and IGBT2 are not on at the same time (Figure 6-3). A value greater than the difference between the maximum total turn-off time (toff Total max) and the minimum total turn-on time (ton Total min) of the PS9552 and IGBTs should be set. tdead toff Total max ton Total min = (tphl PS ton IGBT ) max minus (tplh PS toff IGBT ) min = (tphl max tplh min PS9552) plus (toff max ton min IGBT ) = PDD PS (toff max ton min IGBT ) PS9552 No. 1 PS9552 No. 2 IGBT No.1 IGBT No.2 If If IO IO Figure 6-3 Dead-time (tdead) tdead t Optocoupler Input Signal t t IGBT Output Current To simplify dead-time setting, the difference in transmission delay time (PDD) between the tphl and tplh of the PS9552 is regulated (±0.35µs refer to the data sheet). This PDD value is based on tphl and tplh measurements taken at the same temperature and in the same measurement conditions. Therefore, in designing the board layout, make sure the ambient conditions are the same for optocouplers in both the upper and lower arms. Set the dead-time based on thorough verification of the actual system, then add extra margin for safety. t Figure 6-1 Normal Operation of the Inverter Control Circuit PS9552 No. 1 IGBT No.1 ON X +HV DC (P Line) Upper Arm PS9552 No. 2 X IGBT No.2 ON Output Lower Arm HV DC (N Line) Figure 6-2 Short Circuit of the Inverter Control Circuit

7 7. Calculating Junction Temperature LED TJE 1 2 Ta Light Receiving IC TJD Figure 7-1 PS9552 Thermal Resistance Model 3 Figure 7-1 shows the thermal resistance model of the PS9552. It is modeled with two heat sources: the IRED and light receiving IC. TJE = IRED junction temperature TJD = Light receiving IC junction temperature TA = Ambient temperature q1 = Thermal resistance between the IRED and the ambient temperature. q2 = Thermal resistance between the IRED and the light receiving IC. q3 = Thermal resistance between the light receiving IC and the ambient temperature. In this model, the junction temperatures of the IRED and the light receiving IC can be expressed as the follows: Where: TJE = (R11 x PE) + (R12 x PD) + TA (Equation 7.1) TJD = (R21 x PE) + (R22 x PD) + TA (Equation 7.2) PE = Power dissipation of IRED PD = Power dissipation of light receiving IC R11 = IRED and ambient temperature thermal resistance parameter (R11 = q1 (q2 + q3)) R12, R21 = IRED and light receiving IC thermal resistance parameter (R12, R21 = (q1 x q3)/( q1 + q2 + q3)) R22 = Light receiving IC-ambient temperature thermal resistance parameter (R22 = q3 (q1 + q2)) Thermal Resistance Parameters ( C/W) R11 R12, R21 R22 TYP Table 7-1 Thermal Resistance Parameters for PS9552 For example, from equations 7.1 and 7.2, if PE = 27mW, Po = PD = 178 mw, and Ta = 85 C: TJE = (R11 x PE) + (R12 x PD) + TA = (244 C/W x 27mW) + (136 C/W x 178mW) + 85 C = 116 C TJD = (R21 x PE) + (R22 x PD) +TA = (136 C/W x 27mW) + ( 182 C/W x 178mW) + 85 C = 121 C Set junction temperatures TJE and TJD to values equal to or lower than 125 C. 8. Recommended optocouplers for IGBT ratings The tables below list recommended optocouplers for 200 and 400VAC motors. These are provided as guidelines only, optocouplers should be selected based on actual specifications of the IGBTs to be used. IGBT AC MOTOR VCES IC Output Power Recommended (V) (A) (kw) Optocoupler 600 IGBT PS PS PS9553 IO (Peak) = 0.6 A max PS IO (Peak) = 2.5A max IGBT Gate Drive Optocoupler plus current booster Table 8-1 IGBT Gate Driving Optocouplers for 200VAC Motors AC MOTOR VCES IC Output Power Recommended (V) (A) (kw) Optocoupler PS PS PS9552 IO (Peak) = 0.6 A max IO (Peak) = 2.5mA max IGBT Gate Drive Optocoupler plus current booster Table 8-2 IGBT Gate Driving Optocouplers for 400VAC Motors

8 9. Conclusion This application note describes the characteristics of and the methods for using IGBT/MOSFET gate driving optocouplers. We hope this document will be helpful in developing your designs. Furthermore, we will be expanding our lineup of gate driving optocouplers to include new products which feature internal protection circuits and support large-current IGBTs. Information and data presented here is subject to change without notice. California Eastern Laboratories assumes no responsibility for the use of any circuits described herein and makes no representations or warranties, expressed or implied, that such circuits are free from patent infringement. California Eastern Laboratories CL-617-A 4590 Patrick Henry Drive, Santa Clara, CA Tel FAX

DISCONTINUED. California Eastern Laboratories PS9817-1,-2. NEC's HIGH CMR, 10Mbps OPEN COLLECTOR OUTPUT TYPE 8-PIN SSOP (SO-8) HIGH-SPEED OPTOCOUPLER

DISCONTINUED. California Eastern Laboratories PS9817-1,-2. NEC's HIGH CMR, 10Mbps OPEN COLLECTOR OUTPUT TYPE 8-PIN SSOP (SO-8) HIGH-SPEED OPTOCOUPLER NEC's HIGH CMR, 1Mbps OPEN COLLECTOR OUTPUT TYPE 8-PIN SSOP (SO-8) HIGH-SPEED OPTOCOUPLER DESCRIPTION NEC's and PS9817-2 are active-low type high-speed photocouplers that use a GaAlAs light-emitting diode