ELEC-H-473 Microprocessor architectures. Lecture 01 Dragomir Milojevic
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1 ELEC-H-473 Microprocessor architectures Lecture 01 Dragomir Milojevic
2 General information 1. Agenda Lectures 2 ECTS = 12 sessions, 2h/session Monday from to (C3.122); CONFLICT 2B solved! Friday from to (H.2213) TPs 3 ECTS Monday from to (Solbosch, building U UA5.217) Friday cancelled (moved to Monday) 2. ELEC-H-473 Internet resources login: etudiants, password: SquareG! (it is case sensitive) Attention: if you do not login you will not even see the notes. 2
3 General information 3. Conflict dates 3, 7 and 21 March I am travelling (we will organise this) 4. Practical work Presence is mandatory! Mini-projects to be implemented; each project to be presented (you have to show the working demo); Q&A are part of the evaluation Practical work account for 45% of the final mark 5. Examen Is oral Most of the questions are theoretical but some of the questions could be closely related to the practical work You are expected not only to show the lecture content (copy slides), but be able to reason on the matter 3
4 Today 1. Tale on computing machines 2. IC manufacturing technology perspective 3. Computing systems performance 4. Example of poor usage : data centers 5. What could happen in the future? 4
5 The lecture starts with a tale on computing machines... how they are made and and how to push their limits... Do u know from where does this comes from? So once upon a time... 5
6 there was a mathematician that prepared a BIG question for XXth century: David Hilbert, 1900 Could maths be automatized? = mc mc 2 E = mc 2 E = m E = mc 2 6
7 BIG QUESTION got an answer: BIG NO! Kurt Gödel, 1931 = mc mc 2 E = mc 2 E = m E = mc 2 7
8 What can machines compute then? Alain Turing, 1936 Anything that can be computed with a Turing machine! Infinite paper roll b & & a HEAD Alphabet Rules 8
9 Turing machine : conceptual but also real! Enigma, 1936 The Bomb,
10 Mechanics are not the best medium! Claude E. Shannon, 1937 but electric switches are, for sure! 10
11 How to make a usable switch? ENIAC,
12 ... but the size does meter! Transistor, 1947 Integrated Circuit, 1958 AND THE SCALING WAS BORN!!! 1cm 12
13 So, in the and today: ZX81 Mobile Encyclopedia or 2,5 Penta FLOPS in a big room 1kB RAM machine 13
14 What is scaling? MacBook pro, 2011 IBM XT, 1983 ENIAC, 1947 Tendency, transformed in a law... 14
15 Scaling : Moore s law and state of the art Intel Dunnington, processors on the same die 2 billion transistors 1 cm 2 15
16 ... if only the car industry did the same Speed Fuel km/h 0,04 l/100km Price 0,0003$ 16
17 Technology scaling: the sky is the limit? Light Mask Lens Pattern Wafer No, but the size of the light IS! Potential end in 2020? 17
18 What to do next? Go for a non-exploited dimension 3D Circuits, 2010 But, even if this solution sound fantastic, it is JUST to push the limits A BIT FURTHER AWAY, for next couple of years (u r concerned) 18
19 But what about the far future? Optical computing, 2??? Quantum computing, 2??? 19
20 Let s (really) think of the future... a) New computational paradigm is LESS engineering problem and MORE fundamental one, as of today b) Fundamental sciences are not that predictive and require some degree of fussiness... Just think of what I ve said in the beginning of this presentation... and how mathematics led to all this c) We can t definitively PLAN, PROJECT MANAGE and/or PREDICT the arrival of a let s say Quantum Computer on May 15th in
21 and the business view of it... Fortune, 2007 Company SW 1 Hewlett-Packard 2 Intl. Business Machines 3 Dell 4 Apple 5 Xerox 6 Sun Microsystems 7 NCR 8 Pitney Bowes 9 Gateway 10 Palm HW 1 Microsoft 2 Oracle 3 Symantec 4 CA 5 Electronic Arts 6 Adobe Systems 7 Intuit Total SW + HW $ millions 91,658 91,424 57,095 19,315 15,895 13,068 6,142 5,811 3,981 1, ,968 44,282 14,380 4,143 3,805 2,951 2,575 2,362 74, ,466 Computer industry $ But profits are less even Apple moves to low-cost to get the volume 21
22 Conflicting visions We need to make an important step forward, and the current state of the art says: THAT WE ARE ABOUT TO HIT THE WALL IN BOTH WORLDS!!! Will everything stop because of the lack of gain/or because people would like to go back to their sources (i.e. life without computers)? 22
23 Questions for XXIth century... That we/you need to answer Do we want/need better technology for the future? Personally, I would like this to happen... How to motivate/enable fundamental research in this field? How to encourage capitalism to become more human friendly and really invest in fundamental research? After all, didn t it all started as a very romantic and COMPLETELY un-profitable story? 23
24 Scaling (tech/business) model comes to an end... Long term solution Solid paradigm change (going beyond a short term solutions) Short term solutions Conclusion... Better technology (still possible) Better system understanding (today more then ever) Co-design of SW/HW/IC technology These lectures are about understanding HW better and how we can get the best out of it 24
25 2. IC manufacturing technology perspective 25
26 From CMOS transistor... n-type and p-type transistors: source gate drain Polysilicon source gate drain SiO 2 n n p p p substrate n substrate gate gate source drain source drain Current flow is controlled by the gate: source gate GND drain source gate V DD drain (a) n n p substrate GND (b) n n channel p substrate GND Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 26
27 to gate (switch) If the control is binary, the transistor acts like a switch: 2 switches used to make an inverter: source gate GND drain source gate V DD drain V DD (a) n n p substrate GND (b) n n channel p substrate GND A P1 Y N1 g = 0 g = 1 GND nmos g d s d s OFF d s ON pmos g s s ON s OFF d d d Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 27
28 Evolution of CMOS We print features on silicon If we can print smaller features : We can reduce transistors size We can reduce width/length of the interconnect More functionality at higher performance for the same area (cost) This is SCALING Currently: 28, 22nm but with lot s of issues 14nm Intel DELAYED 11nm should arrive sometimes in the near future Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 28
29 Scaling enables better performance 10, Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 29
30 Evolution of CMOS This was the model that run smoothly for past 50 years This is not the case any more After 100nm (sub-micron, ultra deep sub-micron) technology nothing is going to be the same as before More then Moore paradigm Inversion of scaling properties Gains are not the same We start even loosing Scaling side effects! Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 30
31 Scaling side effects : a) $$$$$ 1/2 Fabrication cost Less productivity 100 1E+08 1E E+07 1E+06 1E+08 1E+07 M$ E+05 1E+04 1E+03 1E+02 1E+06 1E+05 1E+04 1E+03 1E Technologie [nm] Conception de masque Logiciel Conception, test, verification de circuit 1E+01 1E+00 Technology [nm] Transistors per IC Transistors placed per month 1E+01 Consequence Technology evolution and design capability do not follow the same path! Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 31
32 Cost examples 2/2 IC cost : very complex equation that is in general carefully balanced (in a very simplified form) IC cost = Die cost + Testing cost + Packaging cost Final test yield Packaging Cost: depends on pins, heat dissipation In practice: constantly increasing! Chip Chip Die Die Package Test Test & Total Total cost cost pins pins type type cost cost Assembly 386DX $4 $ QFP QFP $1 $1 $4 $4 $9 $9 486DX2 $12 $ PGA $11 $11 $12 $12 $35 $35 PowerPC $53 $ QFP QFP $3 $3 $21 $21 $77 $77 HP HP PA PA 7100 $73 $ PGA $35 $35 $16 $16 $124 DEC Alpha $ PGA $30 $30 $23 $23 $202 SuperSPARC $ PGA $20 $20 $34 $34 $326 Pentium $ PGA $19 $19 $37 $37 $473 Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 32
33 Scaling side effects : b) performance gains We have gate delays that decrease, but not those of the wires : We can compute fast, but we communicate slowly! Total delay AI, Si02 Interconnect AI, Si02 Delay, ps Total delay Cu, low k Interconnect Cu, low k Gate delay Gate delay Wire delay Feature size generation, micron Consequence Optimization should be done at communication level too!!! (NoCs) Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 33
34 Scaling side effects : c) power Tendency is changing (curves are normalised to dynamic power dissipation) Power (normalized) 0,01 0, Dynamique Statique Technologie Consequence Get 10% savings in dynamic power dissipation is not significant any more! Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 34
35 End result is : That the CPU F do not increase anymore, to get more functionality (performance) we increase the parallelism Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 35
36 System level impact of scaling Memories and CPUs do not scale equally! 3000 Core frequency (MHz) bus bandwidth (MTs) Core to bus ratios are increasing at 20% per year Core freq increases 40% per year The memory gap. ( Year : Sandpile.org.) Bus rate inc 20% per year Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 36
37 3. Computing systems performance 37
38 Performance Clock cycle (Clk) Clk is there because CPU is a synchronous logic circuit (circuits with feedback) system state is stored in flip-flops Clk is used to drive all flip-flops in the design (data-flow from flops to flops, so for the combinatory circuits too) Typically one master clock that supply different clock domains 38
39 CPI Performance We can measure the number of cycles required to execute all instruction within a computer program We can count the number of executed instructions Cycles per instruction (CPI) on average for a given program : = Total number of cycles to execute Total number of instructions in the program 39
40 Performance CPI of each instruction (CPU data sheet) addition, logic operation (simple) 1 cycle, multiplication (complex operation) from 1 to few cycles, depending on hardware Instruction(s) Per Cycle (IPC) for an application IPC = 1/CPI but computed a posteriori (profiling) Measures the parallelism if it is > 1 Most of the computers should have this TRUE!!! 40
41 Performance Execution of a computer program (IC app instruction count): CPU_time = Clk x CPI x IC How to minimize CPU_time? Increase Clk Increase F (will not hold that long) look at IC scaling predictions for the future from node to node:!"#$%&"'()*" +&"#,! -.. /01"& /01"&'2"3()$4 56'7778'9: ;<=66 ;<6= ;<>>6?<? ;<@:6 ;<>:>?<;@> 9:'7778':: ;<=66 ;<6= ;<>>6?<;A ;<@6 ;<>5A?<?96 ::'7778'?5 ;<=66 ;<6= ;<>>6?<;6 ;<@=6 ;<>>5?<?>:?5'7778'?; ;<=66 ;<6= ;<>>6?<;5 ;<@A6 ;<>=??<?=6 41
42 Performance How to minimize CPU_time? Increase Clk Increase F (will not hold that long) Reduce CPI Parallelism: inter et intra CPU (multi, scalar, super-pipeline etc.) Reduce IC Algorithm, SIMD, implementation (SW), Certain mechanisms are automatic, others are not! Optimizations as function of the architecture You need to know HW and the way that operate to be able to exploit at best all the possibilities that are there! 42
43 Solutions? Improve tech Increase parallelism multi, many core multi-processor Better usage at application level After all, all these systems are used badly Let s see this on a concrete example DATA CENTERS!!! (cloud computing) Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 43
44 4. Example of poor usage: Data Centers 44
45 Data centers are power hungry! Board Rack Building in all, thousands of CPUs using considerable power. Did BIG ones (MS, Yahoo, etc.) became GREEN? $$$ Electricity bill $$$ In 2007: 7.2 Billions US$ 45
46 Data centers use traditional cores Heavily pipelined Bunch of FPUs SIMD support Big, shared caches Complex circuits, built to suit any application (as long as it is not embedded) 46
47 How good multi-core really is? B/W unused! Cores too fat! Too few cores! 10 MB (80%) waste of silicon (no reuse)! Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 47
48 But how good parallelism really is? Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 48
49 But how good parallelism really is? Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 49
50 Learnings One fits all solution was the only one economically viable Same CPU: for gaming, scientific computing, grandma s wordprocessing and data center Worked very well in the past (Intel), but... Doesn t work any more! Computing usage habit changed: we eventually went back to the terminal/main frame concept from the past (tablet/cloud) Small/or not embedded computing power with IO capacity Demand on high-perf CPUs is slowing down, much more then even almighty Intel predicted: 14nm fab is delayed! 50
51 5. What could happen in the future? (this is not a tale) 51
52 Computer classes and important issues Desktop Computing Price-performance ratio and graphics capabilities (gaming!, look at NVIDIA) Servers Throughput, availability, scalability Embedded Computers Price, power consumption, application-specific performance Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 52
53 Computer classes Winds of change Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 53
54 What could happen in the near future? Desktop Computing disappears, Intel opens their fab and stop working on CPUs Servers made using low power cores like ARM Embedded Computers made using the same lowpower cores used for servers (just look at the Apple products: iphone/ipad) What about CPUs? CPU architectures are stable Instructions set do not change much (although they can be adapted to a particular app) We need to start really using them plus system integration Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 54
55 So what s for us there? Whatever underlaying tech will be used (even in the far future) some processing devices will always be there Atomic adder it is still an adder Processing device = CPU Architectural concepts of the CPU may vary depending on the technology offering, but lots of fundamental concepts will probably remain the same Even if low-power CPUs are killing desktop CPUs they still Have pipelined structure Use reg files and ALUs to compute things Parallelize what ever could be done in parallel & many others Université libre de Bruxelles/Faculté des Sciences Appliquées/PARTS/MILOJEVIC Dragomir 55
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