The Advanced Power Semiconductor Laboratory at ETH Zurich. from semiconductor materials to module reliability

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1 The Advanced Power Semiconductor Laboratory at ETH Zurich from semiconductor materials to module reliability 19 Apr

2 The Advanced Power Semiconductor Laboratory APS Established in 2015 Based on an departmental initiative to strengthen the Research Area Energy Start-up phase supported by ETH Foundation 19 Apr

3 Semiconductor to Converter Research at APS Power Electronics Systems EMPA Power Electronics Integration Semiconductor Materials and their Devices Performance & Reliability Packaging of Power Devices Packaging BRNC PSI Characterization of Devices and their Modules Power Semiconductors 19 Apr

4 Establishing the research infrastructure Simulation tools from material to circuit level Introducing SiC to ETH cleanroom facilities Setup of electrical characterization laboratory Partnering within ETH domain PSI, EMPA large scale facilities at PSI, radiation hardness, advanced bonding technologies 19 Apr

5 First projects Understanding SiC TCAD simulation SiC MOSFET manufacturing SiO 2 -SiC interface with PSI Bonding technologies with EMPA Module design for high-voltage devices Setting up module simulation tools Ansys Q3D 19 Apr

6 Deep-Level Transient Spectroscopy (DLTS) Determination of energy levels PN junctions Schottky junctions MIS capacitors Characteristics Bias voltage [-100V, 100V] Res. of 0.3mV Min. pulse width 20ns Max. current 15mA Res. of 10pA Temperature range [20K, 800K] 19 Apr

7 Wafer Prober / Parameter Analyzer On-wafer measurements Up to 8 inch wafers I-V 10kV, 100A pulse C-V 1kHz - 10 MHz Thermal chuck [-60 C, 300 C] Safety system Interlock circuit Light curtains 19 Apr

8 Custom Test Stands Modular system Power Control DUT PCB Drivers PSUs HV, LV, Aux Low power Keysight DSO 500 MHz, 10 GS/s 10 bit Double Pulse Switching, Unclamped Inductive Switching, Short Circuit, C OSS 19 Apr

9 Power Tester 1500A Thermal transient measurements Determine thermal impedances Analyze package structure Active thermal cycling Simulate application operation Determine package lifetime Three power supplies 500 A, 8V each Can be paralleled T3ster measurement system Records device parameters Delivers measurement current (1A) 19 Apr

10 SiC Research at the Paul Scherrer Institut From fundamental research towards device physics Judith Wörle Gain deeper understanding of the SiO 2 /SiC interface Morphology (HR-AFM, SEM, TEM, ) Chemical composition (XPS, EDX, ) Electrical characteristics (cafm, ARPES, ) «High» μ Ch without post-oxidation annealing Slow oxidation at 1050 C D it increases for longer oxidation times Mobilities μ Ch > 30 cm 2 V -1 s Apr

11 Analyzing the SiO 2 /SiC Interface the ARPES Approach Angle-Resolved Photoemission Spectroscopy at the SLS Judith Wörle Use Synchrotron light to investigate 4H-SiC, buried under SiO 2 layer e - hν Very surface sensitive but could see SiC below SiO 2 No surface defects observed No Shockley-Tamm states observed in SiC 19 Apr

12 Virtual Dynamic Characterization of Discrete SiC Power Devices Ivana Kovacevic, Thomas Ziemann, Bhagyalakshmi Kakarla 1.2kV 80mΩ SiC MOSFET (CREE C2M D) in ANSYS Q3D LTSpice ANSYS Q3D 19 Apr

13 TCAD Device Simulations Johanna Müting Goal: simulation of silicon carbide power semiconductors from beginning (processing) to end (package) Prediction of electrical behavior and failure mechanisms Simulation of a Cree MOSFET device to understand macroscopic charge carrier transport Influence of mobility degradation models Influence of interface properties Influence of doping and geometry Drain-Source Current (A) Drain-Source Current (A) Simulation Exp. Data [8] V GS = 16 V V GS = 18 V V GS = 5 V V GS = 10 V V GS = 20 V Drain-Source Voltage (V) V GS = 20 V V GS = 15 V -60 Simulation Exp. Data [8] Drain-Source Voltage (V) V GS = 14 V V GS = 12 V V GS = 10 V 19 Apr

14 Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kv Silicon Carbide MOSFETs S. Nida, T. Ziemann, B. Kakarla P-base Source Source P-base Source P-base N - Drift N+ Drain Voltage spikes lead to reaching critical electric field N - Drift N+ Drain Impact ionization generates carriers and the device starts conducting N - Drift N+ Drain Self heating increases the junction temperature Planar 1.2kV 80 mω MOSFET (C2M D) simulation Gate off Discharging failure S2 There is no significant improvement of avalanche performance by using an off state gate bias of -10 V. Thus, threshold voltage lowering due to self-heating is an insignificant contributor to destructive failure in the power MOSFETs tested. For devices other than S1, threshold was above 4 V, which is the maximum reduction in threshold calculated at 1500K. So the device remains off until intrinsic temperature. Our simulations show the device going intrinsic at the point of failure. Thus current path goes through the entire p-base region. 19 Apr

15 ICSCRM 2017 Continuous Compact Model of a SiC VDMOSFET Based on Surface Potential Theory B. Jäger, Y. Ju, R. Stark Planar to Trench: Short Circuit Capability Analysis of State-of-the-Art 1.2 kv SiC MOSFETs B. Kakarla, T. Ziemann, S. Nida, E. Dönni Improvement in Single Pulse Avalanche Ruggedness of 1.2 kv Silicon Carbide Trench MOSFETs by Applying a Negative Gate Bias S. Nida, B. Kakarla, T. Ziemann Simulation-Based Sensitivity Analysis of Conduction and Switching Losses for Silicon Carbide Power MOSFETs J. Müting Exploring the Buried SiO 2 /SiC Interface by Soft X-Ray ARPES J. Wörle, V. N. Strokov, H. Sigg, Jens Gobrecht, M. Camarda 19 Apr

16 Trade-off Analysis of the p-base Doping on Ruggedness of SiC MOSFETs B. Kakarla, S. Nida, J. Müting, T. Ziemann, I. Kovacevic MOSFET with modified channel doping is more rugged under short-circuit as well as avalanche conditions while maintaining reasonable threshold as well as breakdown voltage 19 Apr

17 Exploring the Behavior of Parallel Connected SiC Power MOSFETs Influenced by Performance Spread in Circuit Simulations J. Müting, N. Schneider, T. Ziemann, R. Stark Drain Drain-Source Voltage (V) f = 200 khz, d = 50 %, t sim = 20 ms Drain-Source Current (A) Gate Drain Resistance VDMOS Interface Charge L G L D L S Source V RD Body Diode Time ( s) Resulting imbalances for T amb = 25 C: ΔI = 2 A ΔT = T max T min = 74 C - 66 C = 8 K 19 Apr

18 Parasitic Extraction Procedures for SiC Power Modules I. Kovacevic-Badstübner, R. Stark, M. Guacci, J. W. Kolar Horizon2020 Project Integrated, Intelligent Modular Power Electronic Converter (I2MPECT) CIPS 2012: K. Weidner et al., Planar Interconnect Technology for Power Module System Integration, Siemens AG position 0 (p 0 ) and position 2 (p 2 ) close to the power module position p 1 includes the length of the bus-bars Simulation A L DS Simulation B L DS,eq 19 Apr

19 Selected Student Projects 2015 now Sentaurus TCAD Device Simulation Model for SiC Power MOSFETs Michael Haider, Friedrich Thöny F2015 Influence of Geometry and Doping of Field Rings on Termination Ruggedness of a 1.2kV SiC MOSFET Armando Piasko F2016 C oss Related Energy Loss of MOSFET's in Zero-Voltage Switching Applications Morris Heller F2016 Comparative Study of Mobility Models Using Comsol Multiphysics Beat Jäger F2016 Development of a Circuit Simulation Model for Silicon Carbide Power MOSFETs - Nick Schneider S2017 Design and Construction of a Short Circuit Tester Elias Dönni S2017 Development of Control Software for a Power Semiconductor Switching Loss Test Stand Marc Herzog S2017 New Technology for 4H-SiC MOSFETs Yandong Zhou S2017 Simulation of SiC XBPM Devices in Synchrotron Applications Elias Passerini S2017 Development of a SiC MOSFET compact model based on the Surface Potential Model Beat Jäger MSc thesis Apr

20 Research Strategy Ruggedness of power devices and modules Design for reliability understanding parameter spaces Radiation hardness Device and module manufacturing Device manufacturing enabling advanced bonding technologies Manufacturability Low inductance, intelligent/integrated power modules Multi-domain, multi-physics modeling from material to virtual prototyping Strong focus on wide bandgap semiconductors 19 Apr

21 People Karin Sonderegger Zaky Administrative Assistant Bhagyalakshmi Kakarla MSc EE Communications U Kassel Device Simulation Roger Stark MSc EE ETHZ Characterization Yanrui Ju MSc EE Peking U Device Manufacturing Ivana Kovacevic Dr.sc. ETH Zurich Multi-Domain Modeling Massimo Camarda PhD Physics. U of Catania / NTNU PSI Academic Associate Dr.rer.nat. FSU Jena, MBA U Mass Head of Laboratory Thomas Ziemann MSc EE RWTH Packaging: Design, Testing Philipp Natzke MSc Material Science, TU Dresden Packaging: Materials, Analysis Judith Wörle MSc Physics U Innsbruck PSI MOS Interface, Analysis Johanna Müting MSc EE RWTH Device Simulation Alexander Tsibizov PhD Physics. Moscow State U Device Simulation Selamnesh Nida MSc EE U Notre Dame Device Manufacturing 19 Apr

22 Thank you for your attention!