Evolution of SiC MOSFETs at Cree Performance and Reliability

Transcription

1 Evolution of SiC MOSFETs at Cree Performance and Reliability Brett Hull :: August 13, 2015 Dan Lichtenwalner, Vipin Pala, Edward VanBrunt, Sei- Hyung Ryu, Jim Richmond, Leo Wang, Philip Butler, Don Gajewski, Scott Allen, John Palmour Cree, Inc. Christina DiMarino CPES, Virginia Tech

2 Acknowledgements 2 Sponsored in part by Army Research Laboratory under Cooperative Agreement W911NF The information, data or work presented herein was funded in part by the Office of Energy Efficiency and Renewable Energy (EERE), U.S. Department of Energy, under Award Number DE-EE The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DE- AR Also Mr. Lynn Petersen from United States Office of Naval Research, through subcontracts from the Pennsylvania State University, Electro-Optics Center (Subcontract # 0145-SC ), supported the information, data, and work presented herein. Disclaimer: The information, data, or work presented herein was funded in part by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

3 Cree Commercial SiC MOSFET Portfolio 3 Gen 2 Platform DC Current (T C = 100 C) 1200V/280 mw 6A 1200V/160 mw 12.5A 1200V/80 mw 24A 1200V/40 mw 40A 1200V/25 mw 60A 1700V/1 W 2.6A Gen 3 Platform DC Current (T C = 100 C) 900V/65 mw 22A (D2PAK-7L) 23A (TO-247) D2PAK-7L TO-247 & TO-220 Die Gen 3 Platform In Development 900V/10 mw 900V/120 mw 900V/280 mw 1200V/15 mw

4 MOSFET Portfolio Commercial and R&D 4 Functional MOSFETs demonstrated from 900V to 15kV Parasitic resistances dominate at lower voltages Channel Mobility R ON,SP (m W cm 2 ) kv 10 kv 15 kv Substrate 10 Cree CMF Family 3.3 kv Cree C2M Family Improving Low Voltage MOSFETs Optimize Cell Layout Improve Oxide Performance Trench MOSFET 1.7 kv 1.2 kv 900 V ,000 10,000 Breakdown Voltage (V)

5 Next Generation SiC MOSFETs Nearly 5 Years in the Market 5 Reduced pitch Optimized doping Gen 2 DMOS Gen 3 DMOS Commercially released in 2013 as C2M product family at kV Commercially released in 2015 as C3M product family at 0.9kV Same high reliability DMOS Structure, but optimized to reduce die size

6 DIVIDER SLIDE EXAMPLE Gen 3 MOSFET Performance: 900V and 1200V

7 Industry s First 900V SiC MOSFETs Released May V/65mΩ TO-220, TO-247, D2PAK-7L, die R on,sp = 2.3 m W cm 2 R DS,on is 1.5X lower than Si at 150 C R DS,on E OSS is 4-6X better than Si

8 Performance Advantages and Cost Competitive 8 Parameter SiC C3M J Package 7L D2PAK TO-247 Blocking Voltage 900 V 900V I DS 100 C 22 A 23 A Si IPW90R120C3 Comments R DS (on) 25 C 65 mω 100 mω 1.5x better than Si R DS (on) 150 C 90 mω 270 mω 3x better than Si Q G 30 nc 270 nc 9x better than Si Ciss 660 pf 6800 pf 10x better than Si Coss 60 pf 300 pf 5x better than Si T Jmax 150 C 150 C Diode Reverse-Recovery Charge (Q rr ) Reverse-Recovery Time (T rr ) Cost (Digikey, single unit, Aug 2015) 131 nc 30,000 nc >200x better than Si 16 ns 920 ns >57x better than Si $10.31 $ % lower cost

9 900V/10mW Gen 3 MOSFET ON Resistance (m W) Temperature ( C) 1.7x Increase in R on from 25 C to 175 C Significantly smaller increase in R DS,on with temperature compared to 650V/19 mw Si Superjunction MOSFET (IPZ65R019C7) mm x 7.56 mm Lower On-State losses than 650V/100A Si IGBT, especially at light loads (IPZ65R019C7) I DS / I CE (Amps) V DS / V CE

10 Switching Performance of 900V/10mW Gen 3 MOSFET Turn-On Drain-Source Voltage (V) 700 Vds Ids Time (ns) 100 Drain Current (A) Switching Loss (mj) Vds Ids Drain-Source Current, I DS (A) Turn-Off Drain-Source Voltage (V) Drain Current (A) E SW = 1.8 mj at 100A/400V E SW = 4.5 mj at 150 C and 100A/400V for 650V/100A Si IGBT (IGZ100N65H5) Time (ns)

11 ES-CPM B (Engineering Samples) V GS = 0, 5, 10, 15V Blocking voltage Current rating 1200 V 75 A (T C < 100 C) Drain Current (A) V GS Max (-8) / (+18) V Typ R 25 C 15 mω R 25 C 2.7 mω cm 2 Typ R 150 C 26 mω Gate charge total 179 nc Drain Bias (V) Chip Dimensions 4.04 mm x 6.44 mm Gate Pad 800 µm x 500 µm Source Pads (each x 3) 1020 µm x 4540 µm Top Side Source/Gate metallization (Al) Bottom Drain metallization (Ni/Ag) 4 μm 0.8 / 0.6 μm

12 DIVIDER SLIDE EXAMPLE Gen 2 MOSFET Quality at 175 C

13 Maximum Junction Temperature 13 Reasons for Increasing T J,max 1) Less cooling required 2) Squeeze more performance from a given chip in a given system 3) Provide additional margin of safety for system designers P T T R, JC Maximum Allowe ed DIssipated Power (W) Case Temperature ( C)

14 Gen 2 MOSFET Qualification at 175 C - HTGB 14 C2M D 4.04 mm x 6.44 mm Chip Size 1000 Hours, V GS = 22V 3 Lots x 75 parts/lot All parts pass parametric specifications 0.2V Shift in V T No shift in V DS,on

15 Gen 2 MOSFET Qualification at 175 C - HTRB 15 C2M D 4.04 mm x 6.44 mm Chip Size 1000 Hours, V DS = 960V 3 Lots x 25 parts/lot All parts pass parametric specifications

16 Gen 2 MOSFET Accelerated Life Testing under High Bias Conditions 16 8 DrainCurrent(uA) V GS = 0V 150 C V BD = 1660V Time (Hours) C2M D Drain Bias (V) Accelerated Life Testing under High Temperature Reverse Bias Conditions (ALT-HTRB) 150 C Drain Bias Conditions: 1460V, 1540V, 1620V Test to Failure Collate Failure Time Statistics Extrapolated Mean Time to Failure at 800V 30 Million Hours 3400 Years

17 Body Diode Stability at T J = 175 C C2M D 17 DC Body Diode Stress 25 MOSFETs 75 C Baseplate I SD = 15A DC T J ~ 175 C All parts show stable Body Diode V SD over 1000 hours Parts removed and checked at 16 hours and 90 hours All parts pass parametric specifications after 1000 hours of stress Bo ody Diode Voltage (V) Time (Hours)

18 DIVIDER SLIDE EXAMPLE Gen 3 MOSFET Avalanche Ruggedness during Unclamped Inductive Switching (UIS) 900V MOSFETs

19 Non-Repetitive Avalanche Rating 19 Defining the Robustness of a MOSFET under a high-current avalanche fault condition Snubberless Circuits Improperly Clamped Inductances Unexpected Voltage Overstresses V GS,ON V GS V DS Current Sense Silicon MOSFETs typically rated such that T J does not exceed T J,max (150 to 175 C) Depends on Current (I AV ), Avalanche Voltage (V AV ), Duration (t AV )/Inductance (L) and Thermal Impedance (Z TH ) Silicon Carbide can handle much higher temperatures I AV V (BR)DSS V DS,OFF t t AV

20 Avalanche Ruggedness of C3M MOSFETs 20 C3M V/65mW MOSFETs 6 5 Inductor / Avalanche current Drain Voltage Breakdown Performance at 25 and 150 C Inductor Current V Av = 1405 V E Av = 191 mj t Av = 68.4 μs Drain Vo oltage (V) Internal Device Temperatures reaching 100 s of C during avalanche Time (μs) Unclamped Inductive Switching (UIS) Event for C3M D MOSFET

21 Defining Avalanche Ruggedness C3M Avalanche rating determined statistically from the failure of tens of MOSFETs at several Input Currents (10A, 20A and 30A) Avalanche Ruggedness Qualification Success Applied rated Avalanche Conditions (100 discrete pulses) 3 Lots x 25 Parts/Lot x 2 different currents (5A and 30A) 1000 hour HTGB and HTRB performed following Avalanche Stress All parts passed HTGB and HTRB Accelerated HTRB (in Avalanche) under way (see next slide) C3M V/65mW MOSFETs

22 Accelerated HTRB in Avalanche (of Parts subjected to Avalanche Stress) Drain Current (ua) V GS = 0V Time (Hours) V DS = 1360V C3M D MOSFETs 900V/65mW 3 Lots x 10 Parts per Lot x 2 Avalanche Stress Currents (5A and 30A) Parts Running for >1600 hours at 150 C at 1200V+ Two failures from the population as of 1600 hours

23 Avalanche Ruggedness at Elevated Temperatures C3M C3M V/65mW MOSFETs Single Pulse Avalanche Energy (mj) Current in Avalanche (A) MOSFETs are avalanche rugged at T J,max In single pulse UIS, internal temperature of the MOSFET significantly exceeds T J,max This overhead results in only a small drop in UIS Avalanche ruggedness with an increased junction temperature

24 Summary 24 Third Generation DMOSFETs in Production (900V) or Development (900V, 1200V +) Significant performance advantage over Si CoolMOS and IGBTs 175 C Qualification ongoing UIS avalanche ruggedness demonstrated R ON,SP (m W cm 2 ) Cree CMF Family 3.3 kv 6.5 kv 10 kv 15 kv Room for improvement remains in lower voltage MOSFETs Further cell pitch optimization Oxide improvements 1 Cree C2M Family 1.7 kv 1.2 kv 900 V 100 1,000 10,000 Breakdown Voltage (V)