Switch mode power supplies Low gate charge. Power factor correction modules Low intrinsic capacitance

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1 Description United Silicon Carbide's cascode products co-package its highperformance F3 SiC fast JFETs with a cascode optimized MOSFET to produce the only standard gate drive SiC device in the market today. This series exhibits very fast switching using a 4-terminal TO-247- package and the best reverse recovery characteristics of any device of similar ratings. These devices are excellent for switching inductive loads, and any application requiring standard gate drive. 3mW - 65V SiC Cascode UF3C653K4S CASE G (4) KS (3) CASE D (1) S (2) Features Typical Applications Typical on-resistance R DS(on),typ of 3mW EV charging Maximum operating temperature of 175 C PV inverters Excellent reverse recovery Switch mode power supplies Low gate charge Power factor correction modules Low intrinsic capacitance Motor drives ESD protected, HBM class 2 Induction heating TO-247-4L package for faster switching, clean gate waveforms Maximum Ratings Drain-source voltage Gate-source voltage Parameter Continuous drain current 1 Maximum junction temperature Operating and storage temperature Max. lead temperature for soldering, 1/8 from case for 5 seconds 1 Limited by T J,max 2 Pulse width t p limited by T J,max 3 Starting T J = 25 C Symbol V DS V GS I DM E AS P tot Test Conditions DC T C =25 C T C =1 C Pulsed drain current 2 T C =25 C 23 Single pulsed avalanche energy 3 L=15mH, I AS =4A Power dissipation I D T C =25 C Part Number Package Marking UF3C653K4S TO-247-4L UF3C653K4S T J,max 175 C T J, T STG -55 to 175 C to +25 T L 25 C V V A A A mj W Preliminary, March For more information go to

2 Electrical Characteristics (T J = +25 C unless otherwise specified) Typical Performance - Static 3mW - 65V SiC Cascode UF3C653K4S Parameter Symbol Test Conditions Min Typ Max Drain-source breakdown voltage BV DS V GS =V, I D =1mA 65 V Total drain leakage current Total gate leakage current Drain-source on-resistance Gate threshold voltage Gate resistance V DS =65V, 6 15 V GS =V, T J =25 C I DSS ma V DS =65V, 3 V GS =V, T J =175 C V DS =V, T j =25 C, I GSS 6 2 ma V GS =-2V / +2V R DS(on) V GS =12V, I D =5A, T J =25 C V GS =12V, I D =5A, T J =175 C 3 35 V G(th) V DS =5V, I D =1mA V R G f=1mhz, open drain 4.5 W 48 mw Typical Performance - Reverse Diode Diode continuous forward current 1 Diode pulse current 2 Forward voltage Reverse recovery charge Reverse recovery time Reverse recovery charge Reverse recovery time Parameter Symbol Test Conditions Min Typ Max I S T C =25 C 85 A I S,pulse T C =25 C 23 A V FSD V GS =V, I F =2A, T J =25 C V GS =V, I F =2A, T J =175 C V R =4V, I F =5A, Q rr 425 nc V GS =-5V, R G_EXT =1W di/dt=265a/ms, t rr 25 ns T J =25 C V R =4V, I F =5A, Q rr 28 nc V GS =-5V, R G_EXT =1W di/dt=265a/ms, t rr 2 ns T J =15 C V Preliminary, March For more information go to

3 Typical Performance - Dynamic 3mW - 65V SiC Cascode UF3C653K4S Parameter symbol Test Conditions Min Typ Max Input capacitance C iss V DS =1V, 15 Output capacitance C oss V GS =V, 32 Reverse transfer capacitance C rss f=1khz 2.3 Effective output capacitance, energy related Effective output capacitance, time related V DS =V to 4V, C oss(er) 23 pf V GS =V V DS =V to 4V, C oss(tr) 52 pf V GS =V C OSS stored energy E oss V DS =4V, V GS =V 18.5 mj Total gate charge Gate-drain charge Gate-source charge Turn-on delay time Rise time Turn-off delay time Fall time Turn-on energy Turn-off energy Total switching energy Turn-on delay time Rise time Turn-off delay time Fall time Turn-on energy Turn-off energy Total switching energy Q G 51 V Q DS =4V, I D =5A, GD 11 V GS =-5V to 15V Q GS 19 t d(on) V DS =4V, I D =5A, Gate 25 t r Driver=-5V to +12V, 31 t Turn-on R G,EXT =8.5W, d(off) 48 Turn-off R G,EXT =2W t f 12 Inductive Load, E ON FWD: same device with 31 E OFF V GS = -5V, R G = 1W 171 E TOTAL T J =25 C 481 t d(on) V DS =4V, I D =5A, Gate 22 t r Driver=-5V to +12V, 27 t Turn-on R G,EXT =8.5W, d(off) 48 Turn-off R G,EXT =2W t f 1 Inductive Load, E ON FWD: same device with 247 E OFF V GS = -5V, R G = 1W 114 E TOTAL T J =15 C 361 pf nc ns mj ns mj Thermal Characteristics Parameter symbol Test Conditions Min Typ Max Thermal resistance, junction-to-case R qjc C/W Preliminary, March For more information go to

4 On Resistance, R DS_ON (P.U.) Typical Performance Diagrams 3mW - 65V SiC Cascode UF3C653K4S Vgs = 15V Vgs = 1V Vgs = 7.5V Vgs = 7V Vgs = 6.5V 1 5 Vgs = 15V Vgs = 1V Vgs = 7V Vgs = 6.5V Figure 1 Typical output characteristics at T J = - 55 C, tp < 25 m s Figure 2 Typical output characteristics at T J = 25 C, tp < 25 m s Vgs = 15V Vgs = 1V Vgs = 7V Vgs = 6.5V Vgs = 6V Junction Temperature, T J ( C) Figure 3 Typical output characteristics at T J = 175 C, tp < 25 m s Figure 4 Normalized on-resistance vs. temperature at V GS = 12V and I D = 5A Preliminary, March For more information go to

5 Threshold Voltage, V th (V) Gate-Source Voltage, V GS (V) On-Resistance, R DS(on) (mw) 3mW - 65V SiC Cascode UF3C653K4S Tj = 175 C Tj = 25 C Tj = - 55 C Tj = -55 C Tj = 25 C Tj = 175 C Gate-Source Voltage, V GS (V) Figure 5 Typical drain-source on-resistance at V GS = 12V Figure 6 Typical transfer characteristics at V DS = 5V Junction Temperature, T J ( C) Gate Charge, Q G (nc) Figure 7 Threshold voltage vs. T J Figure 8 Typical gate charge at V DS = 5V and I D = 1mA at V DS = 4V and I D = 5A Preliminary, March For more information go to

6 E OSS (mj) 3mW - 65V SiC Cascode UF3C653K4S -25 Vgs = -5V Vgs = V Vgs = 5V -25 Vgs = - 5V Vgs = V Vgs = 5V Figure 9 3rd quadrant characteristics Figure 1 3rd quadrant characteristics at T J = - 55 C at T J = 25 C Vgs = - 5V Vgs = V Vgs = 5V Figure 11 3rd quadrant characteristics at T J = 175 C Figure 12 Typical stored energy in C OSS at V GS = V Preliminary, March For more information go to

7 Power Dissipation, P tot (W) Thermal Impedance, Z qjc ( C/W) Capacitance, C (pf) DC 3mW - 65V SiC Cascode UF3C653K4S C iss 8 1 C oss C rss Case Temperature, T C ( C) Figure 13 Typical capacitances at 1kHz and V GS = V Figure 14 DC drain current derating Case Temperature, T C ( C) Figure 15 Total power dissipation.1.1 D =.5 D =.3 D =.1 D =.5 D =.2 D =.1 Single Pulse.1 1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 Pulse Time, t p (s) Figure 16 Maximum transient thermal impedance Preliminary, March For more information go to

8 Turn-on Energy, Eon (mj) Turn-Off Energy, Eoff (mj) Switching Energy (mj) 3mW - 65V SiC Cascode UF3C653K4S 1 1 1ms 1ms 1ms V DD = 4V, V GS = -5V/12V R G_ON =8.5W, R G_OFF = 2W FWD: same device with V GS =-5V, R G = 1W Etot Eon Eoff 1 DC 1ms 1ms Figure 17 Safe operation area Figure 18 Clamped inductive switching energy T c = 25 C, D =, Parameter t p vs. drain current at T J = 25 C V DD = 4V, V GS = -5V/12V I D = 5A, T J = 25 C FWD: same device with V GS = -5V, R G = 1W V DD = 4V, V GS = -5V/12V I D = 5A, T J = 25 C FWD: same device with V GS = -5V, R G = 1W Total External R G, R G,EXT_ON (W) Total External R G, R G,EXT_OFF (W) Figure 19 Clamped inductive switching Figure 2 Clamped inductive switching turn-on energy vs. R G,EXT_ON turn-off energy vs. R G,EXT_OFF Preliminary, March For more information go to

9 Switching Energy (mj) Qrr (nc) 3mW - 65V SiC Cascode UF3C653K4S V DD = 4V, V GS = -5V/12V R G_ON = 8.5W, R G_OFF = 2W FWD: same device with V GS =-5V, R G =1W Etot Eon Eoff V DD = 4V, I S = 5A, di/dt = 265A/ms, V GS = -5V, R G =1W Junction Temperature, T J ( C) Junction Temperature, T J ( C) Figure 21 Clamped inductive switching energy Figure 22 Reverse recovery charge Qrr vs. vs. junction temperature at I D = 5A junction temperture Applications Information SiC cascodes are enhancement-mode power switches formed by a high-voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (R DS(on) ), output capacitance (Coss), gate charge (Qg), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC cascodes also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the cascode is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on cascode operation, see Disclaimer United Silicon Carbide, Inc. reserves the right to change or modify any of the products and their inherent physical and technical specifications without prior notice. United Silicon Carbide, Inc. assumes no responsibility or liability for any errors or inaccuracies within. Information on all products and contained herein is intended for description only. No license, express or implied, to any intellectual property rights is granted within this document. United Silicon Carbide, Inc. assumes no liability whatsoever relating to the choice, selection or use of the United Silicon Carbide, Inc. products and services described herein. Preliminary, March For more information go to

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