IRF3205S/L. HEXFET Power MOSFET V DSS = 55V. R DS(on) = 8.0mΩ I D = 110A

Transcription

1 l l l l l l Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Fully Avalanche Rated Description Advanced HEXFET Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G IRF3205S/L HEXFET Power MOSFET D S PD V DSS = 55V R DS(on) = 8.0mΩ I D = 0A The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF3205L) is available for low-profile applications. Absolute Maximum Ratings D 2 Pak IRF3205S TO-262 IRF3205L Parameter Max. Units I T C = 25 C Continuous Drain Current, V 0V 0 I T C = C Continuous Drain Current, V 0V 80 A I DM Pulsed Drain Current 390 P C = 25 C Power Dissipation 200 W Linear Derating Factor.3 W/ C V GS Gate-to-Source Voltage ± 20 V I AR Avalanche Current 62 A E AR Repetitive Avalanche Energy 20 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting torque, 6-32 or M3 srew 0 lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 C/W R θja Junction-to-Ambient (PCB mounted, steady-state)* /09/0

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 8.0 mω V GS = 0V, I D = 62A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA g fs Forward Transconductance 44 S V DS = 25V, I D = 62A I DSS Drain-to-Source Leakage Current 25 V µa DS = 55V, V GS = 0V 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage V GS = 20V na Gate-to-Source Reverse Leakage - V GS = -20V Q g Total Gate Charge 46 I D = 62A Q gs Gate-to-Source Charge 35 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 54 V GS = 0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 4 V DD = 28V t r Rise Time 0 I D = 62A ns t d(off) Turn-Off Delay Time 50 R G = 4.5Ω t f Fall Time 65 V GS = 0V, See Fig. 0 Between lead, L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact C iss Input Capacitance 3247 V GS = 0V C oss Output Capacitance 78 V DS = 25V C rss Reverse Transfer Capacitance 2 pf ƒ =.0MHz, See Fig. 5 E AS Single Pulse Avalanche Energy mj I AS = 62A, L = 38µH Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 0 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 390 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 62A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 62A Q rr Reverse Recovery Charge nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 38µH R G = 25Ω, I AS = 62A. (See Figure 2) ƒ I SD 62A, di/dt 207A/µs, V DD V (BR)DSS, T J 75 C Pulse width 400µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. This is a typical value at device destruction and represents operation outside rated limits. This is a calculated value limited to T J = 75 C. * When mounted on " square PCB ( FR-4 or G-0 Material ). For recommended footprint and soldering techniques refer to application note #AN D S

3 I D, Drain-to-Source Current (A) 0 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 4.5V I D, Drain-to-Source Current (A) 0 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 0 0 T J = 25 C T J= 75 C V DS = 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 I D = 07A V GS = 0V T J, Junction Temperature( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 C, Capacitance(pF) IRF3205S/L V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss V GS, Gate-to-Source Voltage (V) I D = 62A V DS= 44V V DS= 27V V DS= V 0 0 V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 0 0 T J= 75 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Voltage (V) 00 I D, Drain Current (A) 0 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us us ms 0ms TC = 25 C TJ = 75 C Single Pulse 0 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) LIMITED BY PACKAGE R D V DS V GS D.U.T. R G 0V Pulse Width µs Duty Factor 0. % Fig 0a. Switching Time Test Circuit V DS 90% V - DD T C, Case Temperature ( C) 0% V GS t d(on) t r t d(off) t f Fig 9. Maximum Drain Current Vs. Case Temperature Fig 0b. Switching Time Waveforms Thermal Response(Z thjc ) 0. D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J= P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 R G V DS 20V tp Fig 2a. Unclamped Inductive Test Circuit tp I AS L D.U.T 0.0Ω 5V V (BR)DSS DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) I D TOP 25A 44A BOTTOM 62A Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF 0 V Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 3a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS 7

8 D 2 Pak Package Outline.40 (.055) MAX (.45) 0.29 (.405) - A (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 0.6 (.400) REF (.255) 6.8 (.243).78 (.070).27 (.050) (.60) 4.73 (.580) 2.79 (.0) 2.29 (.090) 5.28 (.208) 4.78 (.88) 2.6 (.03) 2.32 (.09) 3X.40 (.055).4 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.08).39 (.055).4 (.045) 8.89 (.350) REF (.00) M B A M MINIMUM RECOMMENDED FOOTPRINT.43 (.450) NOTES: DIMENSIONS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS - GATE 2 - DRAIN 3 - SOURCE 8.89 (.350) 3.8 (.50) 7.78 (.700) 2.08 (.082) 2X 2.54 (.) 2X D 2 Pak Part Marking Information INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S B M PART NUMBER DATE CODE (YYW W ) YY = YEAR WW = WEEK 8 A

9 TO-262 Package Outline TO-262 Part Marking Information 9

10 D 2 Pak Tape & Reel Information TRR.60 (.063).50 (.059) 4.0 (.6) 3.90 (.53).60 (.063).50 (.059) (.045) (.035) FEED DIRECTION TRL.85 (.073).65 (.065) 0.90 (.429) 0.70 (.42).60 (.457).40 (.449) 6.0 (.634) 5.90 (.626).75 (.069).25 (.049) 5.42 (.609) 5.22 (.60) (.957) (.94) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) (.079) (.94) (4.73) MAX (2.362) MIN. NOTES :. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (.039) (.96) (.97) MAX. 4 Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) TAC Fax: (30) Visit us at for sales contact information.3/0 0