SMPS MOSFET. V DSS R DS(on) max I D

Transcription

1 Absolute Maximum Ratings SMPS MOSFET Applications l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l High Frequency Buck Converters for Server Processor Power Synchronous FET l Optimized for Synchronous Buck Converters Including Capacitive Induced Turn-on Immunity Benefits l Ultra-Low Gate Impedance l Very Low RDS(on) at 4.5V V GS l Fully Characterized Avalanche Voltage and Current IRF3711 IRF3711S IRF3711L HEXFET Power MOSFET V DSS R DS(on) max I D 20V 6.0mΩ 1A TO-220AB IRF3711 D 2 Pak IRF3711S PD D TO-262 IRF3711L Symbol Parameter Max. Units V DS Drain-Source Voltage 20 V V GS Gate-to-Source Voltage ± 20 V I T C = 25 C Continuous Drain Current, V V 1 I T C = 0 C Continuous Drain Current, V V 69 A I DM Pulsed Drain Current 440 P C = 25 C Maximum Power Dissipation 120 W P A = 25 C Maximum Power Dissipation 3.1 W Linear Derating Factor 0.96 W/ C T J, T STG Junction and Storage Temperature Range -55 to 150 C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.04 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 R θja Junction-to-Ambient (PCB mount) 40 Notes through are on page /9/04

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 20 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1mA V GS = V, I D = 15A ƒ R DS(on) Static Drain-to-Source On-Resistance mω V GS = 4.5V, I D = 12A ƒ V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA 20 V µa DS = 16V, V GS = 0V I DSS Drain-to-Source Leakage Current 0 V DS = 16V, V GS = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage 200 V GS = 16V na Gate-to-Source Reverse Leakage -200 V GS = -16V T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 53 S V DS = 16V, I D = 30A Q g Total Gate Charge I D = 15A Q gs Gate-to-Source Charge 7.3 nc V DS = V Q gd Gate-to-Drain ("Miller") Charge 8.9 V GS = 4.5V Q oss Output Gate Charge 33 V GS = 0V, V DS = V Rg Gate Resistance Ω t d(on) Turn-On Delay Time 12 V ns DD = V t r Rise Time 220 I D = 30A t d(off) Turn-Off Delay Time 17 R G = 1.8Ω t f Fall Time 12 V GS = 4.5V ƒ C iss Input Capacitance 2980 V GS = 0V C oss Output Capacitance 1770 pf V DS = V C rss Reverse Transfer Capacitance 280 ƒ = 1.0MHz Avalanche Characteristics Symbol Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 460 mj I AR Avalanche Current 30 A Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 1 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 440 (Body Diode) p-n junction diode. S V T J = 25 C, I S = 30A, V GS = 0V ƒ V SD Diode Forward Voltage 0.82 T J = 125 C, I S = 30A, V GS = 0V ƒ t rr Reverse Recovery Time ns T J = 25 C, I F = 16A, V R =V Q rr Reverse Recovery Charge nc di/dt = 0A/µs ƒ t rr Reverse Recovery Time ns T J = 125 C, I F = 16A, V R =V Q rr Reverse Recovery Charge nc di/dt = 0A/µs ƒ 2

3 I D, Drain-to-Source Current (A) 00 0 VGS TOP 15V V 4.5V 3.7V 3.5V 3.3V 3.0V BOTTOM 2.7V 2.7V I D, Drain-to-Source Current (A) 00 0 VGS TOP 15V V 4.5V 3.7V 3.5V 3.3V 3.0V BOTTOM 2.7V 2.7V 20µs PULSE WIDTH T J = 25 C V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 150 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 25 C T J = 150 C V DS= 25V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.0 I D = 1A V GS = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 I D, Drain-to-Source Current (A) C, Capacitance(pF) IRF3711/3711S/3711L V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 1 0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) I = D 30A V DS = 16V V DS = V 2 FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) T J= 150 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Voltage (V) Tc = 25 C Tj = 150 C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS (on) 0µsec 1msec msec 1 0 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 120 LIMITED BY PACKAGE V DS R D 0 V GS D.U.T. R G I D, Drain Current (A) V GS Pulse Width 1 µs Duty Factor 0.1 % Fig a. Switching Time Test Circuit - V DD 20 V DS 90% T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = SINGLE PULSE t (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t Peak T J = P DM x Z thjc TC t 1, Rectangular Pulse Duration (sec) PDM t1 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 R G V DS 20V tp Fig 12a. Unclamped Inductive Test Circuit tp L D.U.T IAS 0.01Ω 15V V (BR)DSS DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 13A 19A 30A Starting T, Junction Temperature ( J C) I AS Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF V GS Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs 7

8 TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information EXAMPLE: T HIS IS AN IRF LOT CODE 1789 AS S EMB LED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INTERNAT IONAL RECTIFIER LOGO AS S E MB L Y LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C 8

9 D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information T HIS IS AN IRF530S WIT H LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" Note: "P" in ass embly line position indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = ASSEMBLY SITE CODE 9

10 TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL33L LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = DESIGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE

11 D 2 Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4. (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065).90 (.429).70 (.421) (.457) (.449) 16. (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MAX (2.362) MIN. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 1.0mH R G = 25Ω, I AS = 30A. NOTES : 1. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) MAX. 4 ƒ Pulse width 400µs; duty cycle 2%. This is only applied to TO-220AB package This is applied to D 2 Pak, when mounted on 1" square PCB ( FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. R θ is measured at T J approximately 90 C Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.12/

12 Note: For the most current drawings please refer to the IR website at: