IRL3102S. HEXFET Power MOSFET V DSS = 20V. R DS(on) = 0.013W I D = 61A PRELIMINARY

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1 l l l l l Advanced Process Technology Surface Mount Optimized for 4.5V-7.0V Gate Drive Ideal for CPU Core DC-DC Converters Fast Switching Description These HEXFET Power MOSFETs were designed specifically to meet the demands of CPU core DC-DC converters. Advanced processing techniques combined with an optimized gate oxide design results in a die sized specifically to offer maximum efficiency at minimum cost. The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. PRELIMINARY G PD A IRL32S HEXFET Power MOSFET D S 2 D Pak V DSS = 20V R DS(on) = 0.013W I D = 61A Absolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V 4.5V 61 I T C = 0 C Continuous Drain Current, V 4.5V 39 A I DM Pulsed Drain Current 240 P C = 25 C Power Dissipation 89 W Linear Derating Factor 0.71 W/ C V GS Gate-to-Source Voltage ± V E AS Single Pulse Avalanche Energy 220 mj I AR Avalanche Current 35 A E AR Repetitive Avalanche Energy 8.9 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to T STG Storage Temperature Range Soldering Temperature, for seconds 300 (1.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R qjc Junction-to-Case 1.4 R qja Junction-to-Ambient ( PCB Mounted,steady-state)** 40 C/W 9/16/97

2 IRL32S Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 20 V V GS = 0V, I D = 250µA DV (BR)DSS /DT J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance V GS = 4.5V, I D = 37A W V GS = 7.0V, I D = 37A V GS(th) Gate Threshold Voltage 0.70 V V DS = V GS, I D = 250µA g fs Forward Transconductance 36 S V DS = 16V, I D = 35A I DSS Drain-to-Source Leakage Current 25 V DS = 20V, V GS = 0V µa 250 V DS = V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 V GS = V na Gate-to-Source Reverse Leakage -0 V GS = -V Q g Total Gate Charge 58 I D = 35A Q gs Gate-to-Source Charge 14 nc V DS = 16V Q gd Gate-to-Drain ("Miller") Charge 21 V GS = 4.5V, See Fig. 6 t d(on) Turn-On Delay Time V DD = V t r Rise Time 130 I ns D = 35A t d(off) Turn-Off Delay Time 80 R G = 9.0W, V GS = 4.5V t f L S Fall Time Internal Source Inductance nh R D = 0.28W, Between lead, and center of die contact C iss Input Capacitance 2500 V GS = 0V C oss Output Capacitance 00 pf V DS = 15V C rss Reverse Transfer Capacitance 360 ƒ = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 61 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 240 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 37A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 35A Q rr Reverse Recovery Charge nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.36mH R G = 25W, I AS = 35A. ƒ I SD 35A, di/dt 0A/µs, V DD V (BR)DSS, T J 150 C Pulse width 300µs; duty cycle 2%. Uses IRL32 data and test conditions ** When mounted on FR-4 board using minimum recommended footprint. For recommended footprint and soldering techniques refer to application note #AN-994.

3 ` IRL32S I D, Drain-to-Source Current (A) 00 0 VGS VGS TOP 15V TOP V 12V V 8.0V 8.0V 6.0V 6.0V 4.0V 4.0V 3.0V BOTTOM 3.0V 2.5V BOTTOM 2.5V 2.5V I D, Drain-to-Source Current (A) 00 0 VGS TOP 15V V 12V 8.0V V 8.0V 6.0V 6.0V 4.0V 4.0V 3.0V BOTTOM 3.0V 2.5V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH T J = 25 C V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 150 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 25 C T J = 150 C V DS= 15V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.0 I D = 61A V GS = 4.5V T J, Junction Temperature( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature

4 IRL32S C, Capacitance (pf) VGS = 0V, f = 1MHz Ciss = Cgs + Cgd, C ds Crss = Cgd Coss = Cds + Cgd C iss C oss C rss SHORTED V GS, Gate-to-Source Voltage (V) I D = 35A V DS = 16V V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 T J = 150 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us 1ms ms TC = 25 C TJ = 150 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

5 IRL32S I D, Drain Current (A) T C, Case Temperature ( C) E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 16A 22A 35A Starting T, Junction Temperature( J C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig. Maximum Avalanche Energy Vs. Drain Current Thermal Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc + TC t 1, Rectangular Pulse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 IRL32S (W) (W) R DS (on), Drain-to-Source On Resistance VGS = 4.5V VGS = 7.0V I D, Drain Current (A) R DS (on), Drain-to-Source On Resistance ID = 61A V GS, Gate-to-Source Voltage (V) Fig 12. On-Resistance Vs. Drain Current Fig 13. On-Resistance Vs. Gate Voltage

7 IRL32S D 2 Pak Package Outline 1.40 (.055) MAX..54 (.415).29 (.405) - A (.185) 4.20 (.165) - B (.052) 1.22 (.048).16 (.400) REF (.255) 6.18 (.243) 1.78 (.070) 1.27 (.050) (.6) (.580) 2.79 (.1) 2.29 (.090) 5.28 (.208) 4.78 (.188) 2.61 (.3) 2.32 (.091) 3X 1.40 (.055) 1.14 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.018) 1.39 (.055) 1.14 (.045) 8.89 (.350) REF (.0) M B A M MINIMUM RECOMMENDED FOOTPRINT (.450) NOTES: 1 DIMENSIO NS AFTER SOLDER DIP. 2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS. LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 8.89 (.350) 3.81 (.150) (.700) 2.08 (.082) 2X 2.54 (.0) 2X Part Marking Information D 2 Pak INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE F530S B 1M PART NUMBER DATE CODE (YYW W ) YY = YEAR WW = WEEK A

8 IRL32S Tape & Reel Information D 2 Pak TRR 1.60 (.063) 1.50 (.059) 4. (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) (.0145) (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065).90 (.429).70 (.421) (.457) (.449) 16. (.634) (.626) 1.75 (.069) 1.25 (.049) (.609) (.601) (.957) (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION (.532) (.504) (1.079) (.941) (14.173) MAX (2.362) MIN. NOTES : 1. CO M FO RM S TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (1.039) (.961) (1.197) MAX. 4 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (3) EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) IR GERMANY: Saalburgstrasse 157, Bad Homburg Tel: IR ITALY: Via Liguria 49, 071 Borgaro, Torino Tel: IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: IR SOUTHEAST ASIA: 315 Outram Road, #-02 Tan Boon Liat Building, Singapore 0316 Tel: Data and specifications subject to change without notice. 9/97

9 Note: For the most current drawings please refer to the IR website at: