SMPS MOSFET. V DSS R DS(on) typ. I D

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1 Absolute Maximum Ratings SMPS MOSFET PD 93923B IRFPS40N50L Applications HEXFET Power MOSFET l Switch Mode Power Supply (SMPS) l UninterruptIble Power Supply V DSS R DS(on) typ. I D l High Speed Power Switching 500V 0.087Ω 46A l ZVS and High Frequency Circuit l PWM Inverters Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Low Trr and Soft Diode Recovery l High Performance Optimised Antiparallel Diode SUPER TO247AC Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 46 I T C = 0 C Continuous Drain Current, V V 29 A I DM Pulsed Drain Current 80 P C = 25 C Power Dissipation 540 W Linear Derating Factor 4.3 W/ C V GS GatetoSource Voltage ± 30 V dv/dtpeak Diode Recovery dv/dt ƒ 25 V/ns T J Operating Junction and 55 to 50 T STG Storage Temperature Range Soldering Temperature, for seconds 300 C (.6mm from case ) Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 46 MOSFET symbol D (Body Diode) showing the A G I SM Pulsed Source Current 80 integral reverse (Body Diode) pn junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S = 46A, V GS = 0V t rr Reverse Recovery Time T J = 25 C I F = 46A ns T J = 25 C di/dt = 0A/µs nc T J = 25 C Q rr Reverse Recovery Charge µc T J = 25 C I RRM Reverse Recovery Current 9.0 A t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) Typical SMPS Topologies l Bridge Converters l All Zero Voltage Switching 05/09/0

2 T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 500 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.60 V/ C Reference to 25 C, I D = ma R DS(on) Static DraintoSource OnResistance Ω V GS = V, I D = 28A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA I DSS DraintoSource Leakage Current 50 µa V DS = 500V, V GS = 0V 2.0 ma V DS = 400V, V GS = 0V, T J = 25 C I GSS GatetoSource Forward Leakage 0 V GS = 30V na GatetoSource Reverse Leakage 0 V GS = 30V T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 2 S V DS = 50V, I D = 46A Q g Total Gate Charge 380 I D = 46A Q gs GatetoSource Charge 80 nc V DS = 400V Q gd GatetoDrain ("Miller") Charge 90 V GS = V, See Fig. 6 and 3 t d(on) TurnOn Delay Time 27 V DD = 250V t r Rise Time 70 ns I D = 46A t d(off) TurnOff Delay Time 50 R G = 0.85Ω t f Fall Time 69 V GS = V,See Fig. C iss Input Capacitance 8 V GS = 0V C oss Output Capacitance 960 V DS = 25V C rss Reverse Transfer Capacitance 30 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 200 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 240 V GS = 0V, V DS = 400V, ƒ =.0MHz C oss eff. Effective Output Capacitance 420 V GS = 0V, V DS = 0V to 400V Avalanche Characteristics Symbol Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 920 mj I AR Avalanche Current 46 A E AR Repetitive Avalanche Energy 54 mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc JunctiontoCase 0.23 R θcs CasetoSink, Flat, Greased Surface 0.24 C/W R θja JunctiontoAmbient 40 Notes: Repetitive rating; pulse width limited by max. junction temperature. (See Fig. ) Starting T J = 25 C, L = 0.86mH, R G = 25Ω, I AS = 46A (See Figure 2a) ƒ I SD 46A, di/dt 367A/µs, V DD V (BR)DSS, T J 50 C. Pulse width 400µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS 2

3 I D, DraintoSource Current (A) VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 4.5V I D, DraintoSource Current (A) 00 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 4.5V 20µs PULSE WIDTH 0.0 T J = 25 C 0. 0 V DS, DraintoSource Voltage (V) 20µs PULSE WIDTH T J = 50 C V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, DraintoSource Current (A) 00 0 T J = 50 C T J = 25 C V DS= 50V 20µs PULSE WIDTH V GS, GatetoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 3.0 I D = 47A V GS= V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature 3

4 C, Capacitance(pF) IRFPS40N50L V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 00 V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) I D = 47A V DS= 400V V DS= 250V V DS= 0V Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage I SD, Reverse Drain Current (A) 00 0 T J = 50 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Voltage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms TC = 25 C ms TJ = 50 C Single Pulse 0 00 V DS, DraintoSource Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 50 V DS R D I D, Drain Current (A) Fig a. Switching Time Test Circuit V DS 90% R G V GS V Pulse Width µs Duty Factor 0. % D.U.T. V DD T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t Peak T J =P DM x Z thjc TC t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase 5

6 E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 2A 30A 46A Starting T, Junction Temperature( J C) Fig 2a. Maximum Avalanche Energy Vs. Drain Current R G V DS 20V tp Fig 2c. Unclamped Inductive Test Circuit tp L D.U.T I AS 0.0Ω V (BR)DSS 5V DRIVER V DD A I AS Fig 2d. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF D.U.T. V DS V GS Q GS Q GD V GS V G 3mA I G I D Current Sampling Resistors Fig 3a. Gate Charge Test Circuit Charge Fig 3b. Basic Gate Charge Waveform 6

7 Peak Diode Recovery dv/dt Test Circuit IRFPS40N50L D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD ReApplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For NChannel HEXFET Power MOSFETs 7

8 SUPER TO247AC Package Outline Dimensions are shown in millimeters (inches) 2X R 3.00 [.8] 2.00 [.079] 6. [.632] 5. [.595] A 5.50 [.26] 4.50 [.78] 0.3 [.005] 2.5 [.084].45 [.058] 0.25 [.0] B A 3.90 [.547] 3.30 [.524].30 [.05] 0.70 [.028] [.88] 9.80 [.780] 4 6. [.633] 5.50 [.6] 4 C 2 3 B 4.80 [.582] 3.80 [.544] 4.25 [.67] 3.85 [.52] Ø.60 [.063] MAX. E E 5.45 [.25] 2X.60 [.062] 3X.45 [.058] 0.25 [.0] B A.30 [.05] 3X. [.044] 2.35 [.092].65 [.065] SECTION EE NOT ES :. DIMENS IONING AND TOLERANCING PER ASME Y4.5M DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES] 3. CONT ROLLING DIMENSION: MILLIMET ER 4. OUTLINE CONFORMS TO JEDEC OUTLINE TO274AA LE AD AS S IGNMENT S MOS FET IGBT GATE 2 DRAIN 3 SOURCE 4 DRAIN GATE 2 COLLECT OR 3 EMITTER 4 COLLECT OR Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.05/0 8