Advanced PDK and Technologies accessible through ASCENT
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1 Advanced PDK and Technologies accessible through ASCENT MOS-AK Dresden, Sept. 3, 2018 L. Perniola*, O. Rozeau*, O. Faynot*, T. Poiroux*, P. Roseingrave^ *Cea-Leti, Grenoble France; ^Tyndall, Cork, Ireland
2 The Challenge Increasingly (in)accessible nodes as scaling progresses IBS, July 2018
3 Nanowire Transistors, Colinge & Greer, Cambridge University Press 2016 The Challenge
4 A part of the solution an infrastructure for the global nanoelectronics modeling, characterization, and design communities Process & Technology Compact Models Circuit & System Design J. Greer, ESSDERC 2017 Technology Computer Aided Design
5 The Access Providers State-of-the-art 14 nm FDSOI CMOS & nanowire Advanced transistor and interconnect test structures Electrical & nanocharacterization platforms Fabrication facilities for nanowires & 2D materials Advanced nanowire and nano- electrode test structures Electrical & nanocharacterization platforms State-of-the-art 14 nm FinFET CMOS Advanced transistor and interconnect test structures Electrical & nanocharacterisation platforms
6 LETI offer Items for Device Analysis 300mm wafers with planar FDSOI and Nanowire devices SPICE models and model cards for digital: target and preliminary 14nm FDSOI 10nm FDSOI 10nm FFSOI 7 nm Stacked-nanowire TCAD decks FDSOI MOSFET Trigate SOI Nanowire GAA Nanowire MOSFET (mainly electrostatics)
7 LETI offer Items for Circuit Performance Analysis Preliminary PDK for Full custom IC design 14nm planar FDSOI technology 10nm planar FDSOI technology (preliminary) DK for IC demonstrators 28nm FDSOI technology (ST Microelectronics) Near future: PDK 10nm including libraries
8 LETI offer Electrical Characterisation Capabilities Parametric testers with 300mm full auto probers General purpose I(V)-C(V) 200/300mm testers Temperature range for test on wafers: 2K 600 C Test systems for memories HF tests up to 40 MHz, Noise measurements Reliability tests: hot carriers, TDDB, charge pumping, Internal Photo Emission Electrical test under calibrated strain High power tests (10kV, >100A) on 300mm prober Deep Level Transient Spectroscopy Electrostatic discharges, Electromigration 450m²
9 Example from Leti Nanowire wafer for characterisation Access to LETI 300mm wafers with Nanowire devices for characterization and study of advanced nanodevices in the characterization facilities of the Nanoelectronics Lab of Univ. Granada. Metal Deposition
10 Tyndall FlexiFab Range of cleanrooms designed for flexible process & product development Silicon MOS Fabrication MEMS Fabrication Compound Semiconductor Fabrication Photonics Fab Training Facility e-beam Lithography Non-standard nano-processing
11 Tyndall Offer Fab Access Access to Tyndall FlexiFab for non-standard processing Test Chips Si nano-wire test chips with range of devices Electrical Characterisation Access Access to Tyndall electrical test labs Physical Characterisation Access Access to Tyndall device characterisation facilities
![Ioff [A/µm] Imec s offer Fin & STI module NFET wells I/I PFET wells I/I Well RTA](/docs-images/90/103924219/images/12-1.jpg "Dummy gate NFET extension I/I PFET extension I/I Extension RTA NFET SiN dep &")
![Id_sat[µA/µm] State-of-the-art devices with dedicated experiments ready on 300mm](/docs-images/90/103924219/images/12-4.jpg "Silicon wafers.")
12 Ioff [A/µm] Imec s offer Fin & STI module NFET wells I/I PFET wells I/I Well RTA Dummy gate NFET extension I/I PFET extension I/I Extension RTA NFET SiN dep & etch NFET recess NFET epi PFET SiN dep & etch PFET recess PFET epi Laser anneal ILD0 RMG LI and BEOL nm fincd 45nm Fin Pitch Access to state of the art process technology NFET post epi PFET post epi Experiment 1 REF Chiarella et al, ESSDERC 16 Id_sat[µA/µm] State-of-the-art devices with dedicated experiments ready on 300mm Silicon wafers. Main features: Bulk finfet, Replacement Metal Gate, S/D epi with Local Interconnect and silicide-last integration using single metal BEOL
13 Imec s offer
14 How to Access Step 1 Sign Up Step 2 Enquire Step 3 Apply Step 4 Selection Step 5 Access Step 6 Report
15 Step 1- Sign-Up
16 347 members of ASCENT Network
17 Recent on-line survey to all members 68 replies Step 6 - User Feedback 85% : Yes, programme is relevant to their research 75% : Have not applied for access yet 44% : plan to apply 88% : Rated application process at highest option 100% : Would recommend this programme to colleagues
18 What s new for MOS-AK 2018 in Dresden? What s new for MOS-AK 2018 in Dresden? Leti presents an advanced SPICE model for 3D mosfets: the Nanowire Surface Potential Model (Leti-NSP)
19 Introduction State-of-the-art today for advanced design (<7 nm): BSIM-CMG, limited to FinFET and 1 squared NW Our solution is Leti-NSP model dedicated to advanced GAA MOSFET. Leti-NSP model can simulate: Vertically stacked GAA MOSFET (nanosheet and/or nanowire) Vertical channel GAA MOSFET (nanosheet and/or nanowire) FinFET / Trigate MOSFET (SOI & bulk) Vertically stacked GAA MOSFET Vertical channel GAA MOSFET FinFET/Trigate MOSFET
20 Innovative solution for SPICE modeling Advances offered by Leti-NSP: stacked nanosheet with variable W & Tch GAA MOSFET architecture and its asymptotic cases O. Rozeau, IEDM 2016 NSP model only supports all nanosheet GAA CMOS technologies
21 Overview of Model features (1/3) For all device sizes Model features: Leti-NSP model v1.0.0 Interface states Quantum mechanical effect (GAA, finfet) Channel doping effect Management of SiGe channel for pfet Mobility model including sidewall effects Temperature scaling and self-heating effect Mobility model including sidewall effects Validation of quantum confinement modeling Channel doping effect Introduction to Leti-NSP model for 3D MOSFETs June 1 st, 2018
22 Overview of Model features (2/3) Short channel effects Model features: Leti-NSP model v1.0.0 Threshold voltage roll-off L-scaling of mobility model Drain Induced Barrier Lowering Velocity saturation Channel length modulation in saturation Series resistances with bias dependence Introduction to Leti-NSP model for 3D MOSFETs June 1 st, 2018
23 Gate capacitance (ff) Gate resistance (W) Overview of Model features (3/3) Other parasitic effects Model features: Leti-NSP model v1.0.0 Inner and Outer fringe capacitances All external parasitic capacitances including device to substrate capacitances External access resistances Gate resistance with scaling effects Gate tunneling currents GIDL/GISL currents Junction currents and charges L g =30nm W=30nm FP=50nm XGW=20nm Symbols: RC-network Lines: analytical model Number of actives NC 3 vertically stacked NS Short channel MOSFET Symbols: TCAD Lines: model NGCON=1 NGCON=2 Dedicated instance parameters for all GAA geometries Gate voltage (V) Introduction to Leti-NSP model for 3D MOSFETs June 1 st, 2018
24 Code and user s manual Leti-NSP model: Verilog-A code and manual are available NSP model is ready for standardization (presented to the CMC) Introduction to Leti-NSP model for 3D MOSFETs August 28 th, 2018
25 Conclusion Highlights to Ascent & Advanced models: Ascent provides a unique platform for access to advanced technologies, electrical & physico-chemical characterization, models thanks to Leti, Tyndall and IMEC as leading European RTO & European subsidy 347 members have already joined.. Go ahead, join, to meet your own targets! As an example of offered platform within ASCENT advanced models Leti NSP Unique SPICE model for 3D Mosfets: from Symmetrical DG to Circular GAA, passing through different aspect ratio of nanosheet MOS Stacking possibility is enabled Fundamental effects included with brand-new emphasis triggered by customised device features (corner effect, quantum confinement, mobility degradation including sidewall effects ) Validated on several technologies.
26 Next step Join our community: Phone: Please join us in this exciting opportunity for nanoelectronics research
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