Failure Mechanisms and Robustness of Wide Band-Gap Devices under short-circuits and unclamped inductive switching

Transcription

1 Failure Mechanisms and Robustness of Wide Band-Gap Devices under short-circuits and unclamped inductive switching Stéphane Lefebvre (Cnam), Zoubir Khatir (IFSTTAR), Mounira Berkani (UPEC), Denis Labrousse (Cnam) 1

2 Motivations Emergence of different SiC devices (BJT, JFET, MOSFET ) Temperature limitation of SiC crystal extended to above 600 C A very higher robustness of SiC devices compared to Si is expected Robustness of SiC device technologies have to be evaluated Failure modes must be identified Robustness tests have been performed under : Current limitation and Short Circuit Unclamped inductive switching Ageing under repetitive SC or UIS has been also characterized 2

3 Outline 1. Robustness of SiC JFET, BJT and MOSFET under UIS 2. Robustness of SiC JFET, BJT and MOSFET under current limitation and short circuit 3. Indirect estimation of die temperature under short circuit at failure 4. Aluminum reconstruction 5. Ageing under UIS and SC 6. Conclusion 3

4 Robustness under UIS (Unclamped Inductive Switching) Normally-on 1200V Vertical JFET (Semithouth) Current Increase Failure IGBT Leakage current JFET 10 µs Failure Different transistors have been tested - JFET - BJT - MOSFET 4

5 Vertical Normally-on JFET under UIS No C OSS for these kind of devices resulting in Self Active Clamping C GD C GS Waveforms at failure Failure - No breakdown between Drain and Source (active clamping) - Avalanche current between Drain and Gate is controled by R G - J FET is working in a linear mode during avalanche - Very high Robustness of these devices in avalanche 5

6 Vertical Normally-on JFET under UIS Effect of gate resistance during intrinsic active clamping Rg = Ohm Control of the avalanche current By the gate resistance 6

7 Vertical Normally off JFET under UIS Effect of the current increase during UIS Conduction of the transistor during UIS, avalanche current through D DG controlled by the gate resistance Similar behavior of N_off devices Compared to N_on devices Ec = 227 mj 7

8 MOSFET under UIS - Different generations of different manufacturers have been characterized in UIS Very low robustness of 1 st generation of MOSFET_B (1200V at 150 C) 2 nd generation of MOSFET_B (25 C) Just before failure E c =36 mj MOSFET_A (25 C) Just after failure E failure = 254 mj Robustness depending on MOSFET technology 8

9 Robustness under Short-Circuit or Current limitation modes Circuit breaker Device under Test (DUT) Gate drive SC duration (control SC energy) off on Current limitation Device is maintained in on-state until failure Gate drive off on off Short Circuit Device is maintained in on-state during a short time Short circuit duration is increased until failure 9

10 Robustness of SiC JFET under current limitation mode 10 JFET from SiCED 1200V, 15A Failure after 0,7ms (400V) 2,4J (about 60 J.cm -2 ) Failure

11 Robustness of SiC JFET under current limitation mode 11 Tests condition for robustness evaluation E = 540V, T C = 25 C Tsc=2ms On-state polarization of the gate to source junction due to leakage current between Drain and Gate Short-Circuit Between Gate and Source Failure (60 J/cm²)

12 Robustness of SiC JFET under current limitation mode 12 Tests condition for robustness evaluation E = 540V, T C = 25 C Tsc=2ms T SC =600µs

13 Robustness of SiC JFET under current limitation mode 13 Tests condition for robustness evaluation E = 540V, T C = 25 C Tsc=2ms T SC =780µs

14 Robustness of SiC JFET under current limitation mode 14 Tests condition for robustness evaluation E = 540V, T C = 25 C Tsc=2ms Failure between Gate and Source preceeds the failure between Drain and Source Unable to switch off V GS V GS Ec = 40J/cm 2 Failure V DRIVER T SC =805µs

15 Robustness of SiC JFET under short-circuit Adding a Schottky diode To limit gate to source increase 15 On-state polarization of the gate to source junction due to leakage current between drain and gate

16 Robustness of SiC JFET under Short Circuit Critical Energy T CASE = 25 C, E = 540 V T SC = 940µs Short-circuit duration lightly higher (950µs) - For SC duration = 950 µs : Device is not able to turn-off the current - Failure of the gate after 940 µs of SC - Drain current remains limited until failure - Failure of the gate preceeding the failure between Drain and Source E C = 37 J/cm² (on active area) 16

17 Robustness of SiC Vertical JFET under Short Circuit When Short Circuit duration increases : - Increase of the gate to source voltage at turn-off (effect of the gate resistance) - Significant tail current JFET Normally_ON_#1 (110mΩ) JFET Normally_ON_#2 (85mΩ) - High temperature is responsible for leakage current in the DG junction - Voltage drop accross gate resistance - JFET are operating in a linear mode before failure 17

18 Robustness of SiC Vertical JFET under Short Circuit Failure Failure JFET Normally_ON_#1 JFET Normally_ON_#2 - High current after channel swith-off - JFET operating in a linear mode - No failure of the gate - Delayed failure mode after thermal runaway? 18

19 Voltage V CE (V) Robustness of SiC BJT under current limitation Current I C (A) Voltage V BE (V) Current I B (A) 19 Destructive test of 1200V BJT at T CASE = 25 C, I B = 0.2 A V CE I C 30 Failure of the die in the off-state I B V BE Short Circuit of Base to Emiter Junction Time ( s) Time ( s)

20 Voltage V CE (V) Current I C (A) Voltage V BE (V) Current I B (A) Robustness of SiC BJT under Current limitation Failure of SiC BJT: I B =0.6 A, T CASE =25 C, E dis = 240 mj; T CASE =150 C E dis = 203 mj 800 T = 25 C T = 150 C T = 25 C T = 150 C V CE I B I C Moderate effect of Temperature on the robustness Time ( s) 25 Failure of the die in the off state 0-5 V BE Failure of BE junction (SC) Time ( s) 0 - Good robustness of BJT in SC mode - Base current controls the SC current - Interesting failure in the open state (circuit reconfiguration) - Very well adapted for circuit breaker applications 20

21 Robustness of SiC MOSFET under current limitation and short-circuit 21 Different 1200V tested devices (Generation 1 & 2, A & B) Different robustness and failure modes

22 Robustness of SiC MOSFET under current limitation MOSFET B, E = 600V, T CASE = 25 C Short-Ciruit between Gate and Source : Failure of the gate Control of the collector current after Short-Ciruit between Gate and Source MOSFET B, E = 600V, T CASE = 150 C - Failure of the Gate - SC of the GS electrodes - High «leakage» current between G&S after failure - Transient leakage GS current during short circuit 22

23 Voltage V DS (V) Current I D (A) Voltage V GS (V) Current I G (A) Robustness of SiC MOSFET_A Under current limitation Failure of A-MOSFET: R G = 47Ω, T CASE = 25 C, E dis = 1153mJ; T= 150 C, E dis = 1128 mj 800 T = 25 C T = 150 C T = 25 C T = 150 C V DS V GS I D I G Time ( s) Time ( s) R G V Driver V GS Decrease of the Gate to Source Voltage results of a gate leakage current 23

24 Robustness of SiC MOSFET_A under current limitation Lower robustness at higher temperature 24 Increase of the drain currrent before failure : - Impact generation? Thermal generation? Temperature is too low - Diffusion current or other phenomenon? Gate Leakage current before failure : - Lower effect on V GS for R G = 10Ω - Degradation of the gate - Not necessary responsible for the failure

25 Robustness of SiC MOSFET_B under current limitation 25 Control of the Drain current with a high «leakage current» after turn-off Gate leakage current before failure Short circuit between Gate and Source at failure

26 Voltage V DS (V), V GS (VX20) Robustness of SiC MOSFET under Short Circuit Current I D (A) Voltage V DS (V), V GS (VX20) Current I D (A) MOSFET_A Failure in a SC mode between D&S MOSFET_B Failure in an open state between D&S 800 t sc = 10 s t sc = 11 s t sc = 12 s t sc = 10 s t sc = 11 s t sc = 12 s V DS V DS V GS failure V GS failure I D I D Time ( s) Time ( s) Delayed failure mode with short circuit between D&S and D&G Delayed failure mode with short circuit between G&S and no «failure» between D&S 26

27 Robustness of SiC MOSFET under Short Circuit 27 MOSFET B, E = 600V, T CASE = 25 C MOSFET B, E = 600V, T CASE = 150 C For high SC duration : - SC current is turned-off - Few μs after SC turn-off : Failure of the gate with a SC between Gate and Source - Delayed failure mode

28 Robustness of SiC MOSFET Under current limitation Microscoy from GPM Different failure modes depending on the manufacturer : - Failure after thermal runaway? and short circuit between D&S and D&G - Failure after SC between Gate and Source and open-state between D&S Very difficult to conclude : - Few tested devices - Technology not yet mature and rapidly changing 28

29 Saturation curent (A) Estimation of junction temperature during SC robustness tests Saturation curent (A) SiC JFET from SiCED (1200V 15A & 1300V 2A) E = 400V T cc =6µs Air streamer until 400 C Device Under Test Circuit breaker Short Circuit duration 1200V 15A JFET 1300V 2A JFET 25 C to 400 C by steps of 25 C 25 C to 400 C by steps of 25 C Time(µs) Time(µs) 29

30 Saturation curent (A) Saturation curent (A) Saturation curent (A) Estimation of junction temperature during SC robustness tests Under constant supply voltage, I SAT function of the temperature only 300 C < Temp < 350 C Over current due to the charge of C OSS 25 C 300 C 350 C Time(µs) 50 C Tamb = 25 C Fitted model 350 C I SAT I SAT exp( ) 0 0 Time(µs) Température ( C) 30

31 Estimation of junction temperature during SC robustness tests 31 Very high temperature at failure : - Similar to that encountered with Si devices - Close to aluminum melting temperature

32 Aluminum degradation during short-circuit Efficiency Aging of SJ MOSFET Under SC Al reconstruction Regular increase of metallization resistance 1,15J / Cycle After cycles Complete degradation of the Al layer 32

33 Aging of SIC devices under Short Circuit 33 - Dissipated energy << dissipated energy leading to one shot failure - Regular electrical characterizations during aging On-state resistance (T0247 or T0220) Including Source metalization and bond wire resistance R DSON Gate to Source resistance (JFET or BJT) R GS Including metalization and bond wire Resistance of Gate and Source Saturation current Leakage currents Threshold voltage

34 Aging of SIC JFET under SC E=540 V, Tc = 25 C, T SC = 200 µs (one shoot failure after 700 µs / 1300 µs) 200µs Repetition of the short circuit Until failure First observation is a significant decrease of the SC current during ageing After cycles 34

35 35 Aging of SIC JFET under SC E=540 V, Tc = 25 C, T SC = 200 µs R GS R DSON - Increase of the Gate to Source Resistance (40%) - Increase of the Drain to source Resistance (170%)

36 Aging of SIC JFET under SC E=540 V, Tc = 25 C, T SC = 200 µs Decrease of the saturation current Increase of Rsm and/or Rs-wire results in the decrease of Vgs-die in on-state Rsm : Source metallization resistance Rs-wire : Bond wire resistance - Significant decrease of the saturation current Which can be partially explained by the increase in the on-state resistance - Aluminum reconstruction and/or bond wire lift-off 36

37 Aging of SIC JFET under SC 37 Example of a representative failure First short-circuit After cycles Suddent increase of the gate to source voltage (~threshold voltage) Possible hypotheses : - Suddent apparition of a leakage current between source and gate which results (through Rg) in a return in conduction - Degradation of the gate pad passivations?

38 Aging of SIC JFET under SC 38 Failure after cycles V DS V GS don t cut off Failure of the gate Increase of I D I D V GS V DRIVER Failure Between D&S

39 Aging of SIC MOSFET under SC MOSFET_A R G Increase of V GS during ageing V Driver V GS 4.5µs Gate leakage current Drain leakage current Significant leakage current after more than 15 kcycles: Between Gate and Source (I GSS =10nA) and Drain and Source (I DSS > 300 µa) 39

40 Aging of SIC MOSFET under SC 40 R DSON = 41% Degradation of the source metallization or bond wires Aging : 0 à 21 kcc - High robustness of SiC MOSFET under repetitive Short Circuits - Weak of the gate - Gate leakage current seems to appear simultaneously with the device failure but is not necessary responsible for the failure Microscoy from GPM

41 Summary and conclusions Very high robustness of SiC JFET Similar robustness between Si and SiC devices for other devices? (J.cm -2 ) Melting of the aluminum metallization? Very interesting behavior of SiC BJT under short-circuit (control of the SC current by the base current) Failure of the BJT preceeding by a SC of the Base to Emitter junction resulting in the off-state failure between Collector and Emitter Similar results have been observed on MOSFET SiC for one manufacturer (physical short between Gate and Emitter?) Very interesting behavior of vertical JFET under UIS (self active clamping) 41