IRF3709ZCS IRF3709ZCL

Transcription

1 PD IRF3709ZCS IRF3709ZCL Applications l High Frequency Synchronous Buck Converters for Computer Processor Power HEXFET Power MOSFET V DSS R DSon) max Qg 30V 6.3m: 7nC Benefits l l l Low R DSon) at 4.5V V GS Low Gate Charge Fully Characterized Avalanche Voltage and Current D 2 Pak IRF3709ZCS TO-262 IRF3709ZCL Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 30 V V GS Gate-to-Source Voltage ± 20 I T C = 25 C Continuous Drain Current, V V 87h A I T C = 0 C Continuous Drain Current, V V 62h I DM Pulsed Drain Current c 350 P C = 25 C Maximum Power Dissipation 79 W P C = 0 C Maximum Power Dissipation Linear Derating Factor W C T J Operating Junction and -55 to 75 C T STG Storage Temperature Range Soldering Temperature, for seconds 300.6mm from case) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case i.89 CW R θja Junction-to-Ambient PCB Mount) g 40 Notes through are on page 604

2 T J = 25 C unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 30 V ΒV DSS T J Breakdown Voltage Temp. Coefficient 0.02 mv C Reference to 25 C, I D = ma R DSon) Static Drain-to-Source On-Resistance mω V GS = V, I D = 2A e V GS = 4.5V, I D = 7A e V GSth) Gate Threshold Voltage V V DS = V GS, I D = 250µA V GSth) T J Gate Threshold Voltage Coefficient -5.5 mv C I DSS Drain-to-Source Leakage Current.0 µa V DS = 24V, V GS = 0V 50 V DS = 24V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 0 na V GS = 20V Gate-to-Source Reverse Leakage -0 V GS = -20V gfs Forward Transconductance 88 S V DS = 5V, I D = 7A Q g Total Gate Charge 7 26 Q gs Pre-Vth Gate-to-Source Charge 4.4 V DS = 5V Q gs2 Post-Vth Gate-to-Source Charge.7 nc V GS = 4.5V Q gd Gate-to-Drain Charge 6.0 I D = 7A Q godr Gate Charge Overdrive 4.9 See Fig. 4a&b Q sw Switch Charge Q gs2 Q gd ) 7.7 Q oss Output Charge nc V DS = 6V, V GS = 0V t don) Turn-On Delay Time 3 V DD = 5V, V GS = 4.5V e t r Rise Time 4 I D = 7A t doff) Turn-Off Delay Time 6 ns Clamped Inductive Load t f Fall Time 4.7 C iss Input Capacitance 230 V GS = 0V C oss Output Capacitance 450 pf V DS = 5V C rss Reverse Transfer Capacitance 220 ƒ =.0MHz Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 60 mj I AR Avalanche Currentc 7 A E AR Repetitive Avalanche Energy c 7.9 mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 87h Body Diode) A I SM Pulsed Source Current 350 Body Diode)c V SD Diode Forward Voltage.0 V t rr Reverse Recovery Time 6 24 ns Q rr Reverse Recovery Charge nc Conditions V GS = 0V, I D = 250µA Conditions MOSFET symbol showing the integral reverse p-n junction diode. T J = 25 C, I S = 7A, V GS = 0V e T J = 25 C, I F = 7A, V DD = 5V didt = 0Aµs e G D S 2

3 I D, Drain-to-Source Current Α) R DSon), Drain-to-Source On Resistance Normalized) I D, Drain-to-Source Current A) I D, Drain-to-Source Current A) 00 VGS TOP V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 00 0 VGS TOP V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 0 3.0V 3.0V 60µs PULSE WIDTH Tj = 25 C 0. 0 V DS, Drain-to-Source Voltage V) 60µs PULSE WIDTH Tj = 75 C 0. 0 V DS, Drain-to-Source Voltage V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 00 0 T J = 75 C 2.0 I D = 42A V GS = V.5 0. T J = 25 C V DS = 5V 60µs PULSE WIDTH V GS, Gate-to-Source Voltage V) T J, Junction Temperature C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I SD, Reverse Drain Current A) I D, Drain-to-Source Current A) C, CapacitancepF) V GS, Gate-to-Source Voltage V) 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 7A V DS = 24V V DS = 5V C iss C oss 2.0 C rss V DS, Drain-to-Source Voltage V) Q G Total Gate Charge nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS on) 0.00 T J = 75 C 0 0µsec.00 T J = 25 C V GS = 0V V SD, Source-to-Drain Voltage V) 0. Tc = 25 C Tj = 75 C Single Pulse msec msec V DS, Drain-to-Source Voltage V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current A) V GSth) Gate threshold Voltage V) Limited By Package I D = 250µA T C, Case Temperature C) T J, Temperature C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Threshold Voltage vs. Temperature D = 0.50 Thermal Response Z thjc ) R R 2 R R 2 τ J τ J τ τ τ 2 τ 2 Ci= τiri Ci iri SINGLE PULSE THERMAL RESPONSE ) Notes:. Duty Factor D = tt2 2. Peak Tj = P dm x Zthjc Tc E-006 E t, Rectangular Pulse Duration sec) Ri CW) τi sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case τ C τ 5

6 E AS, Single Pulse Avalanche Energy mj) R DS on), Drain-to -Source On Resistance mω) T J = 25 C Vgs = V R DSon), Drain-to -Source On Resistance m Ω) I D = 2A T J = 25 C T J = 25 C T J = 25 C I D, Drain Current A) V GS, Gate -to -Source Voltage V) Fig 2. On-Resistance vs. Drain Current Fig 3. On-Resistance vs. Gate Voltage Current Regulator Same Type as D.U.T. 50KΩ Vds Id 2V V GS.2µF 3mA.3µF D.U.T. V - DS Vgsth) Vgs I D TOP 5.4A 8.0A BOTTOM 7A I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 4a&b. Basic Gate Charge Test Circuit and Waveform V tp V BR)DSS V DS L DRIVER 50 I AS R G 20V tp D.U.T I AS 0.0Ω - V DD A Starting T J, Junction Temperature C) Fig 5a&b. Unclamped Inductive Test circuit and Waveforms Fig 6. Maximum Avalanche Energy vs. Drain Current 6

7 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current didt D.U.T. V DS Waveform Diode Recovery dvdt D = P.W. Period V GS =V V DD * R G dvdt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 7. Peak Diode Recovery dvdt Test Circuit for N-Channel HEXFET Power MOSFETs V DS L D V DD - V GS Pulse Width < µs Duty Factor < 0.% D.U.T Fig 8a. Switching Time Test Circuit V DS 90% % V GS t don) t r t doff) t f Fig 8b. Switching Time Waveforms 7

8 Power MOSFET Selection for Non-Isolated DCDC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q and Q2. Power losses in the high side switch Q, also called the Control FET, are impacted by the R dson) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = I 2 rms R dson ) ) I Q gd V in f i g ) Q g V g f Q oss 2 V f in I Q gs2 i g V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs and Q gs2, can be seen from Fig 6. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ) P loss = I rms 2 Rdson) ) Q g V g f Q oss 2 V in f Q rr V in f *dissipated primarily in Q. ) For the synchronous MOSFET Q2, R dson) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdvdt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q turns on and off there is a rate of change of drain voltage dvdt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd Q gs must be minimized to reduce the potential for Cdvdt turn on. Figure A: Q oss Characteristic 8

9 D 2 Pak Package Outline Dimensions are shown in millimeters inches) D 2 Pak Part Marking Information UCDTDT6IDSA"TXDUC GPU8P9@'!# 6TT@H7G@9PIXX!! DIUC@6TT@H7G`GDI@G DIU@SI6UDPI6G S@8UDAD@S GPBP A"T Q6SUIVH7@S 96U@8P9@ 6TT@H7G` GPU8P9@ `@6S2! X@@F! GDI@G 9

10 TO-262 Package Outline Dimensions are shown in millimeters inches) IGBT - GATE 2- COLLEC- TOR TO-262 Part Marking Information,5,6, ; 5 % ' & 7 2 5,2 2 7,,) * &, : : 2 ' 0% 6 &, < 0% 6 7, ' 2 & 7 ' 5. &, < : < % 0 6 ' 7 &2 2

11 D 2 Pak Tape & Reel Information Dimensions are shown in millimeters inches) TRR ) ) 4..6) ) ) ) ) ) FEED DIRECTION TRL ) ) ).70.42) ) ) ) ) ) ) ) ) ) ) ) ) FEED DIRECTION ) ) ) ) ) MAX ) MIN. NOTES :. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE ) ) ) MAX. 4 Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.42mH, R G = 25Ω, I AS = 7A. ƒ Pulse width 400µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. This is applied to D 2 Pak, when mounted on " square PCB FR- 4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 42A. R θ is measured at T J of approximately 90 C. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: 3) TAC Fax: 3) Visit us at for sales contact information

12 Note: For the most current drawings please refer to the IR website at: