TO-220AB IRFB4410. W/ C V GS Gate-to-Source Voltage ± 20 dv/dt Peak Diode Recovery f 19

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1 Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability G D S V DSS D IRFB44 IRFS44 IRFSL44 HEXFET Power MOSFET V R DS(on) typ. 8.m: max. m: 96A I D PD C S D G TO-22AB IRFB44 S G D 2 Pak IRFS44 S D G TO-262 IRFSL44 Absolute Maximum Ratings Symbol Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 96c A I T C = C Continuous Drain Current, V V 68c I DM Pulsed Drain Current d 38 P C = 25 C Maximum Power Dissipation 25 W Linear Derating Factor.6 W/ C V GS Gate-to-Source Voltage ± 2 V dv/dt Peak Diode Recovery f 9 V/ns T J Operating Junction and -55 to + 75 C T STG Storage Temperature Range Soldering Temperature, for seconds (.6mm from case) Mounting torque, 6-32 or M3 screw 3 lbxin (.Nxm) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 22 mj I AR Avalanche Currentc See Fig. 4, 5, 6a, 6b A E AR Repetitive Avalanche Energy g mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc Junction-to-Case k.6 R θcs Case-to-Sink, Flat Greased Surface, TO-22.5 C/W R θja Junction-to-Ambient, TO-22 k 62 R θja Junction-to-Ambient (PCB Mount), D 2 Pak jk 4 5/2/7

2 IRFB44/IRFS44/IRFSL44 T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage V V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.94 V/ C Reference to 25 C, I D = mad R DS(on) Static Drain-to-Source On-Resistance 8. mω V GS = V, I D = 58A g V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 5µA I DSS Drain-to-Source Leakage Current 2 µa V DS = V, V GS = V 25 V DS = V, V GS = V, T J = 25 C I GSS Gate-to-Source Forward Leakage 2 na V GS = 2V Gate-to-Source Reverse Leakage -2 V GS = -2V R G Gate Input Resistance.5 Ω f = MHz, open drain T J = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 2 S Q g Total Gate Charge 2 8 nc Q gs Gate-to-Source Charge 3 Q gd Gate-to-Drain ("Miller") Charge 44 t d(on) Turn-On Delay Time 24 ns t r Rise Time 8 t d(off) Turn-Off Delay Time 55 t f Fall Time 5 C iss Input Capacitance 55 pf C oss Output Capacitance 36 C rss Reverse Transfer Capacitance 9 C oss eff. (ER) Effective Output Capacitance (Energy Related) 42 C oss eff. (TR) Effective Output Capacitance (Time Related)h 5 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 96c A Conditions V DS = 5V, I D = 58A I D = 58A V DS = 8V V GS = V g V DD = 65V I D = 58A R G = 4.Ω V GS = V g V GS = V V DS = 5V ƒ =.MHz V GS = V, V DS = V to 8V i, See Fig. V GS = V, V DS = V to 8V h, See Fig. 5 Conditions MOSFET symbol (Body Diode) showing the I SM Pulsed Source Current 38 A integral reverse G (Body Diode)d p-n junction diode. V SD Diode Forward Voltage.3 V T J = 25 C, I S = 58A, V GS = V g t rr Reverse Recovery Time ns T J = 25 C V R = 85V, 5 77 T J = 25 C I F = 58A Q rr Reverse Recovery Charge 6 92 nc T J = 25 C di/dt = A/µs g 7 T J = 25 C I RRM Reverse Recovery Current 2.8 A T J = 25 C t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) D S Notes: Calculated continuous current based on maximum allowable junction C oss eff. (TR) is a fixed capacitance that gives the same charging time temperature. Package limitation current is 75A. as C oss while V DS is rising from to 8% V DSS. Repetitive rating; pulse width limited by max. junction C oss eff. (ER) is a fixed capacitance that gives the same energy as temperature. C oss while V DS is rising from to 8% V DSS. ƒ Limited by T Jmax, starting T J = 25 C, L =.4mH ˆ When mounted on " square PCB (FR-4 or G- Material). For recommended R G = 25Ω, I AS = 58A, V GS =V. Part not recommended for use footprint and soldering techniques refer to application note #AN-994. above this value. R θ is measured at T J approximately 9 C. I SD 58A, di/dt 65A/µs, V DD V (BR)DSS, T J 75 C. Pulse width 4µs; duty cycle 2%. 2

3 C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFB44/IRFS44/IRFSL44 VGS TOP 5V V 8.V 6.V 5.5V 5.V 4.8V BOTTOM 4.5V VGS TOP 5V V 8.V 6.V 5.5V 5.V 4.8V BOTTOM 4.5V 4.5V 6µs PULSE WIDTH Tj = 25 C.. V DS, Drain-to-Source Voltage (V) 4.5V 6µs PULSE WIDTH Tj = 75 C. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 58A V GS = V T J = 75 C 2. T J = 25 C V DS = 25V 6µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics T J, Junction Temperature ( C) Fig 4. Normalized On-Resistance vs. Temperature V GS = V, f = MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd I D = 58A V DS = 8V V DS = 5V V DS = 2V C iss 6. C oss 4. C rss V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3

4 Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) Drain-to-Source Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) IRFB44/IRFS44/IRFSL44 OPERATION IN THIS AREA LIMITED BY R DS (on) µsec T J = 75 C msec T J = 25 C msec DC V GS = V V SD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Tc = 25 C Tj = 75 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area 9 8 Limited By Package T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature T J, Temperature ( C ) Fig. Drain-to-Source Breakdown Voltage I D TOP 6.7A 9.7A BOTTOM 58A V DS, Drain-to-Source Voltage (V) Starting T J, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy vs. DrainCurrent 4

5 E AR, Avalanche Energy (mj) Avalanche Current (A) IRFB44/IRFS44/IRFSL44 Thermal Response ( Z thjc ) D = R R 2 R R 2 τ J τ J τ τ τ 2 τ 2 τ C τ Ri ( C/W) τi (sec) Ci= τi/ri Ci i/ri. SINGLE PULSE ( THERMAL RESPONSE ) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc + Tc. E-6 E t, Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Case Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 5 C and Tstart =25 C (Single Pulse)..5. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τj = 25 C and Tstart = 5 C E-6.E-5.E-4.E-3.E-2.E- TOP Single Pulse BOTTOM % Duty Cycle I D = 58A Starting T J, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature tav (sec) Fig 4. Typical Avalanche Current vs.pulsewidth Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN-5 at Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as neither T jmax nor Iav (max) is exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av 5

6 Qrr (nc) I RRM (A) Qrr (nc) V GS(th) Gate threshold Voltage (V) I RRM (A) IRFB44/IRFS44/IRFSL I D = 5µA 2.5 I D = 25µA I D =.ma 2. I D =.A T J, Temperature ( C ) Fig 6. Threshold Voltage vs. Temperature 2 I 5 F = 9A V R = 85V T = 25 C J T = 25 C J di f /dt (A/µs) Fig. 7 - Typical Recovery Current vs. di f /dt I F = 38A V = 85V R T = 25 C J T J = 25 C di f /dt (A/µs) Fig. 8 - Typical Recovery Current vs. di f /dt I F = 9A V R = 85V T = 25 C 5 J T = 25 C J di f /dt (A/µs) Fig. 9 - Typical Stored Charge vs. di f /dt I = 38A F V = 85V R T J = 25 C T J = 25 C di f /dt (A/µs) Fig. 2 - Typical Stored Charge vs. di f /dt 6

7 IRFB44/IRFS44/IRFSL D.U.T + ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - + Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD + - Re-Applied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T IAS.Ω + - V DD A I AS Fig 2a. Unclamped Inductive Test Circuit Fig 2b. Unclamped Inductive Waveforms L D V DS V DD + - V DS 9% D.U.T % V GS Pulse Width < µs Duty Factor <.% V GS t d(on) t r t d(off) t f Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms Vds Id Vgs K DUT L VCC Vgs(th) Qgs Qgs2 Qgd Qgodr Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform 7

8 IRFB44/IRFS44/IRFSL44 TO-22AB Package Outline Dimensions are shown in millimeters (inches) TO-22AB Part Marking Information (;$3/( 7+,6,6$,5) $66(%/('2::,7+($66(%/</,(& RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,7(5$7,2$/ 5(&7,),(5 /2*2 $66(%/< 3$578%(5 '$7(&2'( <($5 :((. /,(& TO-22AB packages are not recommended for Surface Mount Application. 8

9 IRFB44/IRFS44/IRFSL44 TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information (;$3/( 7+,6,6$,5// $66(%/('2::,7+($66(%/</,(&,7(5$7,2$/ 5(&7,),(5 /2*2 $66(%/< 3$578%(5 '$7(&2'( <($5 :((. /,(& 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(%/< 3$578%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ <($5 :((. $ $66(%/<6,7(&2'( 9

10 IRFB44/IRFS44/IRFSL44 D 2 Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D 2 Pak (TO-263AB) Part Marking Information 7+,6,6$,5)6:,7+,7(5$7,2$/ $66(%/('2:: 5(&7,),(5,7+($66(%/</,(/ /2*2 $66(%/< )6 3$578%(5 '$7(&2'( <($5 :((. /,(/ 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(%/< 3$578%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ <($5 :((. $ $66(%/<6,7(&2'( )6

11 IRFB44/IRFS44/IRFSL44 D 2 Pak (TO-263AB) Tape & Reel Information TRR.6 (.63).5 (.59) 4. (.6) 3.9 (.53).6 (.63).5 (.59).368 (.45).342 (.35) FEED DIRECTION TRL.85 (.73).65 (.65).6 (.457).4 (.449) 5.42 (.69) 5.22 (.6) 24.3 (.957) 23.9 (.94).9 (.429).7 (.42) 6. (.634) 5.9 (.626).75 (.69).25 (.49) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.5 (.532) 2.8 (.54) 27.4 (.79) 23.9 (.94) (4.73) MAX. 6. (2.362) MIN. NOTES :. COMFORMS TO EIA CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION HUB. 4. INCLUDES FLANGE OUTER EDGE (.39) 24.4 (.96) (.97) MAX. 4 Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. 5/7

12 Note: For the most current drawings please refer to the IR website at:

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