8 S1, D2. Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )

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1 Co-Pack Dual N-channel HEXFET Power MOSFET and Schottky Diode Ideal for Synchronous Buck DC-DC Converters Up to A Peak Output Low Conduction Losses Low Switching Losses Low Vf Schottky Rectifier D D 2 G 3 G2 4 S2 5 S2 6 S2 7 Q Q2 4 S, D2 3 S, D2 2 S, D2 S, D2 S, D2 9 S, D2 8 S, D2 PD IRF7335D Dual FETKY Co-Packaged Dual MOSFET Plus Schottky Diode Device Ratings (Typ.Values) Q Q2 and Schottky R DS(on) 3.4 mω 9.6 mω Q G 3 nc 8 nc Q sw 5.5 nc 6.4 nc V SD.V.43V Description The FETKY family of Co-Pack HEXFET MOSFETs and Schottky diodes offers the designer an innovative, board space saving solution for switching regulator and power management applications. Advanced HEXFET MOSFETs combined with low forward drop Schottky results in an extremely efficient device suitable for a wide variety of portable electronics applications. The SO-4 has been modified through a customized leadframe for enhanced thermal characteristics and multiple die capability making it ideal in a variety of power applications. With these improvements multiple devices can be used in an application with dramatically reduced board space. Internal connections enable easier board layout design with reduced stray inductance. Absolute Maximum Ratings Parameter Max. Units V DS Drain-Source Voltage 3 V I T A = 25 C Continuous Drain Current, V V I T A = 7 C Continuous Drain Current, V V 8. A I DM Pulsed Drain Current 8 P A = 25 C Power Dissipation ƒ 2. W P A = 7 C Power Dissipationƒ.3 Linear Derating Factor.2 W/ C V GS Gate-to-Source Voltage ± 2 V E AS (6 sigma) Single Pulse Avalanche Energy 5 mj T J Operating Junction and -55 to + 5 T STG Storage Temperature Range Soldering Temperature, for seconds 3 (.6mm from case ) C Thermal Resistance Symbol Parameter Typ. Max. Units R θjl Junction-to-Drain Lead 2 R θja Junction-to-Ambient ƒ 62.5 C/W Notes through are on page 2 9//2

2 IRF7335D Electrical Characteristics Q-Control FET Q2-Synch FET & Schottky Parameter Min Typ Max Min Typ Max Units Conditions Drain-to-Source BV DSS 3 3 V V GS = V, I D = 25µA Breakdown Voltage Breakdown Voltage BV DSS/ T J V Reference to 25 C, I D =.ma Tem. Coefficient Static Drain-Source R DS(on) mω V GS =, I D = A on Resistance Gate Threshold Voltage V GS(th).. V V DS = V GS,I D = 25µA Drain-Source Leakage I DSS 3 3 µa V DS = 24V, V GS = Current.3 ma V DS = 24V, V GS =, Tj = 25 C Gate-Source Leakage I GSS ± ± na V GS = ±2V Current Forward Transconductance g FS 2 28 S V GS =5V, I D =8.A, V DS =5V Total Gate Charge Q G V GS =, I D =8.A, V DS =5V Pre-Vth Q GS Gate-Source Charge Post-Vth Q GS2.4.5 nc Gate-Source Charge Gate to Drain Charge Q GD Switch Chg(Q gs2 + Q gd ) Q sw Output Charge Q oss 7.7 nc V DS = 6V, V GS = Gate Resistance R G Ω Turn-on Delay Time t d (on) V DD = 6V, I D = 8.A Rise Time t r ns V GS = Turn-off Delay Time t d (off) 9 7 Clamped Inductive Load Fall Time t f Input Capacitance C iss 5 23 Output Capacitance C oss 3 45 pf V DS = 5V, V GS = Reverse Transfer Capacitance C rss 4 8 Source-Drain Rating & Characteristics Parameter Min Typ Max Min Typ Max Units Conditions D Continuous Source Current I S A MOSFET symbol (Body Diode) showing the G Pulse Source Current I SM 8 8 intergral reverse (Body Diode) p-n junction diode S Diode Forward Voltage V SD V T J = 25 C, I S =.A,V GS = V Reverse Recovery Time t rr 28 3 ns T J = 25 C, I F = 8.A, V R = 5V Reverse Recovery Charge Q rr nc di/dt = A/µs Reverse Recovery Time t rr 29 3 ns T J = 25 C, I F =8.A, V R = 5V Reverse Recovery Charge Q rr nc di/dt =A/µs 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (Α) Typical Characteristics IRF7335D TOP V 5.V 3.V 2.7V 2.2V BOTTOM 2.V Q - Control FET Q2 - Synchronous FET & Schottky TOP 2V V 8.V 3.5V 3.V BOTTOM 2.25V 2.V 2µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.25V 2µs PULSE WIDTH Tj = 25 C TOP V 5.V 3.V 2.7V 2.2V BOTTOM 2.V TOP 2V V 8.V 3.5V 3.V BOTTOM 2.25V 2.V 2.25V. V DS, Drain-to-Source Voltage (V) Fig 3. Typical Output Characteristics T J = 5 C 2µs PULSE WIDTH Tj = 5 C. 2µs PULSE WIDTH Tj = 5 C V DS, Drain-to-Source Voltage (V) Fig 4. Typical Output Characteristics. T J = 5 C.. T J = 25 C. T J = 25 C V DS = 5V V DS = 5V 2µs PULSE WIDTH. 2µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) Fig 5. Typical Transfer Characteristics Fig 6. Typical Transfer Characteristics 3

4 I SD, Reverse Drain Current (A) I D Drain-to-Source Current (A) I D Drain-to-Source Current (A) I D Drain-to-Source Current (A) I SD, Reverse Drain Current (A) I D Drain-to-Source Current (A) IRF7335D Q - Control FET Typical Characteristics Q2 - Synchronous FET & Schottky TOP 7.5V 3.5V 2.V.5V.V BOTTOM.V TOP 7.5V 3.5V 2.V.5V.V BOTTOM.V 2µs PULSE WIDTH Tj = 25 C µs PULSE WIDTH Tj = 25 C V SD Source-to-Drain Voltage (V) V SD Source-to-Drain Voltage (V) Fig. 7. Typical Reverse Output Characteristics Fig. 8. Typical Reverse Output Characteristics TOP 7.5V 3.5V 2.V.5V.V BOTTOM.V TOP 7.5V 3.5V 2.V.5V.V BOTTOM.V 2 2µs PULSE WIDTH Tj = 5 C V SD Source-to-Drain Voltage (V) 2µs PULSE WIDTH Tj = 5 C V SD Source-to-Drain Voltage (V) Fig. 9. Typical Reverse Output Characteristics Fig.. Typical Reverse Output Characteristics. 2. T J = 5 C.. T J = 5 C. T J = 25 C. T J = 25 C V GS = V V SD, Source-toDrain Voltage (V) V GS = V V SD, Source-toDrain Voltage (V) Fig. Typical Source-Drain Diode Forward Voltage Fig 2. Typical Source-Drain Diode Forward Voltage 4

5 I D, Drain-to-Source Current (A) V GS, Gate-to-Source Voltage (V) C, Capacitance (pf) I D, Drain-to-Source Current (A) C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) Q - Control FET Typical Characteristics IRF7335D Q2 - Synchronous FET & Schottky 25 V GS = V, f = MHZ 4 V GS = V, f = MHZ 2 C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 35 3 C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 5 Ciss 25 2 Ciss 5 5 Coss Crss 5 Coss Crss V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig 3. Typical Capacitance Vs.Drain-to-Source Voltage Fig 4. Typical Capacitance Vs.Drain-to-Source Voltage 2 I D = 8.A V DS = 24V VDS= 5V 2 I D = 8.A V DS = 24V VDS= 5V Q G Total Gate Charge (nc) Q G Total Gate Charge (nc) Fig. 5. Gate-to-Source Voltage vs Typical Gate Charge Fig. 6. Gate-to-Source Voltage vs Typical Gate Charge OPERATION IN THIS AREA LIMITED BY R DS (on) OPERATION IN THIS AREA LIMITED BY R DS (on) µsec µsec msec msec msec Tc = 25 C Tj = 5 C Single Pulse.... V DS, Drain-toSource Voltage (V) Fig 7. Maximum Safe Operating Area msec Tc = 25 C Tj = 5 C Single Pulse.... V DS, Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area 5

6 R DS(on), Drain-to -Source On Resistance ( Ω) R DS(on), Drain-to -Source On Resistance ( Ω) R DS ( on), Drain-to-Source On Resistance ( Ω) R DS(on), Drain-to-Source On Resistance (Normalized) R DS (on), Drain-to-Source On Resistance ( Ω) IRF7335D Typical Characteristics Q - Control FET Q2 - Synchronous FET & Schottky 2. I D = A V GS = 2. I D = A V GS = T, Junction Temperature ( J C) T J, Junction Temperature ( C) Fig 9. Normalized On-Resistance Vs. Temperature Fig 2. Normalized On-Resistance Vs. Temperature R DS(on), Drain-to-Source On Resistance (Normalized) V GS =.2. V GS= I D, Drain Current (A) I D, Drain Current (A) Fig 2. Typical On-Resistance Vs. Drain Current Fig 22. Typical On-Resistance Vs. Drain Current I D = A I D = A V GS, Gate -to -Source Voltage (V) V GS, Gate -to -Source Voltage (V) Fig 23. Typical On-Resistance Vs. Gate Voltage Fig 24. Typical On-Resistance Vs. Gate Voltage 6

7 I D, Drain Current (A) IRF7335D 2 V DS R D 8 R G V GS D.U.T V DD T J, Junction Temperature ( C) Fig 25. Maximum Drain Current Vs.CaseTemperature V DS 9% V GS Pulse Width µs Duty Factor % Fig 26a. Switching Time Test Circuit % V GS t d(on) t r t d(off) t f Current Regulator Same Type as D.U.T. Fig 26b. Switching Time Waveforms 5KΩ V GS Q G 2V.2µF.3µF D.U.T. + V - DS V G Q GS Q GD V GS 3mA Charge I G I D Current Sampling Resistors Fig 27a&b. Basic Gate Charge Test Circuit and Waveform Thermal Response ( Z thja ) D = SINGLE PULSE ( THERMAL RESPONSE ). E-6 E-5... t, Rectangular Pulse Duration (sec) Fig. 28. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 7

8 Instantaneous Forward Current - I F ( A ) Reverse Current - I R (µa ) IRF7335D Schottky Diode Characteristics Tj = 5 C 25 C C 75 C 5 C 25 C Reverse Voltage - V R (V) T J = 5 C T J = 25 C Fig. 3 - Typical Values of Reverse Current Vs. Reverse Voltage T J = 25 C Forward Voltage Drop - V F ( V ) Fig Maximum Forward Voltage Drop Characteristics 8

9 IRF7335D + - D.U.T + ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - + Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig. 3 Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs Qgs2 Qgd Qgodr Fig. 32 Gate Charge Waveform 9

10 IRF7335D Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q and Q2. Power losses in the high side switch Q, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q are given by; P loss = P conduction + P switching + P drive + P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) + I Q gd V in f + I Q gs 2 V in f i g ( ) + Q g V g f + Q oss 2 V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs and Q gs2, can be seen from Fig 6. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. i g Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction + P drive + P output ( ) P loss = I rms 2 R ds(on) ( ) + Q g V g f + Q oss 2 V f in + Q V f rr in *dissipated primarily in Q. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Q oss Characteristic

11 IRF7335D SO-4 Package Details SO-4 Part Marking

12 IRF7335D SO-4 Tape and Reel Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width 3 µs; duty cycle 2%. ƒ When mounted on inch square copper board. Combined Q,Q2 I Pwr V out pins. Calculated continuous current based on max allowable junction temperature; switching or other losses will decrease RMS current capability Q and Q2 is tested % in production to 5mJ to stress and eliminate potentially defective parts. This is not a design for use value. Data and specifications subject to change without notice. This product has been designed and qualified for the consumer market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.9/2 2