V DSS R DS(on) max (mw)

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1 Typical Applications Relay replacement Anti-lock Braking System Air Bag Benefits Advanced Process Technology Ultra Low On-Resistance Fast Switching Repetitive Avalanche Allowed up to Tjmax AUTOMOTIVE MOSFET PD A HEXFET Power MOSFET V DSS R DS(on) max (mw) I D 40V 0@V GS = 7.0V 4A A 8 S D Description Specifically designed for Automotive applications, this Stripe Planar design of HEXFET Power MOSFETs utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 50 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. S S G Top View D D D SO-8 Absolute Maximum Ratings Parameter Max. Units I T A = 25 C Continuous Drain Current, V 0V 4 I T A = 70 C Continuous Drain Current, V 0V A I DM Pulsed Drain Current 0 P A = 25 C Power Dissipationƒ 2.5 W Linear Derating Factor 0.02 W/ C V GS Gate-to-Source Voltage ± 8.0 V E AS Single Pulse Avalanche Energy 230 mj I AR Avalanche Current See Fig.6c, 6d, 9, 20 A E AR Repetitive Avalanche Energy mj T J, T STG Junction and Storage Temperature Range -55 to + 50 C Thermal Resistance Symbol Parameter Typ. Max. Units R θjl Junction-to-Drain Lead 20 R θja Junction-to-Ambient ƒ 50 C/W 0/04/05

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 40 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 0 mω V GS = 7.0V, I D = 4A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA g fs Forward Transconductance 40 S V DS = 0V, I D = 4A I 20 V DS = 40V, V GS = 0V DSS Drain-to-Source Leakage Current µa 250 V DS = 32V, V GS = 0V, T J = 25 C I Gate-to-Source Forward Leakage 200 V GS = 8.0V GSS na Gate-to-Source Reverse Leakage -200 V GS = -8.0V Q g Total Gate Charge I D = 4A Q gs Gate-to-Source Charge 9.0 nc V DS = 32V Q gd Gate-to-Drain ("Miller") Charge 6 V GS = 7.0V t d(on) Turn-On Delay Time 9.3 V DD = 20V t r Rise Time 5.0 I D =.0A ns t d(off) Turn-Off Delay Time 80 R G = 6.2Ω t f Fall Time 58 V GS = 7.0V C iss Input Capacitance 3520 V GS = 0V C oss Output Capacitance 660 pf V DS = 25V C rss Reverse Transfer Capacitance 76 ƒ =.0MHz Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol 2.3 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 0 (Body Diode) p-n junction diode. V SD Diode Forward Voltage.3 V T J = 25 C, I S = 2.3A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 2.3A Q rr Reverse Recovery Charge 0 70 nc di/dt = 00A/µs D S Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width 400µs; duty cycle 2%. ƒ Surface mounted on in square Cu board. Starting T J = 25 C, L = 2.3mH, R G = 25Ω, I AS = 4A. (See Figure 2). I SD 4A, di/dt 40A/µs, V DD V (BR)DSS, T J 50 C. Limited by T Jmax, see Fig.6c, 6d, 9, 20 for typical repetitive avalanche performance. 2

3 I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) VGS TOP 7.5V 7.0V 4.5V 3.0V 2.5V 2.3V 2.0V BOTTOM.8V VGS TOP 7.5V 7.0V 4.5V 3.0V 2.5V 2.3V 2.0V BOTTOM.8V 0 0.8V V 20µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 0. 20µs PULSE WIDTH Tj = 50 C V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D = 4A T 0.00 J = 50 C T J = 25 C.00 V DS = 5V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) V GS = 0V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS = 0V, f = MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd I D = 4A V DS V DS V DS = 32V = 20V = 8V Ciss Coss Crss V GS, Gate-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS (on) 00 T J = 50 C 00 00µsec 0 T J = 25 C 0 msec V GS = 0V V SD, Source-to-Drain Voltage (V) 0. Tc = 25 C Tj = 50 C Single Pulse 0msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 5 V DS R D I D, Drain Current (A) T, Case Temperature ( C C) Fig 0a. Switching Time Test Circuit V DS 90% R G V GS V GS Pulse Width µs Duty Factor 0. % D.U.T. + - V DD Fig 9. Maximum Drain Current Vs. Case Temperature 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms 00 Thermal Response (Z thja ) 0 D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thja + T A t, Rectangular Pulse Duration (sec) P DM t t 2 Fig. Typical Effective Transient Thermal Impedance, Junction-to-Ambient 5

6 V GS(th) Gate threshold Voltage (V) R DS (on), Drain-to-Source On Resistance (mω) Power (W) R DS(on), Drain-to -Source On Resistance (mω) I D = 4A V GS = 7.0V V GS, Gate -to -Source Voltage (V) I D, Drain Current (A) Fig 2. Typical On-Resistance Vs. Gate Voltage Fig 3. Typical On-Resistance Vs. Drain Current I D = 250µA T J, Temperature ( C ) Time (sec) Fig 4. Typical Threshold Voltage Vs. Fig 5. Typical Power Vs. Time Junction Temperature 6

7 E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM Starting Tj, Junction Temperature ( C) I D 6.3A A 4A 5V V DS L DRIVER R G D.U.T + I AS - V DD A 20V tp 0.0Ω Fig 6c. Unclamped Inductive Test Circuit Fig 6a. Maximum Avalanche Energy Vs. Drain Current tp V (BR)DSS I AS Fig 6d. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF D.U.T. + V - DS V GS Q GS Q GD V GS V G 3mA I G I D Current Sampling Resistors Fig 7. Gate Charge Test Circuit Charge Fig 8. Basic Gate Charge Waveform 7

8 Avalanche Current (A) E AR, Avalanche Energy (mj) 00 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses E-06.0E-05.0E-04.0E-03.0E-02.0E-0.0E+00.0E+0.0E+02.0E+03 tav (sec) Fig 9. Typical Avalanche Current Vs.Pulsewidth TOP Single Pulse BOTTOM 0% Duty Cycle I D = 4A Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN-005 at Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) Fig 20. Maximum Avalanche Energy Vs. Temperature P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av 8

9 SO-8 Package Details ' % ',0,&+(6 0, 0$; 0,//,0(7(56 0, 0$; $ $ $ ( + >@ $ E F ' ( H %$6,& %$6,& H %$6,& %$6,& + ; H. / \ ƒ ƒ ƒ ƒ H $.[ƒ & \ ;E $ >@ ;/ ;F >@ & $ % 27(6 ',0(6,2,* 72/(5$&,*3(5$60(<0 &2752//,*',0(6,20,//,0(7(5 ',0(6,26$5(6+2:,0,//,0(7(56>,&+(6@ 287/,(&2) ('(&287/,(06$$ ',0(6,2'2(627,&/8'(02/' ,26 02/' ,262772(;&(('>@ ',0(6,2'2(627,&/8'(02/' ,26 02/' ,262772(;&(('>@ ',0(6,2,67+(/(*7+2)/($')2562/'(5,*72 $68%675$7( >@ ;>@ )22735,7 ;>@ ;>@ SO-8 Part Marking (;$03/(7+,6,6$,5)026)(7,7(5$7,2$/ 5(&7,),(5 /2*2 <:: ;;;; ) '$7(&2'(<:: < /$67',*,72)7+(<($5 :: :((. /27&2'( 3$5780%(5 9

10 SO-8 Tape and Reel TERMINAL NUMBER 2.3 (.484 ).7 (.46 ) 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES:. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-48 & EIA (2.992) MAX. NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-48 & EIA (.566 ) 2.40 (.488 ) Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q0] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) TAC Fax: (30) Visit us at for sales contact information. 0/05 0

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