PFP15T140 / PFB15T140
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- Cornelia Poole
- 6 years ago
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1 FEATURES 1% EAS Test Super high density cell design Extremely Low Intrinsic Capacitances Remarkable Switching Characteristics Extended Safe Operating Area Lower R DS(ON) : 6. mω =1V 15V N-Channel MOSFET BS = 15 V R DS(on) = 6. mω I D = 14 A Gate Drain Source APPLICATION DC Motor control for E-bike & Power tools Amplifier and car booster Load Switch DC-DC converters TO Gate. Drain 3. Source D-PAK Gate. Drain 3. Source Absolute Maximum Ratings T j =5 unless otherwise specified Symbol Parameter Value Units S Drain-Source Voltage 15 V S Gate-Source Voltage ± V I D Continuous Drain Current (T C = 1 ) 1 A Continuous Drain Current (T C = 5 ) 14 A I DM Pulsed Drain Current 56 A E AS Single Pulsed Avalanche Energy 196 mj P D Maximum Power Dissipation (T C = 5 ) 3 W Maximum Power Dissipation (T C = 1 ) 16 W R θjc Thermal Resistance, Junction-to-Case.47 /W T J, T STG Operating and Storage Temperature Range -55 to +175 T L Maximum lead temperature for soldering purposes, 1/8 from case for 5 seconds 3 Package Marking and Ordering Information Marking Device Package Remark NCEP15T14 PFP15T14 TO- RoHS NCEP15T14D PFB15T14 TO-63(D-PAK) RoHS
2 Electrical Characteristics T C =5 C unless otherwise specified Symbol Parameter Test Conditions Min Typ Max Units On Characteristics (th) Gate Threshold Voltage =, I D = 5 ua V R DS(ON) Drain-Source On-Static Resistance = 1 V, I D = 7 A, T C = mω g FS Forward Transconductance = 1 V, I D = 7 A V Off Characteristics BS Drain-Source Breakdown Voltage = V, I D = 5 ua V I DSS Zero Gate Voltage Drain Current = 1 V, = V ua I GSSF I GSSR Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse = V, = V na = - V, = V na V SD Diode Forward Voltage I S = 14 A, = V V Dynamic Characteristics C iss Input Capacitance pf C oss Output Capacitance =75 V, = V, f=1. MHz pf C rss Reverse Transfer Capacitance pf Switching Characteristics t d(on) Turn-On Time ns t r Turn-On Rise Time = 75 V, I D = 7 A, ns t d(off) Turn-Off Delay Time = 1 V, R G = 4.7 Ω ns t f Turn-Off Fall Time ns Q g Total Gate Charge nc Q gs Gate-Source Charge =75 V, I D =7 A, =1V nc Q gd Gate-Drain Charge nc Notes ; 1. Repetitive Rating : Pulse width limited by maximum junction temperature. L=.5mH, =5V, R G =5Ω, Starting T J =5 3. Pulse Test : Pulse Width 3μs, Duty Cycle % 4. Essentially Independent of Operating Temperature
3 Typical Characteristics PD, Power Dissipation [W] Power Dissipation Drain Current Safe Operation Area 1 Thermal Transient Impedance Rds(on) Limit 1us 1us 1ms 1ms Theraml Response 1-1 Duty= TC=5 o C VDS, Drain-Source Voltage [V] DC Single Pulse Square Wave Pulse Duration [sec] Output Characteristics VGS=1V 7.V 6.5V 6.V 5.5V 5.V 4.5V RDS(ON), Drain-Source On-Resistance [m.ohm] Drain-Source On Resistance VGS = 1V 4.V VDS, Drain-Source Voltage [V]
4 Typical Characteristics (continued) Transfer Characteristics Normalized Threshold Voltage IDS = 5uA Gate Threshold Voltage o C 5 o C VGS, Gate-Source Voltage [V] VGS = 1V Drain-Source On Resistance 1 3 Source-Drain Diode Forward IDS = 7A Normalized On Resistance IDR, Reverse Drain Current [A] TJ=175 o C TJ=5 o C * Notes 1. VGS = V. 5us pulse test VSD, Source-Drain Voltage [V] 1 4 Capacitance Frequence=1MHz 1 VDS = 75V Gate Charge Ciss 1 IDS = 7A Capacitance [pf] Crss Coss VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Qg, Total Gate Charge [nc]
5 Characteristics Test Circuit & Waveform 1V R G R L (.5 rated ) V in 1% 9% t d(on) t r t d(off) tf t on t off Fig 14. Resistive Switching Test Circuit & Waveforms 1V nf 5KΩ 3nF Same Type as 1V Q g Q gs Q gd 3mA Charge Fig 15. Gate Charge Test Circuit & Waveform L 1 E AS = ---- L L I AS BS BS -- I D BS I AS R G I D (t) 1V (t) t p Time Fig 16. Unclamped Inductive Switching Test Circuit & Waveforms
6 Characteristics Test Circuit & Waveform (continued) + I S _ L Driver R G Same Type as dv/dt controlled by RG I S controlled by pulse period ( Driver ) D = Gate Pulse Width Gate Pulse Period 1V I FM, Body Diode Forward Current I S ( ) di/dt I RM Body Diode Reverse Current ( ) Body Diode Recovery dv/dt V f Body Diode Forward Voltage Drop Fig 17. Peak Diode Recovery dv/dt Test Circuit & Waveforms
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More informationSymbol Parameter Rating Unit Common Ratings (T C=25 C Unless Otherwise Noted) V DSS
Absolute Maximum Ratings Symbol Parameter Rating Unit Common Ratings (T C=25 C Unless Otherwise Noted) V DSS Drain-Source Voltage 3 V GSS Gate-Source Voltage ±2 T J Maximum Junction Temperature 75 C T
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TSA20N60S, TSK20N60S 600V N-Channel MOSFET Description SJ-FET is new generation of high voltage MOSFET family that is utilizing an advanced charge balance mechanism for outstanding low on-resistance and
More informationDescription TO-3PN D S. Symbol Parameter FDA18N50 Unit. Maximum Lead Temperature for Soldering Purpose, 300 C 1/8 from Case for 5 Seconds
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PD - 95514A IRFR34PbF IRFU34PbF HEXFET Power MOSFET Applications High frequency DC-DC converters Lead-Free l l V DSS R DS(on) max I D V 39mΩ 31A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses
More informationC Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Mounting Torque, 6-32 or M3 screw 1.1 (10) N m (lbf in)
Typical Applications l Industrial Motor Drive Features l Advanced Process Technology l Ultra Low On-Resistance l 175 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax
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DKG2 Aug. 2 Features Low on-state resistance Built-in gate protection diode SMD PKG Package TO252 Applications DC / DC converter Switching Internal Equivalent Circuit D(2) Key Specifications V (BR)DSS
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% EAS Guaranteed Green Device Available Super Low Gate Charge Excellent CdV/dt effect decline Advanced high cell density Trench technology Product Summary BVDSS RDSON ID 3V mω A Description TO Pin Configuration
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N-Channel Enhancement Mode Power MOSFET Description The PE6018 uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. It D can be used in a wide variety of applications.
More informationFeatures. Symbol Parameter Rating Units V DS Drain-Source Voltage 20 V V GS Gate-Source Voltage ±10 V
General Description These N-Channel enhancement mode power field effect transistors are using trench DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance,
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