SLD8N6 65S / SLU8N65 5S

Transcription

1 SLD8N65S / SLU8N65S 650V N-Channel MOSFET General Description This Power MOSFET is produced using Maple semi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switched mode power supplies, active power factor correction based on half bridge topology. Features - 7.5A, 650V, R DS(on) = 1.4Ω@ = 10 V - Low gate charge ( typical 48nC) - High ruggedness - Fast switching - 100% avalanche tested - Improved dv/dt capability LEAD FREE Pb RoHS D D D2-PAK I2-PAK G G S G D S S Absolute Maximum Ratings T C = 25 unless otherwise noted Symbol Parameter SLD8N65S SLU8N65S Units S Drain-Source Voltage 650 V I D Drain Current - Continuous (T C = 25 ) 7.5 A - Continuous (T C = 100 ) 4.6 A I DM Drain Current - Pulsed (Note 1) 21 A S Gate-Source Voltage ±30 V EAS Single Pulsed Avalanche Energy (Note 2) 128 mj I AR Avalanche Current (Note 1) 7.5 A E AR Repetitive Avalanche Energy (Note 1) 12.6 mj dv/dt Peak Diode Recovery dv/dt (Note 3) 3.3 V/ns Power Dissipation (T C = 25 ) 78 W P D - Derate above W/ T J, T STG Operating and Storage Temperature Range -55 to +150 Maximum lead temperature for soldering purposes, T L 1/8" from case for 5 seconds 300 Thermal Characteristics Symbol Parameter Max SLD8N65S SLU8N65S Units R θjc Thermal Resistance, Junction-to-Case 1.6 /W R θja Thermal Resistance, Junction-to-Ambient 62.5 /W

2 Electrical Characteristics T C = 25 unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BS Drain-Source Breakdown Voltage = 0 V, I D = 250 ua V BS Breakdown Voltage Temperature / T J Coefficient I D = 250 ua, Referenced to V/ I DSS Zero Gate Voltage Drain Current = 650 V, = 0 V ua = 520 V, T C = ua I GSSF Gate-Body Leakage Current, Forward = 30 V, = 0 V na I GSSR Gate-Body Leakage Current, Reverse = -30 V, = 0 V na On Characteristics (th) Gate Threshold Voltage =, I D = 250 ua V R DS(on) Static Drain-Source On-Resistance = 10 V, I D = 3.75A Ω g FS Forward Transconductance = 40 V, I D = 3.75 A (Note 4) S Dynamic Characteristics C iss Input Capacitance pf C oss Output Capacitance = 25 V, = 0 V, f = 1.0 MHz pf C rss Reverse Transfer Capacitance pf Switching Characteristics t d(on) Turn-On Delay Time ns t r Turn-On Rise Time = 300 V, I D =7.5 A, ns R G = 25 Ω t d(off) Turn-Off Delay Time ns (Note 4, 5) t f Turn-Off Fall Time ns Q g Total Gate Charge = 520 V, I D = 7.5 A, nc Q gs Gate-Source Charge = 10 V nc Q gd Gate-Drain Charge (Note 4, 5) nc Drain-Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain-Source Diode Forward Current A I SM Maximum Pulsed Drain-Source Diode Forward Current A V SD Drain-Source Diode Forward Voltage = 0 V, I S = 7.5A V t rr Reverse Recovery Time = 0 V, I S = 7.5 A, ns Q rr Reverse Recovery Charge di F / dt = 100 A/us (Note 4) uc Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L=1mH,I AS = 16A, = 50V, R G = 25Ω, Starting T J = 25 C 3. I SD 7.5A, di/dt 300A/us, BS, Starting T J = 25 C 4. Pulse Test : Pulse width 300us, Duty cycle 2% 5. Essentially independent of operating temperature

3 Typical Characteristics SLD8N6 65S / SLU8N65S Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature Figure 5. Capacitance Characteristics Figure 6. On-Resistance Variation vs Temperature

4 Typical Characteristics (Continued) SLD8N6 65S / SLU8N65S Figure 7. Breakdown Voltage Variation vs Temperature

5 12V 3mA Current Regulator 200nF 50KΩ VGS Gate Charge Test Circuit & Waveform 300nF Same Type as R 1 R 2 Q gs Q g Q gd Current Sampling (I G ) Resistor Current Sampling (I D ) Resistor Charge Resistive Switching Test Circuit & Waveforms R L V in V out ( 0.5 rated ) V out 90% R G V in 10% t d(on) t r t d(off) tf t on t off Unclamped Inductive Switching Test Circuit & Waveforms L L 1 E AS = ---- L L I 2 AS 2 BS BS -- Vary t p to obtain required peak I D I D BS I AS R G C I D (t) (t) t p t p Time

6 Peak Diode Recovery dv/dt Test Circuit & Waveforms + I S Driver -- L R G Same Type as dv/dt controlled by by 밨RG G IISD S controlled by by Duty pulse Factor period밆? ( Driver ) D = Gate Pulse Width Gate Pulse Period I FM, Body Diode Forward Current I S S ( ) di/dt I RM Body Diode Reverse Current ( ) Body Diode Recovery dv/dt V f Body Diode Forward Voltage Drop