PKP3105. P-Ch 30V Fast Switching MOSFETs
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1 Super Low Gate Charge % EAS Guaranteed Green Device Available Excellent CdV/dt effect decline Advanced high cell density Trench technology Product Summary BVDSS RDSON ID -3V mω -6A Description TO22 Pin Configuration The is the high cell density trenched P-ch MOSFETs, which provide excellent RDSON and gate charge for most of the synchronous buck converter applications. The meet the RoHS and Green Product requirement, % EAS guaranteed with full function reliability approved. Absolute Maximum Ratings Symbol Parameter Rating Units VDS Drain-Source Voltage -3 V VGS Gate-Source Voltage ±2 V ID@TC=25 Continuous Drain Current, -V -6 A ID@TC= Continuous Drain Current, -V -38 A ID@TA=25 Continuous Drain Current, -V - A ID@TA=7 Continuous Drain Current, -V -8 A IDM Pulsed Drain Current 2-5 A EAS Single Pulse Avalanche Energy 3 25 mj IAS Avalanche Current -5 A PD@TC=25 Total Power Dissipation 7 W TSTG Storage Temperature Range -55 to 5 TJ Operating Junction Temperature Range -55 to 5 Thermal Data Symbol Parameter Typ. Max. Unit RθJA Thermal Resistance Junction-Ambient /W RθJC Thermal Resistance Junction-Case /W
2 Electrical Characteristics (T J=25, unless otherwise noted) Symbol Parameter Conditions Min. Typ. Max. Unit BVDSS Drain-Source Breakdown Voltage VGS=V, ID=-25uA V BVDSS/ TJ BVDSS Temperature Coefficient Reference to 25, ID=-mA V/ RDS(ON) Static Drain-Source On-Resistance 2 VGS=-V, ID=-3A VGS=-.5V, ID=-5A m VGS(th) Gate Threshold Voltage V VGS=VDS, ID =-25uA VGS(th) VGS(th) Temperature Coefficient mv/ IDSS VDS=-2V, VGS=V, TJ= Drain-Source Leakage Current ua VDS=-2V, VGS=V, TJ= IGSS Gate-Source Leakage Current VGS=±2V, VDS=V ± na gfs Forward Transconductance VDS=-5V, ID=-3A S Rg Gate Resistance VDS=V, VGS=V, f=mhz Qg Total Gate Charge (-.5V) Qgs Gate-Source Charge VDS=-5V, VGS=-.5V, ID=-5A nc Qgd Gate-Drain Charge Td(on) Turn-On Delay Time Tr Rise Time VDD=-5V, VGS=-V, RG= ns Td(off) Turn-Off Delay Time ID=-5A Tf Fall Time Ciss Input Capacitance Coss Output Capacitance VDS=-5V, VGS=V, f=mhz pf Crss Reverse Transfer Capacitance Diode Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit IS Continuous Source Current, A VG=VD=V, Force Current ISM Pulsed Source Current 2, A VSD Diode Forward Voltage 2 VGS=V, IS=-A, TJ= V trr Reverse Recovery Time IF=-5A, di/dt=a/µs, ns Qrr Reverse Recovery Charge TJ= nc Note :.The data tested by surface mounted on a inch 2 FR- board with 2OZ copper. 2.The data tested by pulsed, pulse width 3us, duty cycle 2% 3.The EAS data shows Max. rating. The test condition is V DD=-25V,V GS=-V,L=.mH,I AS=-5A.The power dissipation is limited by 5 junction temperature 5.The data is theoretically the same as I D and I DM, in real applications, should be limited by total power dissipation. 2
3 Typical Characteristics 5 -ID Drain Current (A) V GS =-V V GS =-7V V GS =-5V V GS =-.5V V GS =-3V V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig.2 On-Resistance vs. G-S Voltage -IS Source Current(A) T J =5 T J = V SD, Source-to-Drain Voltage (V) Fig.3 Forward Characteristics of Reverse -VGS Gate to Source Voltage (V) V DS =-5V I D =-5A Q G, Total Gate Charge (nc) Fig. Gate-charge Characteristics Normalized VGS(th).5 Normalized On Resistance T J,Junction Temperature ( ) T J, Junction Temperature ( ) Fig.5 Normalized V GS(th) vs. T J Fig.6 Normalized R DSON vs. T J 3
4 F=.MHz Capacitance (pf) Ciss Coss Crss V DS, Drain to Source Voltage (V) Fig.7 Capacitance Fig.8 Safe Operating Area Normalized Thermal Response (RθJC). DUTY= SINGLE PULSE T J peak = T C + P DM x R θjc t, Pulse Width (s) P DM T ON D = T ON /T Fig.9 Normalized Maximum Transient Thermal Impedance T Fig. Switching Time Waveform Fig. Unclamped Inductive Switching Waveform
5 Package Information ( TO-22-3L ) 5
Symbol Parameter Rating Units VDS Drain-Source Voltage 30 V VGS Gate-Source Voltage ±20 V
% EAS Guaranteed Green Device Available Super Low Gate Charge Excellent CdV/dt effect decline Advanced high cell density Trench technology Product Summary BVDSS RDSON ID 3V mω A Description TO Pin Configuration
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P-channel 20 V, 0.087 Ω typ., 1.4 A STripFET H7 Power MOSFET in a SOT-23 package Datasheet - production data Features Order code VDS RDS(on) max ID STR1P2UH7 20 V 0.1 Ω @ 4.5 1.4 A Very low on-resistance
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1 3 FEATURES RDS(ON) 110mΩ@VGS=-4.5V RDS(ON) 150mΩ@VGS=-2.5V Super high density cell design for extremely low RDS(ON) APPLICATIONS Power Management in Note book Portable Equipment Battery Powered System
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2N7632UC IRHLUC767Z4 RADIATION HARDENED 6V, Combination N-P-CHANNEL LOGIC LEVEL POWER MOSFET TECHNOLOGY SURFACE MOUNT (LCC-6) Product Summary Part Number Radiation Level R DS(on) I D CHANNEL IRHLUC767Z4
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DESCRIPTION The is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to
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PD-91551D POWER MOSFET SURFACE MOUNT(SMD-1) Product Summary Part Number RDS(on) ID IRFN350 0.315 Ω 14A IRFN350 JANTX2N7227U JANTXV2N7227U REF:MIL-PRF-19500/592 400V, N-CHANNEL HEXFET MOSFET TECHNOLOGY
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General Description These N-Channel enhancement mode power field effect transistors are using trench DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance,
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N-channel 30 V, 2.15 mω typ., 120 A Power MOSFET in a TO-220 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STP200N3LL 30 V 2.4 mω 120 A 176.5 W Very low on-resistance
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