Bias Stress Testing of SiC MOSFETs
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1 Bias Stress Testing of SiC MOSFETs Robert Shaw Manager, Test and Qualification August 15 th, 2014 Special thanks to the U.S. Department of Energy for funding this under SBIR DE-SC
2 Outline Objectives Test Plans High Temperature Gate Bias (HTGB) Gate Switching Bias DC Body Diode Bias Pulsed Body Diode Bias Initial Characterization (t0) Results HTGB Results (1000 hours) Pulsed Body Diode Results (1000 hours) 2
3 Objectives
4 Objectives An assessment of gate oxide stability in commercially available SiC MOSFETs Prototype/engineering sample SiC MOSETs included as available Supplemental assessment of body diode/channel degradation Study the effects of biasing at 150 C junction temperature Bias devices for a minimum of 1000 hours, with characterization at specified intervals 4
5 Test Plan 5
6 Test Plan Three vendors included in testing Target device is 1200 V, ~20 A SiC MOSFET Devices biased at a junction temperature of 150 C Four different electrical biases: High Temperature Gate Bias (HTGB) Gate Switching Bias DC Body Diode Bias Pulsed Body Diode Bias
7 HTGB Goal is to determine effect of constant gate voltage bias on oxide stability Gate to source voltage applied while tying drain and source to common potential (ground) Bias test modeled after JESD-22 A108C Four different bias voltages +20, +15, -10, and -15 volts Twenty devices at each voltage for each vendor Total of 240 devices Characterization performed at 0, 300, 600, and 1000 hours
8 Gate Switching Bias Goal is to compare alternating gate bias voltage to constant gate bias This test aims to simulate gate bias similar to that of a device in a switching application Gate bias: 100 khz frequency +20 to -5 V 50% duty cycle Drain and source tied to common potential (ground) 5 devices from each vendor Characterization performed at 0, 300, 600, and 1000 hours 8
9 DC Body Diode Bias Goal is to determine channel and/or body diode degradation as a result of body diode conduction Gate to source voltage held constant at -5 V to ensure no channel conduction Constant body diode bias of 18 A Thermal management system designed to maintain junction temperature of 150 C 5 devices from each vendor Characterization performed at 0, 1, 10, and 100 minutes. Previous tests have shown performance shifts in as little as 1 minute 9
10 Pulsed Body Diode Test Goal is to compare DC body diode bias to pulsed body diode bias This test aims to simulate free wheeling body diode conduction found in switching applications Gate to source voltage held constant at -5 V to ensure no channel conduction Pulse characteristics 18 A amplitude 450 ns pulse width 50 khz frequency 5 devices from each vendor Characterization performed at 0, 300, 600, and 1000 hours 10
11 Initial Characterization 11
12 Reverse Drain Current (V DS = 1200 V) V GS = 0 V Reverse Drain Current (na) Vendor A Vendor B Vendor C Average Minimum Maximum V GS = -4 V Reverse Drain Current (na) Vendor A Vendor B Vendor C Average Minimum Maximum
13 Threshold Voltage Threshold Voltage (V) Vendor A Vendor B Vendor C Average Minimum Maximum Threshold voltage was measured at I DS = 10 ma, with V DS = 10 V. 13
14 Sub-threshold 14
15 On-resistance On-resistance (mω) Vendor A Vendor B Vendor C Average Minimum Maximum On-resistance was measured at I DS = 20 A, V GS = 20 V 15
16 Body Diode 16
17 3 rd Quadrant Operation 17
18 HTGB Results Threshold voltage plotted 20 samples per vendor at each gate voltage Vds = 10 V, Vth measured at Ids = 10 ma Characterized at 0, 300, 600, and 1000 hours 18
19 Vendor A 19
20 Vendor B 20
21 Vendor C 21
22 Vendor C Vendor B Vendor A Threshold Shift Averages V GS 0 hr 300 hr 600 hr 1000 hr
23 Pulsed Body Diode Bias Results 5 samples per vendor 18 A pulse amplitude 450 ns pulse width 50 khz frequency 23
24 Pulsed Body Diode Results 24
25 Gate Switching Bias Results 5 samples per vendor 100 khz frequency V GS = +20 to -5 V 50% duty cycle 25
26 Gate Switching Bias Results Due to a test bed failure during testing, no results are available for Vendor B, and the sample size for Vendor C was limited to 3.
27 Questions?
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Applications Dual SO-8 MOSFET for POL converters in desktop, servers, graphics cards, game consoles and set-top box PD - 95858A IRF895 HEXFET Power MOSFET V DSS R DS(on) max I D 20V 8.3m:@V GS = V 8.9A
More informationPackage Code. Date Code YYXXX WW
N-Channel Enhancement Mode MOSFET Features Pin Description 8V/ 2A R DS(ON) = 2.9 mω (typ.) @ V GS =1V 1% avalanche tested Reliable and Rugged Lead Free and Green DevicesAvailable (RoHS Compliant) G D S
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These miniature surface mount MOSFETs utilize a high cell density trench process to provide low r DS(on) and to ensure minimal power loss and heat dissipation. Typical applications are DC-DC converters
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Main Product Characteristics V DSS R DS(on) I D 650V 0.32Ω (typ.) 11A TO-220F Marking and Pin S c h e m a ti c Dia g r a m Assignment Features and Benefits High dv/dt and avalanche capabilities 100% avalanche
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PD-9464D IRHNA59764 RADIATION HARDENED POWER MOSFET SURFACE MOUNT (SMD-2) 6V, P-CHANNEL REF: MIL-PRF-195/733 R 5 TECHNOLOGY Product Summary Part Number Radiation Level RDS(on) I D QPL Part Number IRHNA59764
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UNISONIC TECHNOLOGIES CO., LTD DUAL ENHANCEMENT MODE (N-CHANNEL/P-CHANNEL) DESCRIPTION The UTC UD466 provides excellent R DS(ON) and low gate charge by using advanced trench technology MOSFETs. The complementary
More informationP HY4004. B HY4004 ÿ YYXXXJWW G HY4004P/B. Features. N-Channel Enhancement Mode MOSFET. 100% avalanche tested. Switching application
N-Channel Enhancement Mode MOSFET Features Pin Description 40V/ 208A R DS(ON) = 2.5 mω (typ.) @ V GS =0V 00% avalanche tested Reliable and Rugged Lead Free and Green DevicesAvailable (RoHS Compliant) G
More informationDevice Marking Device Device Package Reel Size Tape width Quantity NCE82H110D NCE82H110D TO-263-2L - - -
http://www.ncepower.com NCE N-Channel Enhancement Mode Power MOSFET Description The uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. It can be used in a wide
More informationDevice Marking Device Device Package Reel Size Tape width Quantity HM5P55R HM5P55R SOT-223 Ø330mm 12mm 2500 units. Parameter Symbol Limit Unit
P-Channel Enhancement Mode Power MOSFET Description The HM5P55R uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. It can be used in a wide variety of applications.
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PD-9440B RAD-HARD SYNCHRONOUS RECTIFIER SURFACE MOUNT (SMD-2) 60V, N-CHANNEL Product Summary Part Number Radiation Level RDS(on) QG 00K Rads (Si) 6.mΩ 60nC IRHSLNA53064 300K Rads (Si) 6.mΩ 60nC IRHSLNA54064
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Robustness Study of SiC MOSFET Under Harsh Electrical and Thermal Constraints To an in-depth physical failure analysis Safa Mbarek, Pascal Dherbécourt, Olivier Latry, François Fouquet* University of Rouen,
More informationSymbol Parameter Typical
PRODUCT SUMMARY (TYPICAL) V DS (V) 600 R DS(on) ( ) 0.29 Q rr (nc) 29 Features Low Q rr Free-wheeling diode not required Low-side Quiet Tab for reduced EMI RoHS compliant High frequency operation Applications
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Approved (Not Released) PD - TBD Applications l Optimized for UPS/Inverter Applications l Low Voltage Power Tools Benefits l Best in Class Performance for UPS/Inverter Applications l Very Low RDS(on) at
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UNISONIC TECHNOLOGIES CO., LTD UTT150N03 Preliminary Power MOSFET N-CHANNEL ENHANCEMENT MODE POWER MOSFET DESCRIPTION The UTC UTT150N03 is a N-channel power MOSFET, using UTC s advanced trench technology
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DESCRIPTIONS The uses advanced trench technology to provide excellent R DS(ON), low gate charge and operation with gate voltages as low as 2.5V. This device is suitable for use as a Battery protection
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