UF3C120080K4S. 1200V-80mW SiC Cascode DATASHEET. Description. Features. Typical applications CASE D (1) CASE G (4) KS (3) S (2) Rev.

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1 1V-8mW SiC Cascode Rev. A, January 19 DATASHEET UF3C18K4S CASE CASE D (1) Description United Silicon Carbide's cascode products co-package its highperformance F3 SiC fast JFETs with a cascode optimized MOSFET to produce the only standard gate drive SiC device in the market today. This series exhibits very fast switching using a 4-terminal TO-247- package and the best reverse recovery characteristics of any device of similar ratings. These devices are excellent for switching inductive loads, and any application requiring standard gate drive. Features Typical on-resistance R DS(on),typ of 8mW Maximum operating temperature of 175 C G (4) KS (3) S (2) Excellent reverse recovery Low gate charge Low intrinsic capacitance ESD protected, HBM class 2 TO-247-4L package for faster switching, clean gate waveforms Typical applications EV charging Part Number UF3C18K4S Package TO-247-4L Marking UF3C18K4S PV inverters Switch mode power supplies Power factor correction modules Motor drives Induction heating Datasheet: UF3C18K4S Rev. A, January 19 1

2 Maximum Ratings Parameter Symbol Test Conditions Value Units Drain-source voltage V DS 1 V Gate-source voltage V GS DC -25 to +25 V Continuous drain current 1 I D T C = 25 C 33 A T C = C 24 A Pulsed drain current 2 I DM T C = 25 C 77 A Single pulsed avalanche energy 3 E AS L=15mH, I AS =2.8A 58.5 mj Power dissipation P tot T C = 25 C W Maximum junction temperature T J,max 175 C Operating and storage temperature T J, T STG -55 to 175 C Max. lead temperature for soldering, 1/8 from case for 5 seconds T L 2 C 1. Limited by T J,max 2. Pulse width t p limited by T J,max 3. Starting T J = 25 C Thermal Characteristics Value Parameter Symbol Test Conditions Units Min Typ Max Thermal resistance, junction-to-case R qjc C/W Datasheet: UF3C18K4S Rev. A, January 19 2

3 Electrical Characteristics (T J = +25 C unless otherwise specified) Typical Performance - Static Parameter Symbol Test Conditions Value Min Typ Max Units Drain-source breakdown voltage BV DS V GS =V, I D =1mA 1 V Total drain leakage current Total gate leakage current I DSS V DS =1V, V GS =V, T J =25 C V DS =1V, V GS =V, T J =175 C 75 V DS =V, T J =25 C, I GSS 6 ma V GS =-V / +V Drain-source on-resistance R DS(on) V GS =12V, I D =A, T J =25 C 8 V GS =12V, I D =A, T J =175 C 172 mw Gate threshold voltage V G(th) V DS =5V, I D =ma V Gate resistance R G f=1mhz, open drain 4.5 W ma Typical Performance - Reverse Diode Value Parameter Symbol Test Conditions Units Min Typ Max Diode continuous forward current 1 I S T C =25 C 33 A Diode pulse current 2 Forward voltage Reverse recovery charge Reverse recovery time I S,pulse T C =25 C 77 A V FSD V GS =V, I F =A, T J =25 C V GS =V, I F =A, T J =175 C Q rr V R =8V, I F =A, V GS =-5V, R G_EXT =W 212 nc di/dt=a/ms, t rr T J =25 C 23 ns 2 V Reverse recovery charge Reverse recovery time Q rr V R =8V, I F =A, V GS =-5V, R G_EXT =W 124 nc di/dt=a/ms, t rr T J =1 C 13 ns Datasheet: UF3C18K4S Rev. A, January 19 3

4 Typical Performance - Dynamic Input capacitance Output capacitance Parameter Symbol Test Conditions Reverse transfer capacitance Effective output capacitance, energy related Effective output capacitance, time related Min Typ Max C iss V DS =V, V GS =V C oss f=khz C rss 2.1 V DS =V to 8V, C oss(er) 59 pf V GS =V V DS =V to 8V, C oss(tr) 136 pf V GS =V C OSS stored energy E oss V DS =8V, V GS =V 19 mj Total gate charge Gate-drain charge Gate-source charge Turn-on delay time Rise time Turn-off delay time Fall time Turn-on energy Turn-off energy Total switching energy Turn-on delay time Rise time Turn-off delay time Fall time Turn-on energy Turn-off energy Total switching energy Value Q G 43 V DS =8V, I D =A, Q GD 11 V GS = -5V to 12V Q GS 19 t d(on) V DS =8V, I D =A, 33 t Gate Driver =-5V to r V, t d(off) Turn-on R 43 G,EXT =8.5W, t f Turn-off R G,EXT =W E ON Inductive Load, 355 E OFF FWD: same device with V GS = -5V, R G = W, 88 E TOTAL T J =25 C 443 t d(on) V DS =8V, I D =A, 29 Gate Driver =-5V to t r V, t d(off) Turn-on R G,EXT =8.5W, 45 t f Turn-off R G,EXT =W E ON Inductive Load, 6 FWD: same device with E OFF 82 V GS = -5V, R G = W, E TOTAL T J =1 C 388 Units pf nc ns mj ns mj Datasheet: UF3C18K4S Rev. A, January 19 4

5 On Resistance, R DS_ON (P.U.) Typical Performance Diagrams Vgs = 15V Vgs = 7.5V Vgs = 7V Vgs = 6.5V 4 Vgs = 15V Vgs = 7V Vgs = 6.5V Vgs = 6V Figure 1. Typical output characteristics at T J = - 55 C, tp < 2ms Figure 2. Typical output characteristics at T J = 25 C, tp < 2ms 6 4 Vgs = 15V Vgs = 7V Vgs = 6V Vgs = 5.5V Vgs = 5V Junction Temperature, T J ( C) Figure 3. Typical output characteristics at T J = 175 C, tp < 2ms Figure 4. Normalized on-resistance vs. temperature at V GS = 12V and I D = A Datasheet: UF3C18K4S Rev. A, January 19 5

6 Threshold Voltage, V th (V) Gate-Source Voltage, V GS (V) On-Resistance, R DS(on) (mw) 6 2 Tj = 175 C Tj = 25 C Tj = - 55 C 4 Tj = -55 C Tj = 25 C Tj = 175 C Gate-Source Voltage, V GS (V) Figure 5. Typical drain-source on-resistances at V GS = 12V Figure 6. Typical transfer characteristics at V DS = 5V Junction Temperature, T J ( C) Gate Charge, Q G (nc) Figure 7. Threshold voltage vs. junction temperature at V DS = 5V and I D = ma Figure 8. Typical gate charge at V DS = 8V and I D = A Datasheet: UF3C18K4S Rev. A, January 19 6

7 E OSS (mj) -5 - Vgs = -5V Vgs = V Vgs = 5V -5 - Vgs = - 5V Vgs = V Vgs = 5V Figure 9. 3rd quadrant characteristics at T J = -55 C Figure. 3rd quadrant characteristics at T J = 25 C Vgs = - 5V Vgs = V Vgs = 5V Figure 11. 3rd quadrant characteristics at T J = 175 C Figure 12. Typical stored energy in C OSS at V GS = V Datasheet: UF3C18K4S Rev. A, January 19 7

8 Power Dissipation, P tot (W) Thermal Impedance, Z qjc ( C/W) Capacitance, C (pf) DC, 35 1, 1 C iss C oss C rss Case Temperature, T C ( C) Figure 13. Typical capacitances at f = khz and V GS = V Figure 14. DC drain current derating Case Temperature, T C ( C).1.1 D =.5 D =.3 D =.1 D =.5 D =.2 D =.1 Single Pulse.1 1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 Pulse Time, t p (s) Figure 15. Total power dissipation Figure 16. Maximum transient thermal impedance Datasheet: UF3C18K4S Rev. A, January 19 8

9 Turn-on Energy, E ON (mj) Turn-Off Energy, E OFF (mj) Switching Energy (mj) 1ms ms V DD = 8V, V GS = -5V/12V R G_ON = 8.5W, R G_OFF = W FWD: same device with V GS = -5V, R G = W 1 DC ms 1ms ms 4 Etot Eon Eoff Figure 17. Safe operation area at T C = 25 C, D =, Parameter t p Figure 18. Clamped inductive switching energy vs. drain current at T J = 25 C V DD = 8V, V GS = -5V/12V I D = A, T J = 25 C FWD: same device with V GS - 5V, R G = W 5 15 Total External R G, RG,EXT_ON (W) V DD = 8V, V GS = -5V/12V I D = A, T J =25 C FWD: same device with V GS = -5V, R G = W Total External R G, RG,EXT_OFF (W) Figure 19. Clamped inductive switching turn-on energy vs. R G,EXT_ON Figure. Clamped inductive switching turn-off energy vs. R G,EXT_OFF Datasheet: UF3C18K4S Rev. A, January 19 9

10 Switching Energy (mj) Qrr (nc) 4 Etot Eon Eoff 2 V DD = 8V, I S = A, di/dt = A/ms, V GS = -5V, R G =W 1 V GS = -5V/12V, R G_ON = 8.5W, R G_OFF = W, FWD: same device with V GS = -5V, R G = W Junction Temperature, T J ( C) Junction Temperature, T J ( C) Figure 21. Clamped inductive switching energy vs. junction temperature at V DS = 8V and I D = A Figure 22. Reverse recovery charge Qrr vs. junction temperature Applications Information SiC cascodes are enhancement-mode power switches formed by a high-voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (R DS(on) ), output capacitance (C oss ), gate charge (Q G ), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC cascodes also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Information on all products and contained herein is intended for description only. No license, express or implied, to any intellectual property rights is granted within this document. United Silicon Carbide, Inc. assumes no liability whatsoever relating to the choice, selection or use of the United Silicon Carbide, Inc. products and services described herein. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the cascode is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on cascode operation, see Disclaimer United Silicon Carbide, Inc. reserves the right to change or modify any of the products and their inherent physical and technical specifications without prior notice. United Silicon Carbide, Inc. assumes no responsibility or liability for any errors or inaccuracies within. Datasheet: UF3C18K4S Rev. A, January 19