Integration of III-V heterostructure tunnel FETs on Si using Template Assisted Selective Epitaxy (TASE)
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1 Integration of III-V heterostructure tunnel FETs on Si using Template Assisted Selective Epitaxy (TASE) K. Moselund 1, D. Cutaia 1. M. Borg 1, H. Schmid 1, S. Sant 2, A. Schenk 2 and H. Riel 1 1 IBM Research Zurich, Switzerland 2 ETH Zurich, Integrated Systems Laboratory IBM Corporation
2 Outline Motivation & background Low power electronics Tunnel FET functionality & SOA Template Assisted Selective Epitaxy Vertical & Lateral approach Experimental P & N-TFET fabrication Electrical characterization Limitations of InAs/Si P-TFETs Analysis of trap contributions Outlook & Summary InAs D it Si CB VB 1
3 Low power electronics InAs Si P tot V 2 C Vdd f active I Leak Vdd leakage Reduce I Leak, Reduce V dd I D (log) V th = I off Slope = 60mV/dec. DV dd MOSFET Steep Slope Device Phase transition Ferro-FET NEMS Tunnel FET 10 µm Out GND In VDD 2 V th V th V dd V dd V GS Steep subthreshold slope can decrease V th to reduce V dd 100 nm W BCB Spin Torque Switch Domain wall switching
4 Tunnel FET functionality Steep slope V dd scaling and low I off Potential to achieve ultra-low power operation source channel Band-to-band-tunneling (BTBT) acts as bandpass filter cutting off the tails of the Fermi distribution SS < 60 mv/dec possible E C filtering of the Fermi function 3
5 How to make a good tunnel switch Increasing Ion l: Electrostatics GAA, EOT scaling, thin body, doping profiles E g, m*: materials based Ge/InAs source on Si, III-V heterostructures GAA Abrupt doping High-k III-V heterostructures Low thermal budget InAs InAs Si GaSb 4 5
6 State of The Art Tunnel FETs Many different implementations (geometry, materials etc.) reported so far Varying potential for: High I on, low SS, integration potential, scalability. InGaAs Air Bridge, Intel (IEDM 2011) s-sinw on SOI (inverters), FZ Julich (IEDM 2013) InGaAs mesa, Penn state (DRC2011) InAs/GaSb mesa, Notre Dame(IEDM 2012) Planar Zn-diffused InGaAs, Tokyo University(IEDM 2013) GaSb/InAs vertical NW Lund (EDL 2016) Vertical Si-Ge NW, IMEC (IEDM 2013) 3D-2D TFET: MoS 2 & Ge, UCSB (Nature 2015)
7 Complementary TFET technologies Challenging for heterojunction TFETs, due to the need for different material combinations for n- and p-channel devices VLSI 2015: Demonstrated p- and n-type InGaAs/GaAsSb TFETs on the same InP substrate use of metamorphic buffer Using TASE we are able to selective grow InAs and GaSb NWs co-planar to each other VLSI 2016: InAs/Si p-tfets and InAs/GaSb n-tfets are implemented on different wafers, using compatible process flows R. Pandey et al., VLSI Symp. (2015) D. Cutaia et al., VLSI Symp. (2016) TASE technology for heterojunction TFETs Development of heterojunction TFET technology: vertical planar Performance and limitations of fabricated TFETs 5
8 Outline Motivation & background Low power electronics Tunnel FET functionality & SOA Template Assisted Selective Epitaxy Vertical & Lateral approach Experimental P & N-TFET fabrication Electrical characterization Limitations of InAs/Si P-TFETs Analysis of trap contributions Outlook & Summary InAs D it Si CB VB
9 Vertical Implementation of TASE α-si SiO 2 Si/α-Si stack Si substrate Etch sacrificial NW MOVPE growth Deposit SiO 2 Open template α-si selective wet etch Large arrays possible dense integration. III-V GaAs as-grown Template stripped 2 um Less flexibility in parameters, L & L i determined by stack. Applications: TFETs, dense integration, photovoltaics 6
10 Horizontal Implementation of TASE Good control over junction placement. Device parameters (L, L i, W, etc.) easily defined by design. Easier fabrication Applications: MOSFETs, TFETs, arbitrary geometry devices, optoelectronics 7
11 Template Assisted Selective Epitaxy (TASE) Growth on any crystalline orientation Stacked nanowires Enables VLSI integration Abrupt junctions Chemical Analysis: EELS, EDX Scalable Technology Arbitrary geometries InSb InAs Courtesy of L. Gignac, IBM Yorktown. Requirement for Steep slope P. D. Kanungo et al. Nanotechnology, 2013, M. Borg et al. Nanoletters, H. Schmid et al. APL 2015, 8
12 Classical devices fabricated using TASE InAs MOSFETs Device: 10 parallel NWs, L G ~ 150 nm, Results: I on = 480 μa/μm (V DS =0.5V) g m = 0.9 ms/μm (V DS =0.5V) Field-effect mobility ~ 500 cm 2 /Vs SS = 250 mv/dec 23x25 nm TASE grown Hall-bar structures Hall measurements (0.1T, RT) n s = IB/qV H = 3.9x10 17 cm 3 electron mobility = 5400 cm 2 /Vs Material allows good device performance 9 H. Schmid et al. APL 2015,
13 Outline Motivation & background Low power electronics Tunnel FET functionality & SOA Template Assisted Selective Epitaxy Vertical & Lateral approach Experimental P & N-TFET fabrication Electrical characterization Limitations of InAs/Si P-TFETs Analysis of trap contributions Outlook & Summary InAs D it Si CB VB
14 Developing our vertical InAs/Si TFET process TEM: L. Gignac, J. Bruley, C. Breslin TASE Scaled diameter Metal ALD Scaled EOT TEOS K. Moselund, EDL H. Riel IEDM D. Cutaia, et al. J-EDS 2015, D. Cutaia, et al. ULIS Transfer to lateral technology flexibility in device processing & complementary TFETs
15 Horizontal TFET fabrication 11
16 Horizontal TFET fabrication 11
17 Horizontal TFET fabrication 11
18 Horizontal TFET fabrication 11
19 Horizontal InAs/Si p-tfets D. Cutaia et al., VLSI Symp
20 Horizontal InAs/gaSb n-tfets 13 D. Cutaia et al., VLSI Symp 2016
21 InAs/Si p-tfet: comparison vertical vs. planar Observations: Ion boosted x50 by EOT scaling (vertical TFETs) Size: 100 nm cross-section 30nm. Horizontal: SS ave much improved 150 mv/dec ~70mV/dec 14
22 Transfer Characteristics 300K P-TFET: I ON =4μA/μm at V GS =V DS =-0.5V, SS~70-80mV/dec., I ON /I OFF ~10 6 N-TFET: I ON =40μA/μm at V GS,ov =3V, V DS =0.5V, SS~1V/dec., I ON /I OFF ~ D. Cutaia et al., VLSI Symp 2016
23 Transfer Characteristics T-sweep Small T-dependence for I D in the ON state Strong SS T dependence P-TFET: SS ave reduced to 55mV/dec. at 150K N-TFET: SS ave reduced to 400mV/dec. at 150K 16 Slide 23
24 SS and g m /I D p-tfet Subthreshold Slope vs. I D : Traps at InAs/Si heterojunction and InAs/High-k interface Switching region limited by TAT g m /I D vs. V GS : Transconductance efficiency peak at 300K 34V -1 Peak shifts to higher I D when reducing T SS improvement 17
25 Diode/Output characteristics P-TFET: No NDR expected for V GS levels used in measurements (-0.5V) due to gate overlap of source. S. Sant, submitted TED 2016 N-TFET: NDR observed on pn and pin diodes with gate metal removed, but not on TFETs 18 D. Cutaia et al., VLSI Symp 2016
26 Outline Motivation & background Low power electronics Tunnel FET functionality & SOA Template Assisted Selective Epitaxy Vertical & Lateral approach Experimental P & N-TFET fabrication Electrical characterization Limitations of InAs/Si P-TFETs Analysis of trap contributions Outlook & Summary InAs D it Si CB VB
27 Effect of generation centers ( traps ) gate oxide Trap-assisted tunneling (TAT) can be seen as multi-phonon-assisted trap-band tunneling or as field-enhanced multi-phonon generation. Contribution from 3 kinds of traps: bulk, hetero interface, gate oxide interface bulk traps traps at hetero interface n-inas Silicon CB oxide interface traps CB intr. VB A. Palma et al., PRB 56, 9565 (1997) n-inas F. Jiménez-Molinos et al., JAP, 91 (8), 5116 (2002) VB 19 A. Schenk et al. ULIS 2015, S. Sant et al., DRC 2016
28 Individual contributions of TAT mechanisms * BTBT T = 300K InAs/ oxide traps InAs/Si traps Only traps at InAs/Si hetero interface can give desired match with the experimental data S. Sant el. al. submitted to IEEE TED 20
29 Dominant mechanism- thermionic emission InAs V GS =0.3V Silicon TAT Therm. emission 300K BTBT TAT bottleneck Therm. emission bottleneck 125K * Low gate bias: thermionic emission is the bottleneck => SS close to thermionic SS. Medium gate bias: thermionic barrier is lowered => TAT becomes bottleneck. High gate bias: BTBT is dominating mechanism 21
30 Traps in InAs/Si TFETs One active trap level per dislocation D it = 1.5x10 13 cm -2 *TEM image - Tomioka et. al. Nano Lett Large lattice mismatch > 11% between Si and InAs. Predictive simulations show highest tolerable dit level ~ 5x10 11 cm -2. Extreme scaling required, or.. Use of lattice-matched material system InGaAs/GaAsSb. Similar requirements on oxide D it levels. 22
31 State-of-the-art TFETs Different designs different merits SS ave scaling below 60 mv/dec in significant I on range still missing 23
32 Summary Introduced tunnel FETs and low-power electronics Demonstrated TASE growth for TFETs and device fabrication. Demonstrated scaled complementary TFETs InAs/Si P-TFET & InAS/GaSb N-TFET Traps at the oxide and hetero interface are currently limiting perfromance. Outlook Optimization of N-TFET (GaSb doping, gate stack) Reduction of defects essential for all TFETs Applications of TASE to new fields: photonics, sensors, 24
33 Thank you for your attention Acknowledgement: MIND group at IBM Research Zurich TEM images: L. Gignac, J. Bruley, C. Breslin, SIMS: Marinus Hopstaken IBM Research Yorktown Support from colleagues and staff at Binnig- Rohrer Nanotechnol. Center Funding: European FP7 Projects 25
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