III-V Channel Transistors

Transcription

1 III-V Channel Transistors Jesús A. del Alamo Professor Microsystems Technology Laboratories MIT Acknowledgements: Students and collaborators: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung Labs at MIT: MTL, EBL 24 April 2017

2 Moore s Law at 50: the end in sight? 2

3 Moore s Law Moore s Law = exponential increase in transistor density Intel microprocessors 2016: Intel 22-core Xeon Broadwell-E5 7.2B transistors 3

4 Moore s Law How far can Si support Moore s Law?? 4

5 Transistor scaling Voltage scaling Performance suffers Supply voltage: Transistor current density: Intel microprocessors Intel microprocessors Goals: Reduced footprint with moderate short-channel effects High performance at low voltage 5

6 Moore s Law: it s all about MOSFET scaling 1. New device structures with improved scalability: 2. New materials with improved transport characteristics: n-channel: Si Strained Si SiGe InGaAs p-channel: Si Strained Si SiGe Ge InGaSb 6

7 III-V electronics in your pocket! 7

8 Contents 8

9 1. Self-aligned Planar InGaAs MOSFETs dry-etched recess selective MOCVD W Mo Lin, IEDM 2012, 2013, 2014 Lee, EDL 2014; Huang, IEDM 2014 implanted Si + selective epi reacted NiInAs Sun, IEDM 2013, 2014 Chang, IEDM

10 Self-aligned Planar InGaAs MIT W Mo Lin, IEDM 2012, 2013, 2014 Recess-gate process: CMOS-compatible Refractory ohmic contacts Extensive use of RIE I d (ma/ m) 1.0 L g =20 nm V gs -V t = 0.5 V 0.8 R on =224 m 0.4 V V ds (V) 10

11 Fabrication process Mo/W ohmic contact + SiO 2 hardmask SF 6, CF 4 anisotropic RIE Resist CF 4 :O 2 isotropic RIE SiO 2 W/Mo n + InGaAs/InP InGaAs/InAs InAlAs -Si InP Waldron, IEDM 2007 Cl 2 :N 2 anisotropic RIE Digital etch Finished device O 2 plasma H 2 SO 4 Pad Mo HfO 2 Lin, EDL 2014 Ohmic contact first, gate last Precise control of vertical (~1 nm), lateral (~5 nm) dimensions MOS interface exposed late in process 11

12 Highest performance InGaAs MOSFET Channel: In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As (t ch =9 nm) Gate oxide: HfO 2 (2.5 nm, EOT~ 0.5 nm) 3.45 ms/ m L g =70 nm: Exceeds best HEMT! Record g m,max = 3.45 ms/µm at V ds = 0.5 V R on = 190 Ω.µm Lin, EDL

13 Excess OFF-state current Transistor fails to turn off: I d (A/ m) 10-5 L g =500 nm V ds V ds =0.3~0.7 V step=50 mv V gs (V) OFF-state current enhanced with V ds Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM

14 Excess OFF-state current I d (A/ m) T=200 K V ds =0.7 V L g =80 nm 120 nm 280 nm 500 nm V gs -V t (V) Lin, EDL 2014 Lin, TED 2015 L g OFF-state current bipolar gain effect due to floating body I d (A/ m) I d (A/ m) 10-5 L g =500 nm w/ W/ BTBT+BJT w/o W/O BTBT+BJT L g =500 nm V ds V ds =0.3~0.7 V step=50 mv V gs (V) Simulations V ds =0.3~0.7 V step=50 mv V gs (V) 14

15 2. InGaAs FinFETs Intel Si Trigate MOSFETs 15

16 Bottom-up InGaAs FinFETs Aspect-Ratio Trapping Fiorenza, ECST 2010 Si Epi-grown fin inside trench Waldron, VLSI Tech

17 Top-down InGaAs FinFETs Radosavljevic, IEDM 2010 dry-etched fins 60 nm Kim, IEDM

18 Natarajan, IEDM 2014 g m [ms/ m] FinFET benchmarking g m normalized by width of gate periphery Si FinFETs channel aspect ratio InGaAs FinFETs W f [nm] State-of-the-art Si FinFETs: W f =7 nm 18

19 Kim, IEDM 2013 Natarajan, IEDM 2014 Oxland, EDL 2016 g m [ms/ m] FinFET benchmarking g m normalized by width of gate periphery Si FinFETs InGaAs FinFETs W f [nm] channel aspect ratio Narrowest InGaAs FinFET fin: W f =15 nm Best channel aspect ratio of InGaAs FinFET: 1.8 g m much lower than planar InGaAs MOSFETs Radosavljevic, IEDM 2011 Thathachary, VLSI

20 InGaAs MIT Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Sub-10 nm fin width Aspect ratio > 20 Vertical sidewalls Vardi, DRC 2014, EDL 2015, IEDM

21 InGaAs MIT High K SiO 2 W/Mo n + InGaAs L g Mo HSQ InGaAs δ Si InAlAs InP HSQ High K InGaAs Mo InP Vardi, VLSI Tech 2016 Vardi, EDL 2016 CMOS compatible process Mo contact-first process Fin etch mask left in place double-gate MOSFET 21

22 Most aggressively scaled FinFET W f =7 nm, L g =30 nm, H c =40 nm (AR=5.7), EOT=0.6 nm: 1E-3 1E-4 V DS =500 mv I d [ A/ m] V GS =-0.5 to 0.75 V GS =0.25 V I d [A/ m] 1E-5 1E-6 1E-7 1E-8 DIBL=90 mv/v S sat =100 mv/dev V DS =50 mv V DS [V] 1E V GS [V] g m max =900 S/ m Current normalized by 2xH c At V DS =0.5 V: g m =900 µs/µm R on =320 Ω.µm g m [ S/ m] V DS =0.5 V Vardi, EDL S sat =100 mv/dec V GS [V] 22

23 L g and EOT scaling g m [ S/ m] EOT V DS =0.5 V W f nm S sat [mv/dec] A: Al 2 O 3, EOT=2.8 nm B:Al 2 O 3 /HfO 2, EOT=1 nm C: HfO 2, EOT=0.6 nm EOT 60 mv/dec L g [nm] L g [nm] V T [V] I on [ A/ m] EOT I off =100 na/ m V DS =0.5 V -0.6 EOT L g [nm] L g [nm] Classical scaling with L g and EOT 23

24 g m max [ S/ m] V T [V] Fin width scaling (EOT=0.6 nm) W f =22 nm W f = 5 nm L g [nm] L g [nm] W f = 5 nm W f =22 nm S sat,min [mv/dec] W f =7 nm W f =12 nm W f =17 nm W f =22 nm L g [nm] Contaminated by gate leakage 60 mv/dec Non-ideal fin width scaling High D it (~5x10 12 cm -2.eV -1 ); mobility degradation; line edge roughness R on [ m] L g [nm] 7 nm W f =22 nm 24

25 InGaAs FinFETs: g m benchmarking g m normalized by width of gate periphery: H c W f H c Double gate Trigate g m [ms/ m] Si FinFETs InGaAs FinFETs W f [nm] First InGaAs FinFETs with W f <10 nm Record results for InGaAs FinFETs with W f < 25 nm Still short of Si FinFETs (though they operate at V DD =0.8 V) 25

26 InGaAs FinFETs: g m benchmarking g m normalized by fin width (FOM for density): H c W f W f H c Vardi, EDL 2016 g m /W f [ms/ m] Si FinFETs (V DD =0.8 V) InGaAs FinFETs W f [nm] Doubled g m /W f over earlier InGaAs FinFETs 26

27 Impact of fin width on V T InGaAs doped-channel FinFETs: 50 nm thick, N D ~10 18 cm -3 Vardi, IEDM 2015 T=90K Strong V T sensitivity for W f < 10 nm; much worse than Si Due to quantum effects Big concern for future manufacturing 27

28 3. Vertical nanowire MOSFET: ultimate scalable transistor L L c spacer L g Vertical NW MOSFET: uncouples footprint scaling from L g, L spacer, and L c scaling 28

29 Vertical nanowire MOSFET for 5 nm node 5 nm node Yakimets, TED 2015 Bao, ESSDERC % area reduction in 6T SRAM 19% area reduction in 32 bit multiplier Vertical NW: power, performance and area gains w.r.t. Lateral NW or FinFET 29

30 InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Vapor-Solid-Liquid (VLS) Technique Selective-Area Epitaxy Riel, MRS Bull 2014 Björk, JCG

31 InGaAs VNW MOSFETs by top-down MIT Key enabling technologies: RIE = BCl 3 /SiCl 4 /Ar chemistry Digital Etch (DE) = O 2 plasma oxidation H 2 SO 4 oxide removal 240 nm 15 nm Sub-20 nm NW diameter Aspect ratio > 10 Smooth sidewalls Zhao, EDL

32 InGaAs VNW Mechanical Stability for D<10 nm Difficult to reach 10 nm VNW diameter due to breakage 8 nm InGaAs VNWs: Yield = 0% Broken NW 32

33 InGaAs VNW Mechanical Stability for D<10 nm Difficult to reach 10 nm VNW diameter due to breakage Broken NW 8 nm InGaAs VNWs: Yield = 0% Water-based acid is problem: Surface tension (mn/m): Water: 72 Methanol: 22 IPA: 23 Solution: alcohol-based digital etch 33

34 Alcohol-Based Digital Etch 8 nm InGaAs VNWs Lu, EDL % HCl in DI water Yield = 0% 10% HCl in IPA Yield = 97% Broken NW Radial etch rate: 1.0 nm/cycle Radial etch rate: 1.0 nm/cycle Alcohol-based DE enables D < 10 nm 34

35 InGaAs Digital Etch First demonstration of D=5 nm diameter InGaAs VNW (Aspect Ratio > 40) Lu, EDL

36 InGaAs VNW-MOSFETs by top-down MIT Starting heterostructure: n + InGaAs, 70 nm i InGaAs, 80 nm n + InGaAs, 300 nm n + : cm 3 Si doping Top-down approach: flexible and manufacturable 36

37 Tomioka, Nature 2012 Persson, DRC 2012 Zhao, IEDM 2013 Process flow 37

38 NW-MOSFET I-V characteristics: D=40 nm I s A/ m) 300 V gs =-0.2 V to 0.7 V in 0.1 V step V ds (V) g m ( S/ m) V d = 0.5 V g m,pk =720 μs/μm Zhao, CSW V gs (V) 10-3 V ds =0.5 V Single nanowire MOSFET: L ch = 80 nm 3 nm Al 2 O 3 (EOT = 1.5 nm) g m,pk =720 V DS =0.5 V S lin =70 mv/dec, S sat =80 mv/dec DIBL=88 mv/v I s (A/ m) V ds =0.05 V S lin = 70 mv/dec S sat = 80 mv/dec DIBL = 88 mv/v V gs (V) 38

39 InGaAs VNW-MOSFETs Benchmark Berg, IEDM 2015 Tomioka, Nature 2012 g m,pk ( S/ m) V ds =0.5 V This work Tanaka, APEX 2010 Tomioka, IEDM 2011 Tomioka, Nature 2012 Persson, DRC 2012 Persson, EDL 2010 Zhao, IEDM 2013 Berg, IEDM 2015 This work S sat (mv/dec) Persson, DRC 2012 Tanaka, APEX 2010 Top down VNW MOSFETs as good as bottom up devices 39

40 How are we doing in terms of short-channel effects? Planar-MOSFET FinFET S lin : linear subthreshold swing L g = gate length λ c = electrostatic scaling length: f(t ox, t ch ) Ideal scaling VNW MOSFET Reasonable scaling behavior but Excessive D it del Alamo, J-EDS

41 4. InGaSb p type MOSFETs Planar InGaSb MOSFET demonstrations: Nainani, IEDM 2010 Takei, Nano Lett

42 InGaSb p type MIT Key enabling technology: BCl 3 /N 2 RIE [digital etch under development] 20 nm fins, 20 nm spacing Lu, IEDM nm fins, AR>13 Smallest W f = 15 nm Aspect ratio >10 Fin angle > 85 Dense fin patterns 42

43 Si-compatible contacts to p + -InAs Ni/Ti/Pt/Al on p + -InAs (circular TLMs): Lu, IEDM 2015 Record ρ c : 3.5x10-8 Ω.cm 2 at 400 o C 43

44 InGaSb p-type FinFETs Fin etch mask left in place double-gate MOSFET Channel: 10 nm In 0.27 Ga 0.73 Sb (compressively strained) Gate oxide: 4 nm Al 2 O 3 (EOT=1.8 nm) Lu, IEDM

45 InGaSb FinFET I-V characteristics L g = 100 nm, W f = 30 nm (AR=0.33) Normalized by conducting gate periphery First InGaSb FinFET Peak g m approaches best InGaSb planar MOSFETs Poor turn off g m ( S/ m) 100 This work (FinFET) In 0.27 Ga 0.73 Sb Planar MOSFETs Yuan, 2013 [7] Nainani, 2010 [8] Chu, 2014 [11] Xu, 2011 [12] Nagaiah, 2011 [13] GaSb GaSb In 0.36 Ga 0.64 Sb L g ( m) In 0.35 Ga 0.65 Sb In 0.2 Ga 0.8 Sb Lu, IEDM

46 InGaSb p-channel FinFETs (2 nd gen.) 200 L g = 100 nm, W f = 18 nm (AR=0.42) Channel: 7.5 nm In 0.4 Ga 0.6 Sb V g : 1 to -1.6 in -0.4V step, R tot :2.30e+03 - m Lu, CSW V d (V) g m ( S/ m) g m,max = 200 µs/µm Still poor turn-off need digital etch, better sidewall passivation 100 Gen 1 In 0.27 Ga 0.73 Sb Gen 1 In 0.2 Ga 0.8 Sb Planar MOSFETs Yuan, 2013 Nainani, 2010 Chu, 2014 Xu, 2011 Nagaiah, 2011 Gen 2 In 0.4 Ga 0.6 Sb GaSb GaSb L g ( m) In 0.35 Ga 0.65 Sb In 0.2 Ga 0.8 Sb In 0.36 Ga 0.64 Sb 46

47 5. Co-integration of SiGe p-mosfets and InGaAs MOSFETs on SOI SiGe InGaAs InGaAs n-mosfet SiGe p-mosfet SiO 2 Si Confined Epitaxial Lateral Overgrowth 6T-SRAM Czornomaz, VLSI Tech

48 Conclusions 1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Device performance still lacking for multigate designs 3. P-type InGaSb MOSFETs in their infancy 4. Many, MANY issues to work out: sub-10 nm fin/nanowire fabrication, self-aligned contacts, device asymmetry, introduction of mechanical stress, V T control, sidewall roughness, device variability, BTBT and parasitic HBT gain, trapping, selfheating, reliability, NW survivability, co-integration on n- and p-channel devices on Si, 48

49 Hype curve for III-V CMOS? # Papers on III-V CMOS at IEDM Year 49

50 A lot of work ahead but exciting future for III-V electronics 50

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