32nm Technology and Beyond
|
|
- Edwin Norris
- 5 years ago
- Views:
Transcription
1 32nm Technology and Beyond Paolo Gargini Chairman ITRS IEEE Fellow Director of Technology Strategy Intel Fellow ISS Europe 2009 P. Gargini 1
2 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 2
3 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 3
4 The Ideal MOS Transistor Metal Source Drain Gate Insulator Fully Surrounding Metal Electrode Fully Enclosed, Depleted Semiconductor High-K Gate Insulator Band Engineered Semiconductor Low Resistance Source/Drain From My Files ISS Europe 2009 P. Gargini 4
5 Staged Investment Aligned to Risks Step 5 Step 4 Step 3 Step 2 Step 1 External Research $/Year ~ 10 7 Research Pathfinding Development Manufacturing ~ 10 8 ~ 10 9 ~ Risk & Options High Moderate Low Create very Evaluate Focus on Synchronize Copy exactly, early on options, choices, and ramp rapidly options collaborate reduce risk integrate externally externally ISS Europe 2009 P. Gargini 5
6 The New Scaling Paradigm Classical Scaling L G T ox V DD L G T ox V DD Strain High-K Metal-G Tri-Gate New New ISS Europe 2009 P. Gargini 6
7 Strained P-Channel Transistor Mobility Innovation Strained N-Channel Transistor High Stress Film SiGe SiGe Source: Intel ISS Europe 2009 P. Gargini 7
8 Problem Statement ISS Europe 2009 P. Gargini 8
9 High-k k Dielectric reduces leakage substantially Gate Gate 1.2nm SiO 2 3.0nm High-k Silicon substrate Silicon substrate Benefits compared to current process technologies Capacitance Gate dielectric leakage High-k k vs. SiO 2 60% greater > 100x reduction November 4th, 2003 Benefit Much faster transistors Far cooler ISS Europe 2009 P. Gargini 9 10
10 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 10
11 ISS Europe 2009 IEDM 2007 P. Gargini 11
12 ISS Europe 2009 IEDM 2007 P. Gargini 12
13 ISS Europe 2009 IEDM 2007 P. Gargini 13
14 ISS Europe 2009 IEDM 2007 P. Gargini 14
15 ISS Europe 2009 IEDM 2007 P. Gargini 15
16 ISS Europe 2009 IEDM 2007 P. Gargini 16
17 ISS Europe 2009 IEDM 2007 P. Gargini 17
18 ISS Europe 2009 IEDM 2007 P. Gargini 18
19 ISS Europe 2009 IEDM 2007 P. Gargini 19
20 Scaling trend for inversion electrical TOX Metal Gate (different for NMOS & PMOS) 10 Electrical (Inv) Tox (nm) 1 High-k Silicon Substrate 350nm 250nm 180nm 130nm 90nm 65nm 45nm Gate Leakage (Rel.) ISS Europe 2009 IEDM 2007 P. Gargini 20
21 ISS Europe 2009 P. Gargini 21 IEDM 2007
22 ISS Europe 2009 P. Gargini 22 IEDM 2007
23 ISS Europe 2009 IEDM 2007 P. Gargini 23
24 ISS Europe 2009 P. Gargini 24 IEDM 2007
25 ISS Europe 2009 IEDM 2007 P. Gargini 25
26 ISS Europe 2009 P. Gargini 26 IEDM 2007
27 IEDM 2007 ISS Europe 2009 P. Gargini 27
28 Intel s 45nm Investment FAB INVESTMENT $9B FAB 11X New Mexico FAB 32 Arizona D1D Oregon FAB 28 Israel TECHNOLOGY INVESTMENT $1B 45nm High-k + Metal Gate Transistors SiGe Metal High-k SiGe PRODUCT INVESTMENT $2B Penryn Nehalem Silverthorne Others Source: Intel ISS Europe 2009 P. Gargini 28
29 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 29
30 A 32nm Logic Technology Featuring 2nd-Generation High-k k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171um 2 SRAM Cell Size in a 291Mb Array S. Natarajan,, M. Armstrong, M. Bost, R. Brain, M. Brazier, C-H C H Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He*, R. Heussner, R. James, I. Jin, C. Kenyon, K S. Klopcic, S-H. S Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae*, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone,, T. Troeger, C. Weber**, M. Yang, A. Yeoh, K. Zhang Logic Technology Development, *QRE, ** TCAD Intel Corporation IEDM 2008 P. Gargini
31 Process Features 32nm Groundrules 193nm Immersion Lithography 2 nd Generation High-K K + Metal Gate 4 th Generation Strained Silicon 9 Cu Interconnect Layers Low-k k CDO / SiCN dielectric Cu bump with Lead-free Packaging ISS Europe 2009 IEDM 2008 P. Gargini 31
32 Contacted Gate Pitch Transistor gate pitch of 112.5nm Continues 0.7x per generation scaling 1000 Contacted Gate Pitch (nm) Pitch 112.5nm Contacted Gate Pitch 0.7x every 2 years nm 180nm 130nm 90nm 65nm 45nm 32nm Technology Node Tightest contacted gate pitch reported for 32nm generation ISS Europe 2009 IEDM 2008 P. Gargini 32
33 SRAM Cells um 2 SRAM cell 10 SRAM Cell Area (um 2 ) 1 SRAM Cell Area 0.5x every 2 years nm 180nm 130nm 90nm 65nm 45nm 32nm Technology Node Transistor density doubles every two years ISS Europe 2009 IEDM 2008 P. Gargini 33
34 SRAM Array Density SRAM array density achieves 4.2 Mb/mm 2 Includes row/column drivers and other circuitry 10.0 SRAM Array Density (Mb/mm 2 ) Mb/mm nm 65nm 45nm 32nm Array density scales at ~2X per generation ISS Europe 2009 IEDM 2008 P. Gargini 34
35 Key Transistor Features 30nm gate length with 112.5nm contacted gate pitch 2 nd generation Hi-k k + Metal Gate 0.9nm EOT Hi-K K with dual workfunction metal gate electrodes Continued use of Replacement Metal Gate approach Metal gate deposition after high temperature anneals Integrated with strained silicon process Transistor mask count same as 45nm Adds ~4% process cost over non hi-k/mg 4 th generation of strained silicon ISS Europe 2009 IEDM 2008 P. Gargini 35
36 NMOS I vs. DSAT I OFF 1000 Vdd=1.0V Ioff (na/um) nm nm 1 45nm: Mistry, 2007 IEDM Idsat (ma/um) 1.55 ma/µm m at I OFF = 100 na/µm 14% better than 45nm ISS Europe 2009 IEDM 2008 P. Gargini 36
37 PMOS I vs. DSAT I OFF 1000 Vdd=1.0V Ioff (na/um) nm: Mistry, 2007 IEDM 45nm nm Idsat (ma/um) 1.31 ma/µm m at I OFF = 100 na/µm 22% better than 45nm 32nm PMOS Idsat almost equal to 45nm NMOS Idsat! ISS Europe 2009 IEDM 2008 P. Gargini 37
38 Transistor Performance vs. Gate Pitch IDSAT (ma/um) V, 100 na/µm 90nm: Mistry, 2004 VLSI 65nm: Tyagi, 2005 IEDM 45nm: Mistry, 2007 IEDM Gate Pitch (Generation) NMOS PMOS 320nm (90nm) 220nm (65nm) Contacted Gate Pitch (nm) 160nm 112.5nm (45nm) (32nm) 100 Highest reported drive current at tightest reported gate pitch Simultaneous performance and density improvement ISS Europe 2009 IEDM 2008 P. Gargini 38
39 Interconnects Metal pitches match transistor pitch Graduated upper level pitches optimize density & performance Extensive use of low-k k ILD and SiCN ISS Europe 2009 IEDM 2008 P. Gargini 39
40 SRAM Yield Defect Density (log scale) 2 Years 32nm SRAM yield maintains 2-year 2 cadence ISS Europe 2009 IEDM 2008 P. Gargini 40
41 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 41
42 Options and Challenges (1) Substrate Engineering (110) vs. (100) crystal orientation + Increased p-channel mobility? Impact on n-channel mobility Hole Mobility (cm 2 /Vs) (100) Mobility (110) Mobility Hole <110> Stress (MPa) <110> (100) <100> <110> <100> (110) <111> <110> ISS Europe 2009 P. Gargini 42
43 Options and Challenges (2) Multi-Gate FETs + Improved electrostatics + Steeper sub-threshold slope? Parasitic resistance? Parasitic capacitance FinFET GAA Wrap around Gate Source-drain Fin ISS Europe 2009 P. Gargini 43
44 Picking the Right High-µ Material Material Property Electron mobility Hole mobility Bandgap (ev) Dielectric constant Si Ge Why Ge? More symmetric and higher carrier mobilities Highest hole mobility Easier integration on Si Lower temperature processing ISS Europe 2009 P. Gargini 44
45 ISS Europe 2009 IEDM 2008 P. Gargini 45
46 Increasing Electron Mobility Increased mobility in the transistor channel leads to higher performance and less energy consumption W IDSAT µ COX L Relative mobility Compound Semiconductors Si GaAs InAs InSb Compound semiconductors have higher electron mobility than Si; InSb (indium antimonide) is highest of all ISS Europe 2009 P. Gargini 46
47 Depletion and Enhancement Mode Gate Source Drain Al x In 1-x Sb barrier InSb QW Source Recessed Gate Al x In 1-x Sb barrier Drain Etch Stop Layer Semi-insulating GaAs substrate for epitaxial growth Semi-insulating GaAs substrate for epitaxial growth Depletion mode (Normally ON) Enhancement mode (Normally OFF) A novel gate recess process is used to fabricate enhancement mode InSb QWFETs IEDM 2005 ISS Europe 2009 P. Gargini 47
48 Speed, Power, Performance Cut-off Frequency, ft [GHz] InSb E-mode QWFET (LG = 85nm) VDS = 0.3V, 0.5V, 0.6V 10X power 1.5X speed Silicon MOSFET (LG = 60nm) VDS = 0.5V, 0.7V, 0.9V, 1.2V DC Power Dissipation [µw/µm] InSb QWFETs show > 10x reduction in active power dissipation compared to Si MOSFETs ISS Europe 2009 P. Gargini 48
49 NMOS 2007 IEDM ISS Europe 2009 P. Gargini 49
50 New Material Integration for High- Performance Transistors N-channel built on Silicon (IEDM 2007) Background: III-V Integration with Silicon Opportunity Higher mobility allows radical voltage scaling for 10x power reduction New material and deposition methods already in use starting with 45nm node Key Challenges Integrate with Silicon Infrastructure Integration with Conventional Design Comparable Density and Cost InGaAs QWFET on Si [L G = 80nm] Si Peak f T > 400GHz at V cc = 0.5V III-V V Transistors May Enable Improved Performance and Lower Power Beyond What Silicon Can Provide Marko Radosavljevic, IEDM 2007 ISS Europe 2009 P. Gargini 50
51 New Material Integration for High- Performance Transistors P-channel with compressive strain (IEDM 2008) Ti/Au Source 6nm p-doped 10nm p-doped 3nm undoped Be δ-doping 7nm undoped Ti/Au Gate L G Ti/Au Drain low resistance cap Alxx In 1-x Sb top barrier Al x In 1-x Sb top barrier Al x In 1-x Sb spacer 5nm InSb quantum well 3 µ m undoped Al x In 1-x Sb bottom barrier 200nm Al y In 1-y S b interfacial layer Semi-insulating GaAs substrate Peak f T > 140 GHz at Vcc = -0.5V High performance III-V p-channel Demonstrated with InSb Compressive strain to raise mobility 10x reduction in power vs equiv Si Highest performance P-channel reported to date Source 40nm gate length Gate Drain P-channel III-V in partnership with Qinetiq Marko Radosavljevic, IEDM 2008 ISS Europe 2009 P. Gargini 51
52 Transistors/Die Intel Sees No End to Moore s s Law 10µm 13 Bipolar PMOS NMOS CMOS Voltage Scaling Data (Moore) Memory Microprocessor Kilo Xtor 1µm 100nm 10nm Mega Xtor Pwr Eff Scaling Giga Xtor New Nano- structures Beyond CMOS? Spin based? Molecular? Other? Tera Xtor ISS Europe 2009 P. Gargini 52
53 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 53
54 Conclusions 45nm and 32nm technologies demonstrate that multiple Technical Red Brick Walls of the past have been overcome Completed development phase on 32nm CMOS On track for production readiness in Q4 09 Multiple viable technical options exist for the next years Device technology will not be a show stopper for the foreseeable future Moore s s Law is Alive and Well! ISS Europe 2009 P. Gargini 54
Logic Technology Development, *QRE, ** TCAD Intel Corporation
A 32nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171um 2 SRAM Cell Size in a 291Mb Array S. Natarajan, M. Armstrong, M. Bost, R. Brain, M.
More informationA 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors
A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann*, K. Johnson#,
More informationFin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018
Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations OUTLINE Background FinFET Future Roadmap Keeping up w/ Moore s Law
More informationTransistor Scaling in the Innovation Era. Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011
Transistor Scaling in the Innovation Era Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W
More informationChallenges and Innovations in Nano CMOS Transistor Scaling
Challenges and Innovations in Nano CMOS Transistor Scaling Tahir Ghani Intel Fellow Logic Technology Development October, 2009 Nikkei Presentation 1 Outline Traditional Scaling Traditional Scaling Limiters,
More informationAdvanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm
EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1 Outline
More informationSoC Technology in the Era of 3-D Tri-Gate Transistors for Low Power, High Performance, and High Density Applications
SoC Technology in the Era of 3-D Tri-Gate Transistors for Low Power, High Performance, and High Density Applications Vice President, Technology Manufacturing Group Intel Corporation August 2013 Outlines
More informationAlternative Channel Materials for MOSFET Scaling Below 10nm
Alternative Channel Materials for MOSFET Scaling Below 10nm Doug Barlage Electrical Requirements of Channel Mark Johnson Challenges With Material Synthesis Introduction Outline Challenges with scaling
More informationECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices
ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor
More informationIntel s s Silicon Power Savings Strategy
Intel s s Silicon Power Savings Strategy Keeping Moore s s Law Alive and Well Paolo Gargini Intel Fellow and Director, Technology Strategy Agenda Moore s s Law and scaling The power challenge Looking ahead
More informationRecord I on (0.50 ma/μm at V DD = 0.5 V and I off = 100 na/μm) 25 nm-gate-length ZrO 2 /InAs/InAlAs MOSFETs
Record I on (0.50 ma/μm at V DD = 0.5 V and I off = 100 na/μm) 25 nm-gate-length ZrO 2 /InAs/InAlAs MOSFETs Sanghoon Lee 1*, V. Chobpattana 2,C.-Y. Huang 1, B. J. Thibeault 1, W. Mitchell 1, S. Stemmer
More informationAlternatives to standard MOSFETs. What problems are we really trying to solve?
Alternatives to standard MOSFETs A number of alternative FET schemes have been proposed, with an eye toward scaling up to the 10 nm node. Modifications to the standard MOSFET include: Silicon-in-insulator
More informationFinFET Devices and Technologies
FinFET Devices and Technologies Jack C. Lee The University of Texas at Austin NCCAVS PAG Seminar 9/25/14 Material Opportunities for Semiconductors 1 Why FinFETs? Planar MOSFETs cannot scale beyond 22nm
More informationEnabling Breakthroughs In Technology
Enabling Breakthroughs In Technology Mike Mayberry Director of Components Research VP, Technology and Manufacturing Group Intel Corporation June 2011 Defined To be defined Enabling a Steady Technology
More informationDesign Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 81 Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness Alpana
More informationParameter Optimization Of GAA Nano Wire FET Using Taguchi Method
Parameter Optimization Of GAA Nano Wire FET Using Taguchi Method S.P. Venu Madhava Rao E.V.L.N Rangacharyulu K.Lal Kishore Professor, SNIST Professor, PSMCET Registrar, JNTUH Abstract As the process technology
More informationTrends and Challenges in VLSI Technology Scaling Towards 100nm
Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends
More informationIntel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors
Intel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors Mark Bohr Intel Senior Fellow Logic Technology Development Kaizad Mistry 45 nm Program Manager Logic Technology Development
More informationITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations
Workshop on Frontiers of Extreme Computing Santa Cruz, CA October 24, 2005 ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Peter M. Zeitzoff Outline Introduction MOSFET scaling and
More informationIII-V CMOS: the key to sub-10 nm electronics?
III-V CMOS: the key to sub-10 nm electronics? J. A. del Alamo Microsystems Technology Laboratories, MIT 2011 MRS Spring Meeting and Exhibition Symposium P: Interface Engineering for Post-CMOS Emerging
More informationNewer process technology (since 1999) includes :
Newer process technology (since 1999) includes : copper metalization hi-k dielectrics for gate insulators si on insulator strained silicon lo-k dielectrics for interconnects Immersion lithography for masks
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 11/01/2007 MOSFETs Lecture 5 Announcements HW7 set is due now HW8 is assigned, but will not be collected/graded. MOSFET Technology Scaling Technology
More informationIntel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells
Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration Intel 1 What are We Announcing? Intel has fabricated fully-functional
More informationEE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements Sign up for Piazza if you haven t already 2 1 Assigned Reading R.H.
More informationIntegrated CMOS Tri-Gate Transistors: Paving the Way to Future Technology Generations
Page 1 Integrated CMOS Tri-Gate Transistors: Paving the Way to Future Technology Generations Robert S. Chau, Intel Senior Fellow Copyright Intel Corporation 2006. *Third-party brands and names are the
More informationIntel Technology Journal
Volume 06 Issue 02 Published, May 16, 2002 ISSN 1535766X Intel Technology Journal Semiconductor Technology and Manufacturing Transistor Elements for 30nm Physical Gate Length and Beyond A compiled version
More informationInnovation to Advance Moore s Law Requires Core Technology Revolution
Innovation to Advance Moore s Law Requires Core Technology Revolution Klaus Schuegraf, Ph.D. Chief Technology Officer Silicon Systems Group Applied Materials UC Berkeley Seminar March 9 th, 2012 Innovation
More informationChapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics
Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1 Topics What is semiconductor Basic semiconductor devices Basics of IC processing CMOS technologies 2006/9/27 2 1 What is Semiconductor
More informationSession 10: Solid State Physics MOSFET
Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)
More informationECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor
More informationOpportunities and Challenges for Nanoelectronic Devices and Processes
The Sixth U.S.-Korea Forum on Nanotechnology, April 28-29, 2009, Las Vegas, NV Opportunities and Challenges for Nanoelectronic Devices and Processes Yoshio Nishi Professor, Electrical Engineering, Material
More informationSub-30 nm InAs Quantum-Well MOSFETs with Self-Aligned Metal Contacts and Sub-1 nm EOT HfO 2 Insulator
Sub-30 nm InAs Quantum-Well MOSFETs with Self-Aligned Metal Contacts and Sub-1 nm EOT HfO 2 Insulator Jianqiang Lin, Dimitri A. Antoniadis, and Jesús A. del Alamo Microsystems Technology Laboratories,
More informationFinFET vs. FD-SOI Key Advantages & Disadvantages
FinFET vs. FD-SOI Key Advantages & Disadvantages Amiad Conley Technical Marketing Manager Process Diagnostics & Control, Applied Materials ChipEx-2014, Apr 2014 1 Moore s Law The number of transistors
More informationChapter 3 Basics Semiconductor Devices and Processing
Chapter 3 Basics Semiconductor Devices and Processing 1 Objectives Identify at least two semiconductor materials from the periodic table of elements List n-type and p-type dopants Describe a diode and
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 11/6/2007 MOSFETs Lecture 6 BJTs- Lecture 1 Reading Assignment: Chapter 10 More Scalable Device Structures Vertical Scaling is important. For example,
More informationMSE 410/ECE 340: Electrical Properties of Materials Fall 2016 Micron School of Materials Science and Engineering Boise State University
MSE 410/ECE 340: Electrical Properties of Materials Fall 2016 Micron School of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures
More informationInGaAs Nanoelectronics: from THz to CMOS
InGaAs Nanoelectronics: from THz to CMOS J. A. del Alamo Microsystems Technology Laboratories, MIT IEEE International Conference on Electron Devices and Solid-State Circuits Hong Kong, June 3, 2013 Acknowledgements:
More informationTransistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.
Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-
More informationAtomic-layer deposition of ultrathin gate dielectrics and Si new functional devices
Atomic-layer deposition of ultrathin gate dielectrics and Si new functional devices Anri Nakajima Research Center for Nanodevices and Systems, Hiroshima University 1-4-2 Kagamiyama, Higashi-Hiroshima,
More informationLecture #29. Moore s Law
Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday
More informationLeakage Current in Low Standby Power and High Performance Devices: Trends and Challenges
Leakage Current in Low Standby Power and High Performance Devices: Trends and Challenges (Invited Paper) Geoffrey C-F Yeap Motorola Inc., DigitalDNA Laboratories, 3501 Ed Bluestein Blvd., MD: K10, Austin,
More informationLecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 33-1 Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007 Contents: 1. MOSFET scaling
More informationIII-V CMOS: Quo Vadis?
III-V CMOS: Quo Vadis? J. A. del Alamo, X. Cai, W. Lu, A. Vardi, and X. Zhao Microsystems Technology Laboratories Massachusetts Institute of Technology Compound Semiconductor Week 2018 Cambridge, MA, May
More informationManufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel
Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel Paolo A. Gargini Director Technology Strategy Intel Fellow 1 Agenda 2-year cycle Copy Exactly Conclusions 2 I see no reason
More informationSub-micron technology IC fabrication process trends SOI technology. Development of CMOS technology. Technology problems due to scaling
Goodbye Microelectronics Welcome Nanoelectronics Sub-micron technology IC fabrication process trends SOI technology SiGe Tranzistor in 50nm process Virus The thickness of gate oxide= 1.2 nm!!! Today we
More informationADVANCED MATERIALS AND PROCESSES FOR NANOMETER-SCALE FINFETS
ADVANCED MATERIALS AND PROCESSES FOR NANOMETER-SCALE FINFETS Tsu-Jae King, Yang-Kyu Choi, Pushkar Ranade^ and Leland Chang Electrical Engineering and Computer Sciences Dept., ^Materials Science and Engineering
More informationDrain. Drain. [Intel: bulk-si MOSFETs]
1 Introduction For more than 40 years, the evolution and growth of very-large-scale integration (VLSI) silicon-based integrated circuits (ICs) have followed from the continual shrinking, or scaling, of
More informationFuture MOSFET Devices using high-k (TiO 2 ) dielectric
Future MOSFET Devices using high-k (TiO 2 ) dielectric Prerna Guru Jambheshwar University, G.J.U.S. & T., Hisar, Haryana, India, prernaa.29@gmail.com Abstract: In this paper, an 80nm NMOS with high-k (TiO
More informationMOSFET & IC Basics - GATE Problems (Part - I)
MOSFET & IC Basics - GATE Problems (Part - I) 1. Channel current is reduced on application of a more positive voltage to the GATE of the depletion mode n channel MOSFET. (True/False) [GATE 1994: 1 Mark]
More informationNanoscale III-V CMOS
Nanoscale III-V CMOS J. A. del Alamo Microsystems Technology Laboratories Massachusetts Institute of Technology SEMI Advanced Semiconductor Manufacturing Conference Saratoga Springs, NY; May 16-19, 2016
More informationInGaAs MOSFETs for CMOS:
InGaAs MOSFETs for CMOS: Recent Advances in Process Technology J. A. del Alamo, D. Antoniadis, A. Guo, D.-H. Kim 1, T.-W. Kim 2, J. Lin, W. Lu, A. Vardi and X. Zhao Microsystems Technology Laboratories,
More informationINTRODUCTION: Basic operating principle of a MOSFET:
INTRODUCTION: Along with the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available whose Gate input is electrically insulated from the main current carrying
More information420 Intro to VLSI Design
Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem
More informationNanometer-Scale InGaAs Field-Effect Transistors for THz and CMOS Technologies
Nanometer-Scale InGaAs Field-Effect Transistors for THz and CMOS Technologies J. A. del Alamo Microsystems Technology Laboratories, MIT ESSDERC-ESSCIRC 2013 Bucharest, Romania, September 16-20, 2013 Acknowledgements:
More informationIntel s High-k/Metal Gate Announcement. November 4th, 2003
Intel s High-k/Metal Gate Announcement November 4th, 2003 1 What are we announcing? Intel has made significant progress in future transistor materials Two key parts of this new transistor are: The gate
More informationIntroducing 7-nm FinFET technology in Microwind
Introducing 7-nm FinFET technology in Microwind Etienne SICARD Professor INSA-Dgei, 135 Av de Rangueil 31077 Toulouse France www.microwind.org email: Etienne.sicard@insa-toulouse.fr This paper describes
More informationIntel s Breakthrough in High-K Gate Dielectric Drives Moore s Law Well into the Future
Page 1 Intel s Breakthrough in High-K Gate Dielectric Drives Moore s Law Well into the Future Robert S. Chau Intel Fellow, Technology and Manufacturing Group Director, Transistor Research Intel Corporation
More informationISSCC 2003 / SESSION 1 / PLENARY / 1.1
ISSCC 2003 / SESSION 1 / PLENARY / 1.1 1.1 No Exponential is Forever: But Forever Can Be Delayed! Gordon E. Moore Intel Corporation Over the last fifty years, the solid-state-circuits industry has grown
More informationGallium nitride (GaN)
80 Technology focus: GaN power electronics Vertical, CMOS and dual-gate approaches to gallium nitride power electronics US research company HRL Laboratories has published a number of papers concerning
More information3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET)
3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET) Pei W. Ding, Kristel Fobelets Department of Electrical Engineering, Imperial College London, U.K. J. E. Velazquez-Perez
More informationFinFET-based Design for Robust Nanoscale SRAM
FinFET-based Design for Robust Nanoscale SRAM Prof. Tsu-Jae King Liu Dept. of Electrical Engineering and Computer Sciences University of California at Berkeley Acknowledgements Prof. Bora Nikoli Zheng
More informationSession 3: Solid State Devices. Silicon on Insulator
Session 3: Solid State Devices Silicon on Insulator 1 Outline A B C D E F G H I J 2 Outline Ref: Taurand Ning 3 SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted
More informationDG-FINFET LOGIC DESIGN USING 32NM TECHNOLOGY
International Journal of Knowledge Management & e-learning Volume 3 Number 1 January-June 2011 pp. 1-5 DG-FINFET LOGIC DESIGN USING 32NM TECHNOLOGY K. Nagarjuna Reddy 1, K. V. Ramanaiah 2 & K. Sudheer
More informationComparison of 32nm High-k Metal Gate Predictive Technology Model CMOS and MOSFET-Like CNFET compact Model Based Domino logic Circuits
Comparison of 32nm High-k Metal Gate Predictive Technology Model CMOS and MOSFET-Like CNFET compact Model Based Domino logic Circuits Saravana Maruthamuthu, Wireless Group Infineon Technologies India Private
More informationA New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight-Pitch Process
A New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight-Pitch Process Jianqiang Lin, Xin Zhao, Tao Yu, Dimitri A. Antoniadis, and Jesús A. del Alamo Microsystems Technology Laboratories,
More information45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11. Process-induced Variability I: Random
45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11 Process-induced Variability I: Random Random Variability Sources and Characterization Comparisons of Different MOSFET
More informationECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline:
ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline: Metal-Semiconductor Junctions MOSFET Basic Operation MOS Capacitor Things you should know when you leave Key Questions What is the
More informationInAs Quantum-Well MOSFET for logic and microwave applications
AWAD June 29 th 2012 Accelerating the next technology revolution InAs Quantum-Well MOSFET for logic and microwave applications T.-W. Kim, R. Hill, C. D. Young, D. Veksler, L. Morassi, S. Oktybrshky 1,
More informationFDSOI for Low Power System on Chip. M.HAOND STMicroelectronics, Crolles, France
FDSOI for Low Power System on Chip M.HAOND STMicroelectronics, Crolles, France OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis
More information40nm Node CMOS Platform UX8
FUKAI Toshinori, IKEDA Masahiro, TAKAHASHI Toshifumi, NATSUME Hidetaka Abstract The UX8 is the latest process from NEC Electronics. It uses the most advanced exposure technology to achieve twice the gate
More informationPerformance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE
RESEARCH ARTICLE OPEN ACCESS Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE Mugdha Sathe*, Dr. Nisha Sarwade** *(Department of Electrical Engineering, VJTI, Mumbai-19)
More informationJack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationIntel Technology Journal
Volume 06 Issue 02 Published, May 16, 2002 ISSN 1535766X Intel Technology Journal Semiconductor Technology and Manufacturing This issue of the Intel Technology Journal describes Intel's state-of-the-art
More informationActive Technology for Communication Circuits
EECS 242: Active Technology for Communication Circuits UC Berkeley EECS 242 Copyright Prof. Ali M Niknejad Outline Comparison of technology choices for communication circuits Si npn, Si NMOS, SiGe HBT,
More informationDESIGN OF 20 nm FinFET STRUCTURE WITH ROUND FIN CORNERS USING SIDE SURFACE SLOPE VARIATION
Journal of Electron Devices, Vol. 18, 2013, pp. 1537-1542 JED [ISSN: 1682-3427 ] DESIGN OF 20 nm FinFET STRUCTURE WITH ROUND FIN CORNERS USING SIDE SURFACE SLOPE VARIATION Suman Lata Tripathi and R. A.
More informationZota, Cezar B.; Lindelow, Fredrik; Wernersson, Lars Erik; Lind, Erik
InGaAs tri-gate MOSFETs with record on-current Zota, Cezar B.; Lindelow, Fredrik; Wernersson, Lars Erik; Lind, Erik Published in: 6 IEEE International Electron Devices Meeting, IEDM 6 DOI:.9/IEDM.6.7886
More informationNanoscale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs
Nanoscale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs J. A. del Alamo Microsystems Technology Laboratories, MIT Purdue University, West Lafayette, IN; September 29,
More informationIntroduction to VLSI ASIC Design and Technology
Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics
More information2014, IJARCSSE All Rights Reserved Page 1352
Volume 4, Issue 3, March 2014 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Double Gate N-MOSFET
More informationINTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No 3, 2010
Low Power CMOS Inverter design at different Technologies Vijay Kumar Sharma 1, Surender Soni 2 1 Department of Electronics & Communication, College of Engineering, Teerthanker Mahaveer University, Moradabad
More informationDesign and Analysis of Double Gate MOSFET Devices using High-k Dielectric
International Journal of Electrical Engineering. ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 53-60 International Research Publication House http://www.irphouse.com Design and Analysis of Double Gate
More informationPractical Information
EE241 - Spring 2010 Advanced Digital Integrated Circuits TuTh 3:30-5pm 293 Cory Practical Information Instructor: Borivoje Nikolić 550B Cory Hall, 3-9297, bora@eecs Office hours: M 10:30am-12pm Reader:
More informationAdvanced PDK and Technologies accessible through ASCENT
Advanced PDK and Technologies accessible through ASCENT MOS-AK Dresden, Sept. 3, 2018 L. Perniola*, O. Rozeau*, O. Faynot*, T. Poiroux*, P. Roseingrave^ olivier.faynot@cea.fr *Cea-Leti, Grenoble France;
More informationImproving CMOS Speed and Switching Energy with Vacuum-Gap Structures
Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures Chenming Hu and Je Min Park Univ. of California, Berkeley -1- Outline Introduction Background and Motivation MOSFETs with Vacuum-Spacer
More informationScaling Electronics: Kelin J. Kuhn Intel Fellow. Kelin Kuhn / MIT / April 4 th
Scaling Electronics: Trends and Bottlenecks Kelin J. Kuhn Intel Fellow Director of Advanced Device Technology 1 Moore s Law Scaling of the SRAM 10.00 Bitcell Area ( m 2 ) 1.00 0.10 2X bitcell area scaling
More informationLecture 8. Thin-Body MOSFET s Process II. Source/Drain Technologies Threshold Voltage Engineering
Atom Probe Tomography for Dopants in FinFETs Lecture 8 A.K. Kambham (imec), VLSI-T 2012 Thin-Body MOSFET s Process II Source/Drain Technologies Threshold Voltage Engineering Reading: multiple research
More informationSustaining the Si Revolution: From 3D Transistors to 3D Integration
Sustaining the Si Revolution: From 3D Transistors to 3D Integration Tsu Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA USA February 23, 2015
More informationState-of-the-art device fabrication techniques
State-of-the-art device fabrication techniques! Standard Photo-lithography and e-beam lithography! Advanced lithography techniques used in semiconductor industry Deposition: Thermal evaporation, e-gun
More informationThe 3 D Tri Gate transistor is a variant of the FinFET developed at UC Berkeley, and is being used in Intel s 22nmgeneration. microprocessors.
On May 4, 2011, Intel Corporation announced what it called the most radical shift in semiconductor technology in 50 years. A new 3 dimensional transistor design will enable the production of integrated
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationField-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;
Chapter 3 Field-Effect Transistors (FETs) 3.1 Introduction Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism; The concept has been known
More informationFundamentals of III-V Semiconductor MOSFETs
Serge Oktyabrsky Peide D. Ye Editors Fundamentals of III-V Semiconductor MOSFETs Springer Contents 1 Non-Silicon MOSFET Technology: A Long Time Coming 1 Jerry M. Woodall 1.1 Introduction 1 1.2 Brief and
More informationLow-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering
Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance
More informationPractical Information
EE241 - Spring 2013 Advanced Digital Integrated Circuits MW 2-3:30pm 540A/B Cory Practical Information Instructor: Borivoje Nikolić 509 Cory Hall, 3-9297, bora@eecs Office hours: M 11-12, W 3:30pm-4:30pm
More informationEECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141
EECS 151/251A Spring 2019 Digital Design and Integrated Circuits Instructors: Wawrzynek Lecture 8 EE141 From the Bottom Up IC processing CMOS Circuits (next lecture) EE141 2 Overview of Physical Implementations
More informationDevice architectures for the 5nm technology node and beyond Nadine Collaert
Device architectures for the 5nm technology node and beyond Nadine Collaert Distinguished member of technical staff, imec Outline Introduction Beyond FinFET: lateral nanowires and vertical transistors
More informationLSI ON GLASS SUBSTRATES
LSI ON GLASS SUBSTRATES OUTLINE Introduction: Why System on Glass? MOSFET Technology Low-Temperature Poly-Si TFT Technology System-on-Glass Technology Issues Conclusion System on Glass CPU SRAM DRAM EEPROM
More informationEC0306 INTRODUCTION TO VLSI DESIGN
EC0306 INTRODUCTION TO VLSI DESIGN UNIT I INTRODUCTION TO MOS CIRCUITS Why VLSI? Integration improves the design: o lower parasitics = higher speed; o lower power; o physically smaller. Integration reduces
More informationDesign & Simulation of Multi Gate Piezoelectric FET Devices for Sensing Applications
Design & Simulation of Multi Gate Piezoelectric FET Devices for Sensing Applications Sunita Malik 1, Manoj Kumar Duhan 2 Electronics & Communication Engineering Department, Deenbandhu Chhotu Ram University
More information6.012 Microelectronic Devices and Circuits
Page 1 of 13 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Microelectronic Devices and Circuits Final Eam Closed Book: Formula sheet provided;
More information