SoC Technology in the Era of 3-D Tri-Gate Transistors for Low Power, High Performance, and High Density Applications

Transcription

1 SoC Technology in the Era of 3-D Tri-Gate Transistors for Low Power, High Performance, and High Density Applications Vice President, Technology Manufacturing Group Intel Corporation August 2013

2 Outlines Industry Leading Intel 22 nm SoC Technology Moore s Law in the Era of 3-D Tri-gate Transistor Summary p. 2

3 The 3-D Tri-gate Transistor Era Has Arrived with 22nm Technology Gate Oxide Silicon Substrate Intel 22 nm Ivy Bridge Microprocessor World s first product based on 22nm 3-D Tri-Gate transistor introduced in 2012 p. 3

4 3-D Tri-gate Transistor Foundation for SoC Platform Technology Voltage Ceiling High Density Interconnect Density 5 V 3 V 1 V Raise Transistor Voltage Ceiling CPU Mixed Signals RF Capability Device Dense NF min 1 x 10 x Digital Analog RF 100 x Lower Transistor Leakage Floor Leakage Floor p. 4

5 Lower Transistor Leakage Transistor Performance vs. Leakage 1x 65nm 45nm 32nm 22nm Server 0.1x Desktop 0.01x Laptop Ultrabook 0.001x Tablet Pocket Device Higher Transistor Performance (Switching Speed) 3-D Tri-gate transistor technology drive key SoC vectors in performance, low power, and integration to optimize for a wider range of SoC products p. 5

6 SoC 3-D Tri-gate Transistors p. 6

7 Tri-gate SoC Transistor Family (a)high Speed (HP/SP) Logic (b) Low Power (LP/ULP) Logic (c) High Voltage (TG) Main types of transistors High performance, Low leakage and high voltage p. 7

8 Tri-Gate SoC Dual Gate Process Logic -High Speed (HP/SP) -Low Power (LP/ULP) High Voltage Dual gate flow : two distinct gate electrodes/gate dielectrics p. 8

9 22 nm Tri-gate SoC Transistor Characteristics Transistor Type High Speed Logic Low Power Logic High Voltage Options High Performance (HP) Standard Perf./ Power (SP) Low Power (LP) Ultra Low Power (ULP) 1.8 V 3.3 V Vdd (Volt) 0.75 / / / / /1.8/ / >5 Gate Pitch (nm) min. 180 min. 450 Lgate (nm) min. 80 min. 280 N/PMOS Idsat/Ioff (ma/um) 1.08/ 0.75 V, 0.71 / 0.75 V, 0.41 / 0.75 V 0.35 / 0.75 V 0.92 / 1.8 V 1.0 / 3.3 V 100 na/um 1 na/um 30 pa/um 15 pa/um 10 pa/um 10 pa/um Mix-and-match flexibility of transistor types Leading edge performance and low power for 22nm SoC products p. 9

10 Sub-threshold Slope (mv/decade) Near Ideal Sub-threshold Slope Logic Transistor 32 nm Planar 1.8 V HV Transistor 32 nm Planar nm 3-D Tri-gate 22 nm 3-D Tri-gate Poly CD (nm) S.S. = 60 mv/dec Ideal S. S. = ln (kt/q) ~ 60 mv Both logic and high voltage transistors show near ideal sub-threshold slope with great short channel control p. 10

11 Vtp (V) Vtn (V) Excellent Short Channel Control Leads to Vmin Reduction nm - Logic [2] Logic (SP) Logic (SP) 32 nm - Low Power [2] L eff (nm) Lower Logic (LP/ULP) Lower Logic (LP/ULP) NMOS PMOS 32 nm - Logic [2] 32 nm - Low Power [2] Excellent short channel control of 22 nm tri-gate SoC reflects in 100 ~200 mv Vt reduction in all transistor types p. 11

12 Ioff (na/um) Ioff (na/um) Lower Leakage Superior 22nm Tri-gate SoC High Performance Transistors NMOS V 32 nm [3] Logic (HP) V 100 na Logic 32 nm [3] (HP) 1 1 na Logic (SP) 1 1 na Logic (SP) pa nm [3] 30 pa 15 pa Low Power (LP) Low Power (ULP) nm [3] 30 pa 30 pa pa Low Power (LP) Low Power (ULP) IDNsat (ma/um) IDPsat (ma/um) Higher Performance Higher Performance High performance transistor Idsat and leakage improvement with pitch scaling p. 12

13 Ioff (na/um) Power I Superior 22 nm Tri-gate SoC Low Leakage Transistor = a CV ( I 2 f + + I V I leakage + I leakage gate, on gate, off off nm Tri-gate NMOS 22 nm Tri-gate PMOS 32 nm planar [3] I I 2 junction R ) Gate Leakage ( I gate ) Source Gate Drain 0.1 Sub-threshold Leakage ( I off, I subthreshold ) Source Gate Drain nm planar [3] 22 nm tri-gate Junction Leakage ( I junction ) Source Gate Drain Lower Leakage Ijunction (na/um) 22 nm LP Ioff vs. GIDL/I junction superior than 32 nm planar LP p. 13

14 Ioff (A/um) Ioff (A/um) Lower Leakage Superior 22 nm SoC High Voltage I/O Transistors 1.E nm Ox/Poly 45 nm Hi-k/MG 32 nm Hi-k/MG 1E nm Ox/Poly 45 nm Hi-k/MG 32 nm Hi-k/MG 1.E pa/um 1E pa/um 1.E pa/um + 51% 1E pa/um + 56% 1.E V IDsat (ma/um) 22 nm Tri-gate Hi-k/MG 1.8 V 22 nm Tri-gate Hi-k/MG 1E IDsat (ma/um) Higher Performance Higher Performance > 50% performance improvement in HV I/O transistors with pitch scaling p. 14

15 Time to Fail [sec] 22 nm Tri-gate SoC Gate Dielectrics Reliability 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E VG/EOT [MV/cm] 32nm Planar 22nm Tri-gate 32nm Planar TG 22nm Tri-gate TG 22 nm Tri-gate SoC logic and HV I/O have robust gate dielectrics TDDB reliability p. 15

16 Interconnects p. 16

17 22nm SoC Interconnect Systems Performance and Density CPU SoC 4 x pitch 3 x pitch 2 x pitch 1.4 x pitch 1 x pitch 4 x pitch 3 x pitch 2 x pitch 1.4 x pitch 1 x pitch ( 2-6 layers) CPU 9 LM High Performance SoC 9 LM Standard SoC 11 LM SoC 11 LM High Density High Density SoC 11 LM High Density Focused on RC Performance Focused on Flexibility and Density p. 17

18 Key 22nm SoC Interconnect Features Top Metal ULK CDO dielectrics (lower layers), thick top metal, copper bump and lead-free solders p. 18

19 22nm SoC Interconnect Design Rules Summary Layer Pitch (nm) Process Dielectric Materials CPU SoC Fin Fin Fin Contact 90 SAC - Contact Contact M1 90 SAV ULK CDO M1 M1 MT - 1X 80 SAV ULK CDO M2/M3 2-6 layers MT 1.4x 112 SAV ULK CDO M4 Semi-global MT 2x 160 SAV ULK CDO M5 Semi-global MT 3x 240 SAV ULK CDO M6 Global Routing MT 4x Via First LK CDO M7/8 Global Routing MT - TOP 14 um Plate Up Polymer M9 Top Metal Multiple interconnect offering to optimize for differing product requirements p. 19

20 Analog/Passives/SRAM p. 20

21 GM * Rout 22 nm Tri-gate SoC Analog Characteristics Improved Analog Performance 5 0 GM*Rout@Vgs=peak GM, Vds=1.1 V, NMOS 65nm Planar 45nm Planar 32nm Planar 22nm Tri-gate Significant gains in G m *Rout characteristics of 22 nm Tri-gate transistors p. 21

22 22 nm Tri-gate SoC Advanced Passive Devices R C L Precision Resistor MIM Capacitor High Q Inductors - 15% + 15% Metal Insulator Metal Normalized Resistance Rich advanced passives precision resistors, MIM capacitors and high Q inductors p. 22

23 22 nm Tri-gate SoC SRAM Offerings 6T SRAM HDC ( um 2 ) 6T SRAM LVC ( um 2 ) 6T SRAM HPC ( um 2 ) Selected SRAM cell options including high density, low voltage and high performance p. 23

24 Bit Cell Leakage (pa/cell) Superior 22 nm Tri-gate SoC SRAM Bit Cell Leakage 1000 [3] nm 1 V 22 nm 1 Standby/retention 22 nm 0.75 V 22 nm 0.6 V Significant SRAM bit cell leakage reduction due to much improved short channel control p. 24

25 Supply Voltage (V) Superior 22 nm Tri-gate SoC SRAM Performance and Vmin MHz 1.8 GHz 65nm LP Planar 32 nm LP Planar [4] Pass 22 nm LP Tri-gate 2.6 GHz 22 nm SP Tri-gate 3.5 GHz 22 nm HP Tri-gate [6] 4.6 GHz mv Fail Operating Frequency (GHz) 40% frequency improvement or 150mV Vmin reduction over 32nm planar LP SRAM p. 25

26 Moore s Law in the Era of 3-D Tri-gate Transistor p. 26

27 A Look Back at History: Classical Era of Scaling 1/k = 0.7 Classical Scaling Ended with 90nm p. 27

28 Modern Era of Scaling Driven by Continual Innovations 90 nm 65 nm 45 nm 32 nm 22 nm Strained Siliconh High-k Metal Gate Tri-Gate 3D Tri-gate Transistor the latest in a series of innovations 28 p. 28

29 Idsat (ma/um) Scaling Now Require New Materials and Structures I 1 0 dsat = eff ( ) (Vg - inv eff 2 m k T e L W V t ) 2 (Eq. 1) Strained Si High -k Metal Gate Tri-Gate Oxide/Poly Gate Non-Strained Si 1V, 100nA/um Ioff NMOS PMOS 0.13 um Oxide/Poly Gate Strained Silicon 90 nm 65 nm Gate Pitch ( nm ) Hi-k/Metal Gate Strained Silicon 45 nm 32nm 100 Strained Si: m eff High k: k Metal Gate: T inv 3-D Tri-gate: V t C.-H. Jan, CSTIC 12 K. Mistry et al, IEDM Tech Dig., pp (2007) C.-H. Jan et al, IEDM Tech. Dig., pp (2008) S. Natarajan et al, IEDM Tech. Dig., pp (2008) C.-H. Jan et al, IEDM Tech. Digest, paper 28.1 (2009) p. 29

30 The Quest for Better Electrostatics and Short Channels GATE Increasing Electrostatics Planar With High K UTB SOI (or QW) Fins & Multigate ALL AROUND Wires/Dots Hisamoto IEDM 1989 And many others Dupre IEDM 2008 Tomioka IEDM 2011 p. 30

31 Effective Velocity [cm/s] Si d The Quest to Increase Mobility for Lower Voltage SEM Micrograph Energy Band Diagram Increasing Mobility Source Gate n-ge Drain Strain Ge III-V CNT InP Graphene QW InAlAs Barriers 3.0E E+07 InSb V DS = 0.5V V G -V T = 0.3V 2.0E E+07 InGaAs >5X V eff increase 1.0E E E DIBL [mv/v] Strained Si p. 31

32 Interconnect Increasing Importance for Scaling Line width (nm) Cu Resistivity from Grain and Sidewall scattering dominant at small dimension p. 32

33 Delay (ps) Rethinking Interconnect Transport Mechanisms Interconnect Length (gate pitch) Source: S. Rakheja et al. IITC 2010 Unlike diffusion & drift, delay for ballistic transport proportional to length p. 33

34 Heterogeneous System Integration 2-D Integration (SoC) 3-D Integration (SiP) Logic Memory Power Reg. Radio Sensors Photonics Source: IEDM 2011: The Evolution of Scaling from the Homogeneous Era to the Heterogeneous Era, M. Bohr Enable smart integration of a variety of functions and devices p. 34

35 Min. Feature Size (um) Wavelength (nm) Lithography Scaling Challenges nm 193 nm nm 22 nm 15 nm EUV Year of Production S. Sivakumar, Lithography for the 15 nm node,2010 IEDM Short Course (2010 Scaling feature size without wavelength scaling are technical and cost challenges p. 35

36 Co-Optimization Key to Extracting Value from Moore s Law Process Product Design for Manufacturing Co-Optimized Process+Product Rapid Yield Learning Early Product Ramp Design Tools Manufacturin g Masks Packaging p. 36

37 DATA GROWTH What Happens in ONE MINUTE? Exabytes (10 18 ) 8,000 6,000 4,000 2,000 Digital Information Created 7 EXABYTES OF DATA EVERY DAY = 17,000 HD MOVIES EVERY SECOND 60 Hours of Video Uploaded 6,000 Songs Downloaded 170K Photos Shared 230K Tweets Posted Forecast 204M s Sent Source: IDC, YouTube, Apple, Facebook, Twitter, Intel And approximately 4 trillion Other brands transistors and names may be claimed as shipped the property of others. per minute in 2012 p. 37

38 Summary Intel has developed an industry leading 22nm SoC technology based on 3-D Tri-Gate transistor and introduced products since D Tri-gate transistor serves as an excellent foundation for SoC platform technology in offering SoC features and their flexible integration for a wide range of products. 3-D Tri-Gate transistor technology is a key innovation in advancing Moore s law, the foundation of the semiconductor industry. p. 38