45nm Foundry CMOS with Mask-Lite Reduced Mask Costs

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Preston Waters
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This work is sponsored in part by the Air

1 This work is sponsored in part by the Air Force Research Laboratory (AFRL/RVSE) 45nm Foundry CMOS with Mask-Lite Reduced Mask Costs 21 March 2012 This work is sponsored in part by the National Aeronautics and Space Administration (NASA)

2012 American Semiconductor, Inc. All rights reserved.

Semiconductor Foundry Corporate Headquarters Boise, ID

Management Test & Characterization Cleanroom Sales,

Austin, TX (SVTC) Fab/Process Engineering Manufacturing

November, 2001 Product Lines Foundry Your Silicon Made.

FleX - Silicon on Polymer Design Services Turnkey Design

2 2012 American Semiconductor, Inc. All rights reserved. American Semiconductor Introduction CMOS and Custom Semiconductor Foundry Corporate Headquarters Boise, ID Engineering Design, Process, Modeling Operations/Fab Management Test & Characterization Cleanroom Sales, Marketing, Administration Manufacturing San Jose, CA; Austin, TX (SVTC) Fab/Process Engineering Manufacturing Specialty Process Modules Privately Held Founded November, 2001 Product Lines Foundry Your Silicon Made. Simple. FleX - Silicon on Polymer Design Services Turnkey Design Solutions ITAR Compliant; Trusted Certification in Progress 2 DoME 45nm CMOS This work is sponsored by the Air Force Research Laboratory)

3 2012 American Semiconductor, Inc. All rights reserved. 45nm Solution On-Shore. Affordable. 3 Mask-Lite 1-D/Grated Layout Reduced Mask Costs On-Shore Domestic Manufacturing of Electronics ITAR Compliant TRUSTED Feasible Economically Viable for Low Volume DoD Aerospace Commercial Supports Process Customization

AS045BK 45nm CMOS Production Process Enablement 2012 American Semiconductor,

4 Process Step Requirement Status 1 Epi Thickness Radiation tolerance

Isolation (STI) 3 Poly Sizing Uniformity and Pitch Integration complete 4

Etchback Integration complete Integration complete 6 Local Interconnect Pattern

4 AS045BK 45nm CMOS Production Process Enablement 2012 American Semiconductor, Inc. All rights reserved. 4 Process Step Requirement Status 1 Epi Thickness Radiation tolerance Integration complete 2 Shallow Trench Uniformity and Pitch Integration complete Isolation (STI) 3 Poly Sizing Uniformity and Pitch Integration complete 4 Spacer Thickness and Uniformity 5 High Voltage Gate Oxide Thickness and Etchback Integration complete Integration complete 6 Local Interconnect Pattern & Continuity Integration complete 7 HKMG Gate Stack Cox & Leakage In progress 8 Strain PMOS Performance In progress 9 Copper Via/Interconnect Size In progress

5 45nm Low Volume Cost Drivers 2012 American Semiconductor, Inc. All rights reserved. 5 A 65-nm mask set can cost 1.8 times that of a 90-nm set, while a 45-nm mask set can cost 2.2 times that of a 65-nm set. - EE Times 10/7/2010 Masks OPC Write Time Inspection Repair 45nm CMOS Project Costs (First Lot / Low Volume) Design EDA Tools Costs Addressed by DoME Fabrication

6 Optical Proximity Correction 2012 American Semiconductor, Inc. All rights reserved. 6 Drawn (top) versus printed (bottom) shapes without OPC (left) and with OPC (right). The desired shape is in blue. The shape after OPC is applied is in green. The shape in red is how the feature prints on the wafer. Mack, Chris A., Field Guide to Optical Lithography, SPIE Press Book, 24 Jan 2006 Optical Proximity Correction. Wikipedia. Retrieved April 28, 2011, from

45nm Low Volume Cost Drivers 2012 American Semiconductor, Inc. All rights reserved. 7 A 65-nm mask set can cost 1.8 times that of a 90-nm set, while a 45-nm mask set can cost 2.

7 45nm Low Volume Cost Drivers 2012 American Semiconductor, Inc. All rights reserved. 7 A 65-nm mask set can cost 1.8 times that of a 90-nm set, while a 45-nm mask set can cost 2.2 times that of a 65-nm set. - EE Times 10/7/2010 Masks OPC Write Time Inspection Repair 45nm CMOS Project Costs (First Lot / Low Volume) Design EDA Tools Costs Addressed by DoME Fabrication

technology that reduces mask costs up to 90%, making leading

8 2012 American Semiconductor, Inc. All rights reserved. Mask-Lite Low Cost 45nm Solution 8 Advanced 45nm CMOS Mask-Lite technology that reduces mask costs up to 90%, making leading edge foundry technology economical for low volume requirements and applications. Concept 1-D straight line geometries Non immersion + lower cost reticles AS045BK 45nm Poly AS045BK 45nm Poly Lines & Cuts

2012 American Semiconductor, Inc. All rights reserved. Mask-Lite Low Cost 45nm Solution 9 1D geometry Fixed pitch, straight line vs Traditional 2-D with corners Enhances Equipment Capability 193nm/.

9 2012 American Semiconductor, Inc. All rights reserved. Mask-Lite Low Cost 45nm Solution 9 1D geometry Fixed pitch, straight line vs Traditional 2-D with corners Enhances Equipment Capability 193nm/.85NA 65nm stepper feasible for 45nm and beyond Reduced Mask costs Reduces or eliminates OPC requirements Reduces mask write time, inspection, and repair Dry lithography rather than immersion technology No double patterning required Potential mask reuse from product to product or metal layers (example M1 and M3 masks can be same with different cut masks) E-beam lithography feasibility (Mask elimination) Smaller Die Tighter rules allow closer geometries at a feature node or Same rules with better control for better yield, better timing, better power

10 2012 American Semiconductor, Inc. All rights reserved. Comparative 45nm Process Technologies 10 Fast follower strategy leverages industry development of 45nm tools, technology, and know-how to minimize R&D and production costs DoME IBM Intel Process ASI AS045BK IBM Trusted Cu-45HP Intel 45nm CMOS Availability Pure-play Foundry IDM/Foundry IDM Mask Cost (tooling) Low (Mask-Lite ) Very High Low Material Bulk SOI Bulk Gate (feature/pitch) 45nm/180nm 45nm/190nm 35nm/160nm M1 (feature/pitch) 70nm/140nm TBD 80nm/160nm Local Interconnect Yes No Yes Ion N/PMOS ua/um 800/ / /1070 Gate/GOX EOT HKMG Poly/SiON High-k/Met. (HKMG) Strain Yes Yes Yes Lithography 193nm/.85NA 193nm/1.35NA 193nm/.93NA 1D Grated Yes In R&D only Yes BEOL Cu, low-k, 9 layer Cu, low-k, 11 layer Cu, low-k, 9 layer

11 2012 American Semiconductor, Inc. All rights reserved. 45nm CMOS Platform-Based Structured ASIC 11 Platform-Based Structured ASIC for space applications utilizes: 1. Performance, logic density, and power of 45nm CMOS 2. Low cost user customization through Mask-Lite for low volume applications 3. Rad-hard design techniques Rad-hard Via ROM with EDAC Rad-hard SRAM with EDAC Microcontroller CPU and Peripherals Analog User Configurable Structured ASIC

12 2012 American Semiconductor, Inc. All rights reserved. Platform-Based Structured ASIC Advantages and Applications 12 Advantages Performance and density similar to a custom ASIC Lower design and manufacturing costs than a custom ASIC Cost effective for low to mid volume quick-turn designs User configuration via standard EDA tools Fixed microcontroller is implemented with optimized standard cells rather than the structured ASIC logic cells. This provides superior performance and lower power consumption than a typical FPGA-based design. Applications Sensor data handling Actuator control Data collection, compression, encryption, and transmission ASIC prototypes

13 Your Project in 45nm 2012 American Semiconductor, Inc. All rights reserved. 13 DoME is ready for early collaboration Your own mask set and dedicated run for less than the cost of traditional 45nm MPWs Multi Layer Reticles supported to further reduce mask costs DoME is available for process customization Add custom process modules Target unique performance goals Supported with custom PDKs Process integration and design support

14 Thank You 2012 American Semiconductor, Inc. All rights reserved. American Semiconductor Inc., the American Semiconductor logo, Flexfet, FleX, and the Flexfet logo are trademarks of American Semiconductor, Inc. All other trademarks are the property of their respective owners. American Semiconductor, Inc South Vista Avenue, Suite 230 Boise, ID Tel: Fax:

45nm Foundry CMOS with Mask-Lite Reduced Mask Costs

This work is sponsored by the Air Force Research Laboratory (AFRL/RVSE) TPOC: Mr. Kenneth Hebert 45nm Foundry CMOS with Mask-Lite Reduced Mask Costs 25 October 2011 www.americansemi.com 2011 American Semiconductor,