Microelectronics, BSc course

Transcription

1 Microelectronics, BSc course MOS circuits: CMOS circuits, construction

2 The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G D n+ DEVICE CMOS circuits András Poppe, BME-EET

3 The CMOS inverter recall V DD V DD V DD p IN OUT IN=1 OUT=0 IN=0 OUT=1 n GND GND GND In steady-state only on transistor is "on", the other one is always "off" CMOS circuits András Poppe, BME-EET

4 X-sectional view of a CMOS inverter n+ n+ p+ p+ n well p-si substrate CMOS circuits András Poppe, BME-EET

5 Characteristic of the CMOS inverter 2 basic cases, depending on the supply voltage and threshold voltages of the transistors pmos is "on" nmos is "on" pmos is "on" nmos is "on" V Tp VTn U IN V Tn V Tp U IN 0 V DD 0 1. small supply voltage: V DD < V Tn + V Tp only one transistor is "on" at a time V DD 2. larger supply voltage V DD > V Tn + V Tp when switching over, both transistors are "on" at the same time CMOS circuits András Poppe, BME-EET

6 Characteristic of the CMOS inverter 1. small supply voltage: V DD < V Tn + V Tp the characteristics: U = OUT V DD indefinit if... V 0 if... U Tn IN < U < - IN V DD VTp < Tn if... U IN V < V - DD VTp VDD UOUT Indefinit VDD UOUT The middle part of the transfer characteristic is very steep, this the specific advantage of CMOS inverters. U IN U IN VDD -VTp VTn VDD VTn VDD VDD -VTp CMOS circuits András Poppe, BME-EET

7 Characteristic of the CMOS inverter 2. large supply voltage: V DD > V Tn + V Tp Switching over? - "mutual conduction" Constructing the characteristic: CMOS circuits András Poppe, BME-EET

8 The CMOS inverter Design for symmetrical operation: If U IN =U inv logic threshold voltage, both transistors have equal current: K = 2 n( Uinv VTn) K p( U DD U inv VTp ) 2 U GSn =U K U inv U = DD V Tp 1+ + V K n Tn / K K p n / K p K X W = L X μ XC 2 ox U GSp =V DD -U K The inverter logic threshold voltage depends on the ratio of the current constants of the transistors. To have U inv at V DD /2 and V Tn = V Tp, then K n =K p has to be set. W L P = W..2.5 L 2 since hole mobility is times less n The logic threshold voltage can be set by the W/L ratios CMOS circuits András Poppe, BME-EET

9 The CMOS inverter / dynamic char. Calculation of the switching times What do they depend on? the current driving capability of the output the capacitive load on the output out If the characteristics of the two transistors are exactly complementary (K n =K p and V Tn = V Tp ), rising and falling times will be equal CMOS circuits András Poppe, BME-EET out

10 The capacitnces Intrinsic capacitances of the driving stage Input capacitance of the loading stage (next gate) extrinsic or fanout capacitances wiring (interconnect) capacitance C G4 M 2 C DB2 M 4 Vin V out1 V out2 C GD12 C w M 1 C DB1 C G3 M 3 intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance CMOS circuits András Poppe, BME-EET

11 The capacitnces The intrinsic capacitances: S-G G-D overlap capacitances the MOS capacitance of the channel capacitances of pn junctions The wiring capacitance depends on the interconnect geometry (width, length) with the advance of manufacturing processes this capacitance tends to increase See later CMOS circuits András Poppe, BME-EET

12 The CMOS inverter / dynamic char. Calculation of switching times identical times, integration for the extreme values of the voltage of If the load capacitance: I D K t ( VDD VT l = 2 ) V V LM DD C I L D du out V LM minimal voltage of the load capacitance out then t l = CL( V K( V DD DD V V LM 2 T ) ) Can be reduced by increasing the supply voltage or the W/L ratio CMOS circuits András Poppe, BME-EET

13 Power consumption of CMOS inv.: There is no static consumption since there is no static current There is dynamic consumption during switching which consists of 2 parts: Mutual conduction: During the rise of the input voltage both transistors are "on" V Tn <U IN <V DD -V Tp Charge pumping: At switching over the output to 1 the C L loading capacitor is charged to the supply voltage through the p transistor, then it is discharged towards the ground through the n transistor. Charge is pumped from VDD to GND CMOS circuits András Poppe, BME-EET

14 Power consumption of CMOS inv.: Mutual conduction ("short power"): During a certain period of the rise of the input signal both transistors are "on" if V Tn <U IN <V DD -V Tp this is called mutual I MAX = conduction K ( V 2 V ) 2 DD / T I [10uA], U [V] I Vin Vout n 10.0n 20.0n 30.0n 40.0n time [sec] charge flowing through: ΔQ = bt I UD MAX, where t UD is the time while current is flowing, b is a constant depending on the signal shape. b P 2 = fδqvdd = fvddbtudk( VDD / 2 VT ) P ~ f V 3 DD CMOS circuits András Poppe, BME-EET

15 Power consumption of CMOS inv.: Charge pumping: At switching the C L load capacitance is charged to VDD through the p-channel device when the output changes to 1, later, when switching the output to 0, it is discharged towards GND through the n-channel device. ΔQ = C V P cp =f C L V 2 DD L The power consumption due to charge pumping is proportional to the frequency and the square of the supply voltage. Total consumption: sum of the two components (if there is mutual conduction), directly proportional to the frequency and the 2 nd and 3 rd power of the supply voltage CMOS circuits András Poppe, BME-EET L DD

16 Components of the consumption of CMOS circuits Dynamic components at every switching event mutual conduction, charge pumping proportional to the the event density clock frequency circuit activity Further components due to parasitics: subthreshold currents leakage currents of pn junctions nowadays already significant leakage (tunneling) through the a gate dielectric CMOS circuits András Poppe, BME-EET

17 Construction Constructing CMOS gates Technology (overview of the poly-si gate process) Layout CMOS circuits András Poppe, BME-EET

18 CMOS gates Create an nmos switching curcuit (pull down network): series path: NAND function paralel path: NOR function combination of these: complex gate switches: nmos transistors Load: the dual circuit of the nmos network: pmos network CMOS circuits András Poppe, BME-EET

19 CMOS gates In a CMOS inverter both transistors are actively controlled In case of gates there will be a PUN (pull up network: pmos circuit) and a PDN (pull down network: nmos circuit). The number of transistors both in PUN and PDN is equal to the number of inputs of the gate For input combinations where the output is 0, the PDN realizes a short towards GND and the PUN is an open circuit; if the output function is equal to 1, the PDN will be an open circuit and the PUN realizes a short towards VDD. Circuits with dual topology should be realized from n and p channel transistors Gates of transistors receiving the same signal are connected CMOS circuits András Poppe, BME-EET

20 CMOS gates NOR gate NAND gate out out For an n input CMOS gate 2n transistors are needed (passive load gates need only n+1 transistors) CMOS circuits András Poppe, BME-EET

21 Construction complex CMOS gates dual topology (loop cut, cut loop) dual components: nmos replaced by pmos transistor gates corresponding to the same signal must be connected proper sizing of the W/L ratios (e/h mobility mismatch) U DD F = A + BC A U out B C CMOS circuits András Poppe, BME-EET

22 The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G D n+ DEVICE CMOS circuits András Poppe, BME-EET

23 Metal gate MOS transistor In-depth structure: Layout view: Source doping Gate Drain doping Thin oxide Source Problems: metal gate large V T requires accurate mask alignment Drain contact CMOS circuits András Poppe, BME-EET

24 Poly-Si gate MOS transistor In-depth structure: Layout view: Source doping Gate Drain doping thin oxide Source Advantages smaller V T self alignment Drain contact CMOS circuits András Poppe, BME-EET

25 A poli-si gate-es nmos technológia Start with: p type substrate (Si wafer) cleaing, grow thick SiO 2 this is called field oxide CMOS circuits András Poppe, BME-EET

26 The poli-si gate nmos process Create the active zone with photolithography coat with resist, expose to UV light through a mask, development, removal of exposed resists etching of SiO 2 removal of the resist M1: active zone CMOS circuits András Poppe, BME-EET

27 The poli-si gate nmos process Create the gate structure: growth of thin oxide deposit poly-si pattern poly-si with photolithography etch poly-si, etch thin oxide (resist, exposure, develop) M2: poly-si pattern CMOS circuits András Poppe, BME-EET

28 The poli-si gate nmos process S/D doping (implantation) the exide (thin, thick) masks the dopants this way the self-alignment of the gate is assured Passivation: deposit PSG CMOS circuits András Poppe, BME-EET

29 The poli-si gate nmos process Open contact windows through PSG photolithography (resist, expose pattern, etching (copy the pattern) cleaning develop) M3: contact window pattern CMOS circuits András Poppe, BME-EET

30 The poli-si gate nmos process Metallization Deposit Al photolithography, etching, cleaning M4: metallization pattern The recepy of the process is given, the in-depth structure is determined by the sequence of the masks One needs to specify the shapes on the masks The set of shapes on subsequent masks is called layout CMOS circuits András Poppe, BME-EET

31 Layout of a depletion mode inverter S G D S G D Layout == set of 2D shapes on subsequent masks Masks are color coded: active zone: poly-si: red green contact windows: black metal: blue Mask == layout layer Where is a transistor? Channel between two doped regions: CHANNEL = ACTIVE AND POLY CMOS circuits András Poppe, BME-EET

32 Simplified layout: stick diagram Vdd active poly metal contact In Out In 2/2 Out 2/2 GND W/L ratios are given CMOS circuits András Poppe, BME-EET

33 Si-compilers Logic schematic / netlist / high level description Transistor level schematic with W/L information Stick diagram layout Actual layout Automatic conversion between these representations HARDWARE SYNTHESIS 1. From behavioural description structural description 2. Implementation of the structural description with a given realization mode / manufacturing process: technology mapping We have seen basics of the realization of an application specific integrated circuit (ASIC) Designs can also be mapped to an FPGA CMOS circuits András Poppe, BME-EET

34 Layout primitives: simple shapes Active zone (window opening through the oxide) Gate (mask of poly-si pattern) Contacts (window opening mask through oxide/psg) S/D lines (mask of metallization pattern) CMOS circuits András Poppe, BME-EET

35 Layout macros from primitives layout of an nmos transistor: layout primitives on actual layers corresponding to real masks nmos transistor layout + outline + pins G D nmos G S nmos transistor macro: outline, pins, scripts: pszeudo layers CMOS circuits András Poppe, BME-EET

36 Layout macros from macros and primitives G G D nmos S D pmos S G G Gate level layout CMOS circuits András Poppe, BME-EET

37 CMOS structure (inverter) n+ n+ p+ p+ n well p-si substrate CMOS circuits András Poppe, BME-EET

38 CMOS structures Further masks: n-well (or p-well, depending on the substrate) p doping (or n doping, depending on the substrate) Multiple metal layer CMOS: each metallization needs own mask, conatct windows, vias There could be multiple poly-si layers (analog CMOS) Typically: masks Certain rules need to be kept for manufacturability: design rules come from the process, given by Si-foundry CMOS circuits András Poppe, BME-EET

39 Layout of a CMOS inverter U DD n well p + n - n + S D p-mos n + U out p well p - p + S D n-mos GND U in poli CMOS circuits András Poppe, BME-EET

40 Details of a CMOS circuit 2 metal layers only INV NAND3 Layout extraction: checking, real delays CMOS circuits András Poppe, BME-EET

41 Modern metallization CMOS circuits András Poppe, BME-EET

42 Intel 0.25 µm process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric CMOS circuits András Poppe, BME-EET

43 Interconnect capacitances Interconnect - substrate: parallel plate capacitance Current flow dir. L Electrical field W H t di dielectric (SiO 2 ) substrate Dielectric constant (SiO 2 => 3.9) C pp = (ε di /t di ) WL CMOS circuits András Poppe, BME-EET

44 Interconnect capacitances C wire = C pp + C fringe + C interwire = (ε di /t di )WL + (2πε di )/log(t di /H) + (ε di /t di )HL fringe interwire paralell plate H CMOS circuits András Poppe, BME-EET

45 Other issues of interconnects Series resistance Distributed parameter RC line (see transmission lines) Sort of a representation of the diffusion equation CMOS circuits András Poppe, BME-EET