A New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight-Pitch Process

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1 A New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight-Pitch Process Jianqiang Lin, Xin Zhao, Tao Yu, Dimitri A. Antoniadis, and Jesús A. del Alamo Microsystems Technology Laboratories, MIT December 10, 2013 Sponsors: FCRP-MSD Center, Intel, E3S STC, MIT SMA and SMART 1

2 Motivation Superior electron transport properties in InAs channel [J. del Alamo, Nature 2011] InAs HEMTs Strained Si V DS =0.5 V Si V DS = V 2 2

3 InGaAs MOSFET evolution Performance (Kim, IEDM 2012) [del Alamo, ESSDERC 2013] Fabrication and Scaling 3

4 InGaAs MOSFET evolution Performance (This work) (Kim, IEDM 2012) [del Alamo, ESSDERC 2013] Fabrication and Scaling 4

5 New InGaAs MOSFET with self-aligned LEDGE Bottleneck to ON current is R sd Introduction of highly conductive LEDGE n + region linking metal contact and channel 5

6 Process integration Key features: Wet-etch free / Lift-off free / Au free Ohmic/Oxide deposition* Gate opening 3-step gate recess ALD deposition Gate metal Pad formation 6

7 Composite W/Mo contact Without W: Long undercut of Mo due to oxidation Limits S/D metal spacing With W: No Mo oxidation Air void s [Lin, IEDM 2012] This work 7

8 3-step gate recess process CF 4 +O 2 RIE * Cl-based RIE Digital etch*: O 2 plasma + H 2 SO 4 *[Waldron, IEDM 2007] *[Lin, EDL submitted] Process enables precise control of: t ch / L ledge L g / t ledge L ledge t ledge t ch 8

9 Semiconductor surface after recess Only wet cleaning (no etching) Additional cap dry etch (~ 20 nm) + 4 cycle digital etch 5 nm RMS = 0.12 nm RMS = 0.21 nm Scanning area: 2x2 m 2 9

10 Structure design: Ledge Short Ledge Long Ledge 10

11 Structure design: Ledge Short Ledge Long Ledge Surface channel: In 0.7 Ga 0.3 As / InAs / In 0.7 Ga 0.3 As = 1/2/5 nm High-k: HfO 2, thickness =2.5 nm (EOT~0.5 nm) 11

12 I d (ma/ m) Output and g m characteristics for Lg = 70 nm -V t = 0 to 0.5 V in 0.1 V step L ledge = 5 nm L ledge = 70 nm g m (ms/ m) 3.0 L ledge =5 nm, 2.7 ms/ m L ledge =70 nm, 1.9 ms/ m = 0.5 V R on = 220 m for L ledge = 5 nm Record g m,max = 2.7 ms/ m at = 0.5 V for L ledge = 5 nm 12

13 Subthreshold characteristics 10-3 =0.5 V L ledge =70 nm S min =94 mv/dec 10-3 L ledge =5 nm =0.5 V S min =138 mv/dec I d (A/ m) =0.05 V S min =90 mv/dec I d (A/ m) =0.05 V S min =108 mv/dec 10-9 DIBL=130 mv/v DIBL=249 mv/v I g < 10 pa/µm over entire voltage range Further EOT scaling possible 13

14 Subthreshold characteristics L ledge =70 nm L ledge =5 nm I d (A/ m) 10-3 =0.5 V S min =94 mv/dec =0.05 V S min =90 mv/dec I d (A/ m) =0.5 V S min =138 mv/dec =0.05 V S min =108 mv/dec Flattening tail at high 10-9 DIBL=130 mv/v DIBL=249 mv/v I g < 10 pa/µm over entire voltage range Further EOT scaling possible 14

15 L g = 20 nm InAs QW-MOSFET with L ledge = 5 nm I d (ma/ m) 1.0 L g =20 nm -V t = 0.5 V 0.8 R on =224 m 0.4 V Smallest functional III-V MOSFET with tight contact spacing 15

16 Parasitic resistance analysis R on ( m) L ledge =70 nm, R sd =302 m Pad W/Mo L ledge =5 nm, n+ Cap R sd =206 m Channel L g (nm) Buffer R probe = 5 m R metal = 5 m R cont = 50 m R ledge ~ 1 m/nm R bar = 40 m Gate For short ledge devices, major R sd contribution from R cont and R bar 16

17 Benchmark: I on I on ( A/ m) I off =100 na/ m, V dd =0.5 V L g (nm) * InGaAs FETs Planar Trigate MIT HEMT MIT MOSFET 2012 This work(l ledge =70 nm) This work(l ledge =5 nm) * [Kim and del Alamo, T-ED 2008] Record I on = 410 A/ m at L g =70 nm for L ledge =70 nm 17

18 Benchmark: g m,max vs. S g m-max (ms/ m) 3.0 InGaAs FETs = 0.5 V 0.5 L g 70 nm S min (mv/dec) Planar Trigate MIT HEMT Teledyne/MIT HEMT MIT MOSFET 2012 This work(l ledge =70nm) This work(l ledge =5 nm) Short ledge MOSFETs show record g m,max Long ledge MOSFETs match record S [Radosavljevic, IEDM 2011] 18

19 Impact of ledge on off-state leakage (Long MOSFETs) L g = 200 nm, L ledge = 70 nm L g = 500 nm, L ledge = 5 nm I d or I g (A/ m) 10-4 I d =0.1 to 0.6 V I g I d =0.1 to 0.6 V I g Flattening tail at high Vds Short ledge leads to high I off Strong dependence 19

20 Off-state leakage: Temperature dependence L g = 500 nm, L ledge = 5 nm I d or I g (A/ m) 10-4 I d K =0.1 to 0.6 V I g 10-4 I d K I g 10-4 I d I g K GIDL (gate-induced drain leakage) signature 20

21 Off-state leakage follows BTBT signature ~ exp I s ( A/ m) = 0.6 V = 0.5 V = 0.4 V T=77 K V -1 dg (V -1 ) I s (A/ m) K =0.6 V = -0.4 V 150K E g 3/2 ( ev 3/2 ) 77K I s follows BTBT dependence on V dg and E g 21

22 GIDL simulations TCAD simulation of BTBT rate based on nonlocal path BTBT model: n+ contact Gate Oxide InP InGaAs InAs S G D 2 nm InGaAs InAlAs E c BTBT E v 22

23 Conclusions Novel self-aligned III-V QW-MOSFETs: Lift-off free, wet-etch free, and Au free in front end process Design and fabrication of critical S/D ledge Tight metal contact spacing Scaled channel thickness, barrier thickness and gate length Record results demonstrated: g m,max = 2.7 ms/ m in L ledge = 5 nm I on = 410 A/ m in L ledge = 70 nm Characteristic GIDL signature observed 23

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