IFSIN. WEB PAGE Fall ://weble.upc.es/ifsin/

Transcription

1 IFSIN IMPLEMENTACIÓ FÍSICA DE SISTEMES INTEGRATS NANOMÈTRICS IMPLEMENTACIÓN N FÍSICA F DE SISTEMAS INTEGRADOS NANOMÉTRICOS PHYSICAL IMPLEMENTATION OF NANOMETER INTEGRATED SYSTEMS Fall 2008 Prof. Xavier Aragones Prof. Antonio Rubio Prof. Francesc Moll Prof. Josep Rius (aragones@eel.upc.edu) (antonio.rubio@upc.edu) (moll@eel.upc.edu) (rius@eel.upc.edu) 1 Introduction Introduction - 1 WEB PAGE ://weble.upc.es/ifsin/ 2 Introduction Introduction - 2

2 COURSE CONTENTS Objective: to provide the student the necessary knowledge to achieve a successful implementation of his design. Contents: Techniques and implementation alternatives of integrated systems Classical and advanced packages Interconnections, effects and models. Power-supply and clock distribution Parasitic couplings: electrical and thermal. Electromagnetic shielding. Heat dissipation. Signal integrity. Internal noise coupling: switching, substrate, crosstalk. Techniques to reduce coupling and noise. Process variations, categories, models, mismatching and layout implementation techniques. Input/output circuits. Pads, protections. Specific design methodologies for nanometer-scale systems. 3 Introduction Introduction - 3 COURSE SCHEDULE INTRODUCTION: XAVIER ARAGONES, 22 and 23 September. Implementation techniques and options for integrated systems BLOCK 1: XAVIER ARAGONES, 29 and 30 September, 6 and 7 October. Substrate as a progagation means. Substrate coupling Modeling of interconnects BLOCK 2: JOSEP RIUS, 13, 14, 20, 21 and 27 October. Crosstalk between interconnects. Power-supply networks. SSN BLOCK 3: FRANCESC MOLL, 28 October, 3, 4, 10 and 11 November. Process variations Impact on digital and analog circuits BLOCK 4: XAVIER ARAGONES, 17, 18, 24 and 25 November Layout techniques. Design rules BLOCK 5: ANTONIO RUBIO, 1, 2, 9, 15 and 16 December Clock distribution Thermal coupling Tolerant design methodologies 4 Introduction Introduction - 4

3 COURSE EVALUATION 75% CONTINOUS ASSESSMENT: Guided works, presentations, exercises... Attendance A mark is obtained from each block 25% FINAL EXAMINATION: Short questions / exercises 7th January 5 Introduction Introduction - 5 INTRODUCTION Reminder: IC manufacturing - photolithography How are ICs today? Smaller, but less certain System-on-a-Chip (SoC) Signal Integrity Needs for First silicon success in nanometer technologies 6 Introduction Introduction - 6

4 IC MANUFACTURING Integrated Circuits (ICs or chips): manufactured on Silicon wafers wafer thickness: ~0.5 mm. wafer diameter: mm Introduction Introduction - 7 IC MANUFACTURING Integrated Circuits (ICs or chips): manufactured on Silicon wafers wafer Silicon P N chip doping on the order of impurities/cm (little conductive) 8 Introduction Introduction - 8

5 IC MANUFACTURING: the wafer Silicon wafers manufacturing of ingots of crystalline Silicon a purity up to % is required slicing of the wafers 9 Introduction Introduction - 9 IC MANUFACTURING: the masks Each step of the manufacturing process that implies the definition of a geometry needs a mask draw the mask with an electron beam (scale 1:4) replicate the mask of the IC to cover the wafer surface 10 Introduction Introduction - 10

6 IC MANUFACTURING: the lithography How do you transfer the drawing in the mask to the chip surface? Example: definition of the gate of a MOS transistor (complete example at 11 Introduction Introduction - 11 IC MANUFACTURING: the lithography How do you transfer the drawing in the mask to the chip surface? Example: definition of the gate of a MOS transistor (complete example at 12 Introduction Introduction - 12

7 IC MANUFACTURING: the lithography How do you transfer the drawing in the mask to the chip surface? Example: definition of the gate of a MOS transistor (complete example at 13 Introduction Introduction - 13 IC MANUFACTURING: the lithography Manufacturing process: successive implants of P or N- type impurities, oxide growths, material depositions (polysilicon, aluminium, etc.), forming the circuit as a stack of layers. photolithography White room 14 Introduction Introduction - 14

8 ICs ACCORDING TO TEXTBOOKS 26 Introduction Introduction - 26 HOW ARE ICs TODAY? to the past to the future 0.18 um Logic Technology 65 nm Copper Logic 90 nm Copper Logic 0.13 um Copper Logic 0.13 um Copper Mixed- Mode/RFCMOS 0.18 um Mixed-Mode/RFCMOS 0.18 um CMOS Image Sensor Core 1.0V, 1.2V 1.0V, 1.2V 1.2V 1.2V 1.8V 1.8V 1.8V Voltage Options 1.8V, 2.5V, 3.3V 2.5V, 3.3V, 3.3VHG 3.3V 3.3V 3.3V 3.3V 0.18 um High Voltage 1.8V 5.5V 24V, 32V 0.25 um 0.35 um 0.5 um 0.6 um 0.8 um ( ) I/O 1.8V, 2.5V, 3.3V High Voltage Max. Metal Layers 10Cu 9Cu 8Cu 8Cu Different technology nodes Different technology flavours Introduction Introduction - 27

9 HOW ARE ICs TODAY? 90 nm node nm node 50 nm length (IEDM 2002) nm prototype (IEDM 2000) 45 nm node nm node nm node nm from Massimo Conti, BCN nm prototype (VLSI 2001) 15nm 15 nm prototype (IEDM 2001) 10 nm prototype (DRC 2003) to the past to the future 28 Introduction Introduction - 28 HOW ARE ICs TODAY? 29 Introduction Introduction - 29

10 HOW ARE ICs TODAY? Characteristics of a typical 65 nm process : 65 nm printed gate length, 35 nm physical gate length Multiple V T voltages for Vdd = 1 V, Vdd = 1,2 V. 1.2 nm gate oxide Ultra-shallow drain-source. Si 3 N 4 spacer necessary to build drain-source extensions. Nickel Silicide (NiSi) for low resistance at gate, and source and drain extensions. Strained silicon at channel Check how complex is to build your own 65 nm transistor!! : 30 Introduction Introduction - 30 HOW ARE ICs TODAY? Ge atoms are injected to the channel, thus the atomic lattice is strained and mobility increases (20% approx.) 31 Introduction Introduction - 31

11 HOW ARE ICs TODAY? Characteristics of a typical 45 nm process : No more polysilicon gate: Metal gate No more SiO 2 gate oxide: Hafnium-based high-k insulator 32 Introduction Introduction - 32 HOW ARE ICs TODAY? Characteristics of a typical 65 nm process : 8 10 metal layers Cu interconnects Low-k dielectrics (carbon doped oxide) M1 distance M1 width 100 nm M5 distance M5 width 150 nm Approx. 600 m/cm 2 (excluding global levels) M1 length at which RC delay = gate delay: 80 µm 33 Introduction Introduction - 33

12 HOW ARE ICs TODAY? Characteristics of a typical 45 nm process : Extra low-resistance top layer (M9) for lowresistance power-supply distribution between package and lower metals C4 package bump Via 9 } Metal 9 Metal Introduction Introduction - 34 HOW ARE ICs TODAY? Devices for Mixed-Mode / RF : 35 Introduction Introduction - 35

13 HOW ARE ICs TODAY? Devices for Mixed-Mode / RF : Special layers for inductors Special layers for capacitors Special layers for resistors Triple well p-well n-well Special layers for NPN 36 Introduction Introduction - 36 SMALLER, BUT LESS CERTAIN ABOVE WAVELENGTH 3µm Silicon feature size 0.6µm 436nm 365nm Lithography Wavelength 0.25µm SUB WAVELENGTH 193nm 0.13µm Lithography (manufacturing) resolution does not increase as fast as demanded by technology evolution! 0.05µm from Massimo Conti, BCN Introduction Introduction - 37

14 SMALLER, BUT LESS CERTAIN 90 nm process : target results (due to lithography diffraction effects) from Massimo Conti, BCN Introduction Introduction - 38 SMALLER, BUT LESS CERTAIN Sub Wavelength Lithography cause strong variations on metal lines width, MOSFET width and length target results (due to lithography diffraction effects) from Massimo Conti, BCN Introduction Introduction - 39

15 SMALLER, BUT LESS CERTAIN Oxide variations over a 20 Å nominal oxide thickness : from Massimo Conti, BCN 2006 from Chandu Visweswarian, Introduction Introduction - 40 SMALLER, BUT LESS CERTAIN Dopant concentration variability has strong influence for small area devices Mean Number of Dopant Atoms Technology (nm) from Massimo Conti, BCN Introduction Introduction - 41

16 SMALLER, BUT LESS CERTAIN W=L= 0.5 µm d= 5µm W=L= 10 µm d= 5µm Performance variability : Example: normalized drain current dispersions of 2 MOSFETs for different geometries and distances W=L= 0.5 µm d= 100µm W=L= 10µm d= 100µm from Massimo Conti, BCN Introduction Introduction - 42 Probability Density SMALLER, BUT LESS CERTAIN Effect of process variability on performance: Technology 0,25 µm Acceptable Region Not Acceptable Region 0,18 µm 0,13 µm Performance from Massimo Conti, BCN Introduction Introduction - 43

17 SMALLER, BUT LESS CERTAIN From: R. Madge, ITC 2004 Defect Density 130nm 90nm 65nm 45nm 180nm Time Defect density decreases in a mature technology But increases as feature size reduces!! from Massimo Conti, BCN Introduction Introduction - 44 SMALLER, BUT LESS CERTAIN from Massimo Conti, BCN Introduction Introduction - 45

18 SMALLER, BUT LESS CERTAIN IBM Power4 Dual-core 0,13 µm copper, SOI technology 1,3 GHz Temperature varies in space and time (switching activity) Temperature effect on clock skew, circuit delay, etc. from Massimo Conti, BCN 2006 from: C. Visweswariah, IBM 46 Introduction Introduction - 46 SMALLER, BUT LESS CERTAIN Isolated interconnects??? Welcome to reality!: crosstalk, crosstalk, delay, delay, Introduction Introduction - 47

19 Design rules provided to minimize them Catastrophic DEFECT TYPES Parametric Objective of this course: how to cope with them Static Spot Defects Design Logic Bugs Technological Process Variations - intradie - interdie Dynamic α Particle Single Event Upsets Environmental (Vdd, Temperature, Coupling Noise, Signal Integrity, Electromigration) 48 Introduction Introduction - 48 SYSTEMS ON A CHIP (SoC( SoC) H. Darabi et al., Single Chip b in 0,18 um CMOS, including PA, PLL filter, baseband and MAC, IEEE JSSC, December 2005 Frank Op t Eynde, et al., Fully-Integrated Single-Chip SoC for Bluetooth in 0,25 µm CMOS, IEEE ISSC Introduction Introduction - 49

20 SYSTEMS ON A CHIP (SoC( SoC) 1.8 mm fo=1,57 GHz Sensitivity -130 dbm (19 db below thermal noise) 50 Introduction Introduction - 50 SIGNAL INTEGRITY System-on-a-Chip paradigm multiplies the problems of signal integrity (signal interactions) A clear example is digital switching noise coupled through the substrate to sensitive RF signals Bluetooth radio + baseband in a single chip 0,18 µm CMOS technology Paul van Zeijl, et al., A Bluetooth Radio in 0,18 µm CMOS, IEEE JSSC December Introduction Introduction - 51

21 SIGNAL INTEGRITY Digital power-supply lines are contaminated with inductive noise. This is the main agent of substrate noise Large circuits being switched on and off (for power saving) provoke current peaks and voltage droop Wire resistance provokes IR drop and significant voltage differences across the chip V dd di L dt di GND + L dt A. Khan, Cadence Design Systems Inc., Introduction Introduction - 52 Interconnects: Coupling capacitance increases (+ crosstalk, + self-capacitance), Resistance increases (reduced cross-section, surface scattering, grain-size limitations, skin effect ) SIGNAL INTEGRITY RC constant of all interconnects increases while gate τ decreases Clock skew in Alpha processor: Signal delays, clock skew impose severe design challenges Rabaey, Chandrakasan, Nikolic 53 Introduction Introduction - 53

22 SIGNAL INTEGRITY Power density (temperature) is one of the major challenges in microelectronics today Temperature differences imply performance differences Clock skew for example is also affected by temperature differences 54 Introduction Introduction - 54 SYSTEMS IN A PACKAGE (SiP( SiP) Integration of non-cmos technologies Best technology option for each part Solution to signal integrity High-Q passives can be implemented Heat Sink Metal Cap Flip Chip Flip Chip SMD SMD B.T. Cost Packaging Yield Lack of system integration models/tools 55 Introduction Introduction - 55

23 NEED TO INCLUDE THESE EFFECTS IN DESIGN PROCESS First silicon success concept Needed today: A. Khan, Cadence Design Systems Inc., Introduction Introduction - 56 NEED TO INCLUDE THESE EFFECTS IN DESIGN PROCESS First silicon success only possible if all the nanometer effects are accounted for during design process: Conventional design flow : Design entry and synthesis Pre-layout simulations Layout synthesis / full custom design Parasitics extraction Post-Layout simulation and final verifications Manufacturing 57 Introduction Introduction - 57

24 NEED TO INCLUDE THESE EFFECTS IN DESIGN PROCESS Process, Vdd and thermal variations included in all design models Conventional design flow : Design entry and synthesis Budgets for clock skew, thermal variations, Vdd and GND noise and drops Pre-layout simulations Chip-package co-design Layout techniques for manufacturing, minimization of process variations, matching, signal integrity Models for all parasitics Layout synthesis / full custom design Parasitics extraction Post-Layout simulation and final verifications Manufacturing 58 Introduction Introduction - 58 FUTURE CHALLENGE: DESIGN TOLERANT TO NANOMETER EFFECTS It must be assumed that nanometer effects (noise, couplings, voltage, temperature and process variations) are both unavoidable and unpredictable (in a deterministic way) Design must become tolerant to nanometer effects, tolerant to local failures. Models will become statistical, statistic design methodologies will be assumed, leading to desired yields. 59 Introduction Introduction - 59

25 PRE-REQUISITES: REQUISITES: CMOS technology basic concepts (layers, geometry, models) CMOS technology manufacturing process (basic concepts) Fundamentals of CMOS digital and analog circuit design IC design methodology 60 Introduction Introduction - 60