Packaging Roadmap: The impact of miniaturization. Bob Pfahl, inemi Celestica-iNEMI Technology Forum May 15, 2007

Transcription

1 Packaging Roadmap: The impact of miniaturization Bob Pfahl, inemi Celestica-iNEMI Technology Forum May 15, 2007

2 The Challenges for the Next Decade Addressing the consumer experience using the converged digital technology base Adopting to changing industry structure Creating new product markets with social value Energy Healthcare Security Closing technology gaps 1

3 The End of Semiconductor Scaling The anticipated end to semiconductor scaling will create a major technology shift in the industry: Implementation of advanced, non-classical CMOS devices with enhanced drive current Identification, selection, and implementation of advanced devices (beyond-cmos) Increased need for improved cooling Potential need for high speed optical communications Innovative packaging for: Nano size devices Hetro systems Innovation must begin today to meet these needs 2

4 Six Identified Strategic Gaps Active Device Technology Thermal Management Communications Bandwidth Design and Simulation Tools Sustainability Metrics Next Generation Packaging Technology 3

5 Active Device Technology Implementation of advanced, non-classical CMOS devices with enhanced drive current Identification, selection, and implementation of advanced devices (beyond-cmos) Device technology drives the following strategic system gaps Multi-wall carbon nanotubes (NanoDynamics Inc.) 4

6 Thermal Management Increased need for improved cooling Improved materials and design concepts Focus is on local hot spots Must design from device to system level BN coated with Al203 (ALD Nanosolutions Inc) 5

7 Communications Bandwidth Copper? RF? Optical? Where? When? How Fast? At what cost? The 2007 Roadmap does not provide guidance 6

8 Sustainability Metrics Development & implementation of scientific methodologies: Assess true environmental impacts of materials Potential trade-offs for alternatives Develop a common, straightforward definition of sustainability 7

9 Design and Simulation Tools Design & simulation tools are main roadblocks to more rapid introduction of new technologies: Mechanical & reliability modeling Thermal & thermo-fluid simulation Co-design of mechanical, thermal & electrical performance of the entire chip, package & associated heat removal structures Simulation tools for nano devices & materials Improved design tools for emerging technologies like embedded passives & optoelectronic PWBs Integrated design & simulation tools (circuit, EM, thermal, mechanical, manufacturing, etc.) for higher functionality in mixed-mode wireless chips & modules 8

10 Next Generation Packaging Technology Innovative Miniaturized Packaging Source: Professor Dr. Reichl, Fraunhofer IZM, Berlin Germany 9

11 Progress is Exceeding Roadmap Forecast 3D packaging Techniques for 3D packaging are proliferating Flexible/wearable electronics Wafer thinning Wafer level packaging System level integration in package 10

12 Major Challenges Handling for ultra-thin die Cost targets for new package types Co-design tools for SiP, 3D packaging, TSV, etc. Handling increasing thermal density (particularly for 3D packaging) Incorporation of new materials Signal integrity for complex SiP 11

13 Packaging is now a limiting factor but it is enabling for more than Moore Packaging has become the limiting element in system cost and performance The assembly and packaging role is expanding to include system level integration functions. As traditional Moore s law scaling become more difficult innovation in assembly and packaging can take up the slack. 12

14 Moore s s Law Scaling Cannot Maintain the Pace of Progress Beyond CMOS Information Processing Digital content System-on-Chip (SOC) Λ. 22nm 32nm 45nm 65nm 90nm 130nm Combine SOC & SiP : Higher Value System More Moore : Scalingn Analog/RF Baseline CMOS: CPU, Memory, Logic Passives HV Power More than Moore : Functional Diversification Interacting with people and environment Non-digital content System-in-Package (SiP) Sensors Actuators Biochips 13

15 System Integration System on Chip Cost / function Time to market MEMS Bio-Interface SiP and 3D Packaging Power supply System complexity 14 Source: Fraunhofer IZM

16 System-in in-package Definition System in Package (SiP) is a combination of multiple active electronic components of different functionality, assembled into a single unit, that provides multiple functions associated with a system or sub-system. A SiP may optionally contain passives, MEMS, optical components and other packages and devices. Note that this definition rules out stacked memory die. However, many of the technology drivers are the same. 15

17 SiP - Situation Analysis Market: In 2004, 1.89 Billion SiPs were assembled. By 2008, this number is expected to reach 3.25 Billion, growing at an average rate of about 12% per year. Technology: SiP applications have become the technology driver for small components, packaging, assembly processes and for high density substrates. Growth: System-in-Package (SiP) has emerged as the fastest growing packaging technology segment although still representing a relatively small percentage of the unit volume. 16

18 Categories of SiP Horizontal Placement Wire Bonding Type Flip Chip Type Stacked Structure Interposer Type Wire Bonding Type Wire Bonding + Flip Chip Type Flip Chip Type Interposer-less Type Terminal Through Via Type Embedded Structure Chip(WLP) Embedded + Chip on Surface Type 3D Chip Embedded Type Source: K. Nishi, Hitachi, JEITA, Revised by H. Utsunomiya WLP Embedded + Chip on Surface Type 17

19 SiP: Multi-level level System Integration SiP may include SoC and other traditional packages Packages may include: Sub-system packages Stacked thin packages containing passives and active chips Mechanical, optical and other non electrical functions Complete systems or sub-systems with embedded components Bare die SoC Source: Fraunhofer IZM 18

20 Wafer Level SiP - Vision Energy source MEMS ASIC + memories Cooling Embedded passives Source: LETI 19

21 3D Stacked Die Package Substrate Base SiP ( up to 7/ 8 die) Die thickness : 60 um Substrate (BT) thickness : 130 um Solder ball Stand-off : 50 um 20

22 Projection for stacked die SiP packages 2014 through 2020 Low cost/handheld (# die / stack) High performance (# die / stack) Low cost/handheld (# die / SiP) Limited by thermal density 21

23 SiP presents new Design Challenges for signal integrity, power integrity and shielding Signal integrity for high density interconnect Cross talk Impedance discontinuities (reflections) Timing skew Parasitic capacitance, resistance and inductance in long traces (inductance change for each layer for wire bonded stacked die) Power integrity Voltage drop for high speed signals (lead and trace inductance limits power delivery) Ground noise due to high frequency current variations Shielding Radiated noise within the package at high frequency External electromagnetic noise sources 22

24 Interconnect Challenges for Complex SiPs Die New circuit elements and components place expanded demands on the environment provided by the package 3D SiP Evolutionary and revolutionary interconnect technologies are needed to enable the migration of microsystems from conventional state-of-art to 3D SiP. Fluidics Optics MEMS Passives RF Bio/organic 23

25 Potential Solutions for Interconnect Challenges 24

26 Many variations of SiP package interconnect are in use or in development today POP (WB Type) POP (Film Type) POP (FC Type + Interposer) POP (only for Memory) PIP - Molded PIP - Spacer 25

27 Interconnect Requirements may be satisfied by Wave Guide Optical Solutions Die VCSEL/PD Solder bump Waveguide Lens Polymer pin Substrate Quasi free-space optical I/O Mirror Substrate Lens assisted quasi free-space optical I/O Substrate Surface-normal optical waveguide I/O Optical source/pd Fiber Substrate Board-level integrated optical devices Fiber-to-the-chip Substrate Examples of guided wave optical interconnects for chip-to-chip interconnection. 26

28 Low k ILD may Require Improved Underfill or Compliant I/O connections Si die Si die The use of compliant electrical I/O can potentially eliminate the need for underfill reducing cost and processing complexity as I/O density rises. 27

29 SiP Presents New Challenges for Thermal Management High performance generates high thermal density Heat removal requires much greater volume than the semiconductor Increased volume means increased wiring length causing higher interconnect latency, higher power dissipation, lower bandwidth, and higher interconnect losses These consequences of increased volume generates more heat to restore the same performance Projection for 14nm node Power density >100W/cm2 Junction to ambient thermal resistance <0.2degrees C/W 28

30 Thermofluidic Heat Sinks may be the Solution Conventional thermal Interconnects Back-side integrated fluidic heat sink using TIM and inlets/outlets Back-side integrated fluidic heat sink and Back and front-side inlets/outlets tube Die Thermal interface Material fluidic I/O Examples of thermofluidic heat-sink integration with CMOS technology. 29

31 Test Challenges of SiP Test cost BIST and other embedded test approaches Thermal management Test access Contactor/ connection issues Single chip testing in SiP configurations Time to market 30

32 inemi Response to Packaging Gaps Minaturization Focus Area Board and System Manufacturing Test TIG Thermal Management TIG SIP TIG Reliability protocols Field failure Pareto Board Assembly TIG Warm assembly Nano solder 31

33 Packaging is now a limiting factor but it is enabling for more than Moore Packaging has become the limiting element in system cost and performance Does not scale like silicon Off chip speed limited by interconnect The Assembly and packaging role is expanding to include system level integration functions. Cooling Embedded passive/active devices Assembly & packaging can take up the slack 3D packaging Wafer level SiP 32

34 contacts: Jim McElroy Bob Pfahl 33