BiCMOS055 Technology Offer

Transcription

1 BiCMOS055 Technology Offer STMicroelectronics Technology & Design Platforms, Crolles February 2016

2 Best-in-class BiCMOS BiCMOS055 (B55)* is: The latest BiCMOS technology developed in STMicroelectronics to address demanding Optical, Wireless and High- Performance Analog Applications The only high-speed BiCMOS technology in 55-nm CMOS fabricated in 300-mm manufacturing facility Pre-production qualified HS NPN peak f T and f MAX (GHz) BiCMOS9MW (ST) f T f MAX HS cells: HD cells: BICMOS8XP (IBM) 130 nm 200 mm SG13G2 (IHP) ST data IBM data ST data 1200 Wafer size 300 mm 1000 BICMOS9HP (IBM) CMOS node INTEL 90 nm BiCMOS055 (ST) 55 nm Standard cells density (Kgate/mm²) (*) P. Chevalier et al, 55 nm Triple Gate Oxide 9 Metal Layers SiGe BiCMOS Technology Featuring 320 GHz f T / 370 GHz f MAX HBT and High-Q Millimeter-Wave Passives Proceedings of the 2014 International Electron Devices Meeting (IEDM), San Francisco, CA (USA), December 2014, pp BiCMOS055 February 2016

3 15 years BiCMOS at ST Continuous improvement of SiGe HBT performance with CMOS scaling f T and f MAX increased by a factor of ~6 from 0.35µm to 55nm CMOS nodes BiCMOS6G BiCMOS7 BiCMOS7RF BiCMOS9 BiCMOS9MW BiCMOS055 f T (GHz) Collector current density J C (ma/µm²) f MAX (GHz) BiCMOS6G BiCMOS7 BiCMOS7RF BiCMOS9 BiCMOS9MW BiCMOS Collector current density J C (ma/µm²)

4 Technology offer & devices targets

5 55nm triple-gate oxide CMOS baseline LP & GP HVT, SVT & LVT * CMOS w/ 2.5V IOs + LP SVT & HVT SRAM * High-Performance Analog GO1 LP LVT CMOS * Natural bipolar transistors, resistors & capacitors + 6 k /sq. HIPO resistor * SiGe NPN HBTs (High-Speed Medium-Voltage & High-Voltage * ) AMOS varactors Diode varactors Overview Thick copper BEOL 5 ff/µm² MIM * Thin Film Resistor * Transmission lines Inductors (*) Option 55-nm SiGe BiCMOS technology = BiCMOS055 Core process: 50 masks / Options: Up to +11 masks (w/o bumping)

6 Technology cross-sections

7 BEOL schematic cross-section 9 metal layers (including Aluminum capping) BEOL obtained by the introduction of a thick Via/Line copper module : 3µm thick M8U and 1.5µm thick V7U MIM integrated in V5Z TFR integrated in V6Z All the 55-nm CMOS libraries are therefore compatible with BiCMOS055 CB Via7U Via6Z Via5Z Via4X BiCMOS055 8M4X2Z1U TFR MIM AP M8U M7Z M6Z M5X Via6Z Via5Z Via4X CMOS055 7M4X2Z0U AP M7Z M6Z M5X M2 to Last Metal Layer 5.5µm M1 polysi 3.1µm M1 polysi

8 BiCMOS055 devices list (DK2.3) Core LP/GP HVT & SVT CMOS w/ 2.5V GO2 (incl. RF SVT for LP, GP & GO2) High-Speed & Medium-Voltage SiGe HBTs Natural devices NPN & PNP bipolar transistors Resistors (active, poly & metal incl. RF resistors) Diodes (N+/Pwell, P+/Nwell, Deep Nwell/Psub, ) DC capacitors (poly, plate) Varactors Single & Diff. GO1/GO2 P+ poly/nwell varactors P+/Nwell diode varactor RF MOM MMW, HQ & LOHQ inductors µstrip transmission line Options LP & GP CMOS LVT (incl. RF models for LP & GP) SRAM SVT + HVT High-Performance Analog (HPA) CMOS (incl. RF models) High-Voltage SiGe HBTs 6k /sq. HIPO resistor (incl. RF model) 5fF/µm² MIM capacitor (incl. RF model) Thin Film Resistor Flip-Chip bumping

9 Devices targets LP & GP CMOS Low Power (LP) and General Purpose (GP) CMOS Device Low Power MOS (T OX =18.5Å) General Purpose MOS (T OX =13Å) I ON (µa/µm) I OFF (na/µm) I ON (µa/µm) I OFF (na/µm) Low V T NMOS Low V T PMOS Standard V T NMOS Standard V T PMOS High V T NMOS High V T PMOS L drawn =0.06µm, W drawn = 1.0 µm, T=25 C

10 Devices targets SiGe HBTs 3 collector flavors sharing the same E/B system Scalable emitter widths and lengths Device f T (GHz) f MAX (GHz) BV CBO (V) BV CEO (V) High-speed SiGe HBT schematic cross-section HS NPN SiGe HBT npnvhs, npnvhs_t 320 V CB =0.5V V BE =0.90V 370 V CB =0.5V V BE =0.90V 5.2 I CB =10µA 1.5 I B =0µA Pedestal oxide C C C B in-situ doped SiGe:C Base B E As in-situ doped Emitter B B doped Polybase C C C MV NPN SiGe HBT npnvmv, npnvmv_t 180 V CB =1.0V V BE =0.87V 380 V CB =1.0V V BE =0.87V 7.2 I CB =10µA 1.8 I B =0µA Localized Collector Collector Sinker HV NPN SiGe HBT npnvhv, npnvhv_t 70 V CB =2.0V V BE =0.80V 250 V CB =2.0V V BE =0.80V 13.5 I CB =10µA 3.2 I B =0µA Epitaxial Collector Buried Layer Shallow Trench Isolation (STI) Deep Trench Isolation (DTI) Double Polysilicon Self-Aligned (DPSA) architecture featuring a Selective Epitaxial Growth (SEG) of the base CBEBC: W drawn = 0.2 µm, L drawn =5.56µm, T=25 C

11 Devices targets Varactors & capacitors P+ Poly/NWell GO1 & GO2 benefit from short gate lengths Device Oxide type Capacitance range (Cmin / max) Typical tuning 25 C =100 ff Max C = V =1,2 V C =100 1,2 V 2,5 V (GO2) Varactor P+/NWell GO1 SE cpo12nw_var GO1 1,2 V 5 ff / 1 pf 3 (max 5) 20 > 110 GHz Varactor P+/NWell GO2 SE cpo25nw_var GO2 2,5 V 5 ff / 1 pf 3 (max 5) 30 > 110 GHz RF MOM MIM C 0 ~0.9 ff/µm² (M1-M2) to ~3.0 ffµm² (M1-M5) / C V1 < 1 ppm/v C 0 =5.0 ff/µm² / C V1 < 150 ppm/v / C V2 < 100 ppm/v²

12 Devices targets Inductors & transmission lines Inductors & TL benefit from the 8ML BEOL with thick V7/M8 Device Stack L Qmax MMW Inductor ind_mmw_8m4x0y2z1u Inductors geometry: Coil M8U Upath M7Z Gnd ring M1 Number of coil turns (n): 1 to 4.25 From 65pH to 1.6nH Internal coil diameter (d): 10 to 50 µm Coil width (w): 0.6 to 4 µm Self resonance frequency > 10 From 27GHz to 300GHz 1-turn inductor 3D view M8 line 4.25-turn inductor 3D view Device Stack Zc IL M1 gnd µ-strip TL microstrip_8m4x0y2z1u Line in M8U Gnd in M1 or M4 From 35 to 70 Lateral wall 3D schematic view

13 All options are compatible with each other* Process options Masks count Masks count Core process 50 SRAM 3 Triple-V T Low-V T (LVT, SVT and HVT transistors) 2 High-Performance Analog (HPA) CMOS 2/4* HIPO (6k /sq poly resistor) 1 HV (High-Voltage) NPN 0 MIM (5fF/µm²) 2 TFR (Thin Film Resistor) 1 Flip-Chip 1 (*) HPA CMOS are LVT MOS devices. This option requires 2 masks in addition to LVT option, then 4 masks if standard LVT MOS devices are not used

14 Design kit & design platform

15 Design kit Front-end/Schematic capture EDA tools EDA Vendors Schematic Capture (Composer) IC Cadence Simulation model libraries Eldo Mentor Spectre Hspice Cadence Synopsys RF Simulation ADS (RFDE) Agilenteesof GoldenGate Agilenteesof ADS environment ADSKit ST Layout Entry & Finishing EDA tools EDA Vendors Layout Placement Virtuoso Layout Editor Cadence Layout Verification : DRC/LVS DFM YA/YE/YS Parasitic Extraction : interconnect RC Post Layout Simulation flow Calibre pvs StarRCXT ext PLSKit Totem Mentor Cadence Synopsys Cadence ST Apache

16 Design platform content

17 Design platform flows

18 Design platform version

19 Design flow