Fabrication, Corner, Layout, Matching, & etc.

Transcription

1 Advanced Analog Building Blocks Fabrication, Corner, Layout, Matching, & etc. Wei SHEN (KIP) 1

2 Fabrication Steps for MOS Wei SHEN, Universität Heidelberg 2

3 Fabrication Steps for MOS Wei SHEN, Universität Heidelberg 3

4 6 METAL BiCMOS Technology Wei SHEN, Universität Heidelberg 4

5 Process Corner main cause for corners : Threshold voltage variation, Caused by doping N and P mosfets are correlated SPFN does not take SP in SPSN and FN in FPFN FPSN and SPFN are closer to TT Wei SHEN, Universität Heidelberg 5

6 Matching / Variation Devices even designed as same will not be fabricated as same. Error sources : traces/geometry error in fabrication(lithograhy), doping variation, implantation tilt, edge effects (surroundings) Monte Carlo Simulation (traces and doping, data calibrated in perfect layout form) Wei SHEN, Universität Heidelberg 6

7 Matching / Variation Mismatch flag in schematic design Wei SHEN, Universität Heidelberg 7

8 Fabrication of Passive Components Capacitance : 3 types, MiM, MOS and MoM MiM : Metal - Insulator - Metal accurate capacitors, used for shaping, signal processing, insensitive to voltage bias, good matching performance (10fF 10pF, area demanding, 1fF/um2) MOS : Poly - Oxide - Diffusion/Well not so accurate, used for filtering, compensation, sensitive to voltage bias, bad matching performance (1pF 50pF) MoM : appears in the deep sub-micron technology (65nm), well arranged parasitic capacitors from metal traces, good matching performance, better used as unit capacitors for ADCs (< 10fF, 0.17fF/um2) Wei SHEN, Universität Heidelberg 8

9 MiM capacitors high dielectric layers between the second top metal layers and one additional metal layer (minimum complexity to build, economical) typical dielectric layers are SiO 2 or Si 3 N 4, the relative permittivity depends on both the material (major) and the fabrication technology (minor), Si 3 N 4 used as SiO 2 Si 3 N 4 SiO 2 structure C = ε s d the distance can be reduced to enhance unit capa but limited by the E strength (avalanche, short) -- dielectric strength (E) Wei SHEN, Universität Heidelberg 9

10 MiM capacitors - parasitics P. Fischer Wei SHEN, Universität Heidelberg 10

11 MiM Capacitor Variability Process : the thickness as well as the composition of the dielectric oxide depending a lot on the process uniformity (uniformity and repeatability of the process control) Max / Min 1.2 Voltage and Temperature : of much less concern compared to MOS capacitor, but non-linear dependence exists different E, dielectric constant) Wei SHEN, Universität Heidelberg 11

12 Common Centroid Layout against gradients from different directions, more symmetric Typical Matching Accuracy of MiM 0.1%, 10 bit resolution Wei SHEN, Universität Heidelberg 12

13 Matching for capacitors In reality, the signal connection has to be considered with signal line parasitics etc more or less complex!! Dummies at the end to improve symmetry!! Absolute parasitics are not fully trustable, but relative parasitics are! Wei SHEN, Universität Heidelberg 13

14 MOS capacitor use the gate oxide as the dielectric material gate poly & well as contacts similar to MOSFETs Well (highly doped diffusion) for bottom plate connection, special mask However, MOSFET needs to generate the bottom connection channel Why still use MOSFET as CAPA? Wei SHEN, Universität Heidelberg 14

15 MOSFET as Capacitor voltage dependent Depletion modulation, worse in matching than MIM, as well as the absolute accuracy If MOSFET used as decoupling capacitor, bias voltages has to be taken care of DC voltage decoupler has to be chosen correctly, NMOS or PMOS depending on the voltage Wei SHEN, Universität Heidelberg 15

16 Parasitics of MOS capa Channel resistance will affect the parasitics, multiple in parallel Wei SHEN, Universität Heidelberg 16

17 Summary of MOSFET capacitor Wei SHEN, Universität Heidelberg 17

18 Metal Oxide Metal Capa much smaller in unit size 0.2 ff/um 2, matching 0.1% (10bit) coming with smaller Technologies because trace fabricated with better resolution (X ray) provided as standard component in the library, specifiy width and length Pros : smaller in size, smaller CR constant response speed much shorter Other Names : (Metal) Finger Capacitors (Lateral) Flux Capaticors... SAR ADC design ~ 40 MHz >150MHz Sps similar T and V coefficient as MIM Cons : Wei SHEN, Universität Heidelberg 18

19 Metal Oxide Metal Capa Vertical parallel plates used to manipulate the unit capa size, the distance and thickness between plates, and oxide density... Vertical bars Wei SHEN, Universität Heidelberg 19

20 Parasitics for Metal Plate Caps General parasitics for Metal plate capas (MIM and MOM) Top plate parasitic is around C des Bottom plate parasitic around C des In most cases in signal processing, signal connection is better to top plate However, in some cases of SAR ADC designs bottom plate sampling is used to pursuit better dymanic performance (switching speed, power) Wei SHEN, Universität Heidelberg 20

21 Parasitics for Metal Plate Caps Error sources for Metal Caps Wei SHEN, Universität Heidelberg 21

22 Resistors PolySilicon Resistors Low Sheet Resistance High Sheet Resistance Doped Silicon Resistors (Diffusion/ Well Resistors) Wei SHEN, Universität Heidelberg 22

23 Resistors R = ρ L, only the ratio matters, therefore, S unit is the square, the real resistance is the number of. However, the size can be tailored, for matching, thermal, parasitics etc... Wei SHEN, Universität Heidelberg 23

24 Polysilicon Resistors the preferred accurate resistors with less parasitic On top of Oxide to decouple Matching 0.2%, a bit worse than MIMcap Silicide Polysilicon Resistor And non-silicide Polysilicon Resistor Silicide, Metal/Silicon Compound deposited On top of Polysilicon to reduce sheet resistance TiSi2 TaSi2 WSi2 can be used. Metal Sputtered, Then silicidation occurs. Different Doping/Implatation happens before Metal Sputtering to enhance uniformity and tuning R. P+ or N+, can be combined with S/D doping Gate Polysilicon formed with Silicided Polysilicon low resistance but still higher than metal R High Sheet Resistor will be created without Silicide Wei SHEN, Universität Heidelberg 24

25 Polysilicon Resistors Well Schielding Careful with the Doping and substrate Polarity N+ / P+ / Light P has Different sheet R, And different substrate Wei SHEN, Universität Heidelberg 25

26 Layout of Polysilicon Resistors Large Resistors have the snake shape, large L/S As the resistance calculated by number of, does it make sense to draw scaled L/S? NO! Termianl Resistance does not scale, doping matters!!! Wei SHEN, Universität Heidelberg 26

27 Layout of Polysilicon Resistors Use units for matching, preferred Not preferred, why? Two material : Polysilicon / Silicide Cause voltage potential With temperate gradiant Seebeck Effect Wei SHEN, Universität Heidelberg 27

28 Layout of Polysilicon Resistors Common Centroid & Dummies However, in practice not so useful, resolution also limited by trace resistance, typical resolution 9 bits, not better than MIMcap Wei SHEN, Universität Heidelberg 28

29 Well/Diffused Resistors Using the doped silicon sheet resistance, not accurate resistors, parasitic with well diodes, why still used?? Wei SHEN, Universität Heidelberg 29

30 Well/Diffused Resistors 1) High current capability of diffusion resistor in comparison with poly resistor. 2) Diff. resistor has an feature, it can limit current due to velocity saturation effect. 3) High resistance in signal path gives increased delay for signals. (smooth) 4) parasitic diode for protection ESD protection circuit Wei SHEN, Universität Heidelberg 30

31 Layout Techniques of MOSFETs Wei SHEN, Universität Heidelberg 31

32 Layout Techniques of MOSFETs What is the disadvantage of large gate resistance? Voltage Drop due to leakage current Thermal noise Wei SHEN, Universität Heidelberg 32

33 Layout Techniques of MOSFETs dummies Substrate contacts for large transistors Wei SHEN, Universität Heidelberg 33

34 Matching Property Lattice structure of 110 direction In silicon substrate, tilt during implantation Source and Drain are not identical Due to this fact Slightly different, therefore Matching of the device is important Wei SHEN, Universität Heidelberg 34

35 Common Centroid Layout Centroid of the matched devices should sitting on each other Equal number of segments In both X and Y direction Wei SHEN, Universität Heidelberg 35

36 In Reality Most of times, symmetry in one direction can be performed but not both, in these cases interdigitate pattern is important 2 3 Wei SHEN, Universität Heidelberg 36

37 Interdigitiation Patterns Maloberti Metal trace should also be matched Wei SHEN, Universität Heidelberg 37

38 Example Maloberti Wei SHEN, Universität Heidelberg 38

39 Remarks 1. matching property for different Transistor species (low V th, normal V th, zero V th ) the more steps in fabrication, the worse the matching (normal V th < low V th < zero V th ) 2. Blocks with several identical submodules in chain, please let the voltage/current transfer direction aligned in one direction or back and forth direction (VCO) Wei SHEN, Universität Heidelberg 39