Analog Devices AD7658 Analog to Digital Converter icmos Process Technology Process Review

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1 November 1, 2005 Analog Devices AD7658 Analog to Digital Converter icmos Process Technology Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.

2 Process Review Table of contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Major Findings 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Double Poly MIM Capacitors 3.7 Poly Resistors 3.8 MOS Transistors 3.9 Isolation 3.10 Lateral PNP Bipolar Devices 3.11 Diodes 3.12 Wells, Epi and Substrate 3.13 High Voltage MOS Transistors 4 References 5 Critical Dimensions 5.1 Package and Die 5.2 Vertical Dimensions 5.3 Horizontal Dimensions Report Evaluation PPR November 1, 2005

3 Overview Overview 1.1 List of Figures 2 Package and Die Package Top Package Bottom Pin Diagram Package x-ray Top-View Package x-ray Side-View Die Photograph Die Markings Die Photograph at Metal Die Photograph at Poly Annotated Die Photograph Die Corner a Die Corner b Die Corner c Die Corner d Minimum Pitch Bond Pads Single Bond Pad 3 Process General Structure Die Edge Die Edge Seal Ball Bond to Bond Pad Bond Pad Edge Bond Pad Edge Detail Dielectrics General Structure Passivation IMD IMD PMD PMD and LOCOS Isolation Metallization General Structure Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal 1

4 Overview Vias and Contacts General Structure Minimum Pitch Via 2s Minimum Pitch Via 1s Minimum Pitch Contacts to Substrate Contact to Poly Contacts to Poly Poly MIM Capacitors and Poly Resistors Poly MIM Capacitor Contact to Poly MIM Capacitor Detail Interpoly Dielectric and Cap Oxide Poly Resistors Poly Resistor Contact Poly Resistor Pitch Poly Resistor Pitch Detail Minimum Gate Length NMOS Transistor Minimum Gate Length PMOS Transistor MOS Transistors (Glass-Etch Only) Minimum Pitch NMOS Transistors Minimum Pitch PMOS Transistors NMOS Transistor with Double Contact Plan-View NMOS Transistor with Double Contact Large NMOS Transistor Minimum Width LOCOS Isolation Poly over Minimum Width LOCOS Isolation Poly over LOCOS Isolation PNP Device at Metal 3 Plan-View PNP Device at Poly Plan-View Large PNP Device (Cross-Section 5) Large PNP Device Detail (Cross-Section 5) Large PNP Device SCM (Cross-Section 9) Small PNP Devices SCM (Cross-Section 8) Small PNP Device Detail SCM (Cross-Section 8) Diodes at Metal 3 Plan-View Diode (Cross-Section 2) Diode SCM Diode Detail SCM

5 Overview Well and Epi Structure Shallow Wells SCM SRP of P-Well SRP of N-Well HVMOS Transistors Plan-View HVMOS Transistors Detail Plan-View HVNMOS Transistor Overview HVNMOS Transistor HVNMOS Transistor Contact to Gate Spacing HVNMOS Transistor Gate Oxide HVNMOS Transistor SCM HVNMOS Transistor SCM Detail HVPMOS Transistor Overview HVPMOS Transistor HVPMOS Transistor Contact to Gate Spacing HVPMOS Transistor Gate Oxide HVPMOS Transistor SCM HVPMOS Transistor SCM Detail

6 Overview List of Tables 1 Overview Device Summary Summary of Major Findings 2 Package and Die Package and Die Dimensions 3 Process Dielectric Composition and Thicknesses Metallization Composition and Thicknesses Minimum Metals Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor and Polysilicon Horizontal Dimensions Transistor and Polysilicon Vertical Dimensions Isolation Horizontal Dimensions Wells and Epi Vertical Dimensions HV Transistor and Polysilicon Horizontal Dimensions HV Transistor and Polysilicon Vertical Dimensions 5 Critical Dimensions Package and Die Dimensions Vertical Dimensions Horizontal Dimensions

7 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

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