ECSE-6300 IC Fabrication Laboratory Lecture 7 MOSFETs. Lecture Outline

Transcription

1 ECSE-6300 IC Fabrication Laboratory Lecture 7 MOSFETs Prof. Rensselaer Polytechnic Institute Troy, NY Office: CII-6229 Tel.: (518) s: luj@rpi.edu /index.html 7-1 Lecture Outline MOSFET Structures MOS Physics Accumulation, Depletion and Inversion Threshold Voltage I-V Characteristics MOSFET Process Chip Layout Note: The lecture slides were prepared based on the original materials written by Profs. T.P. Chow and J.-Q. Lu 7-2

2 FabLab Goal: n- and p-channel MOSFETs Source Gate Drain Poly Si Gate Oxide ILD n+ Channel n+ P Substrate 15 Weeks 4 Masks 1 Ion Implant Tools: Furnaces (2) P5000 OAI Aligner RIE etcher (Trion, Alcatel) Sputter Wet bench 7-3 P-type Flatband Condition Ideal MOS Structure N-type V FB = m [ + (E C -E F )/q] = 0 7-4

3 Accumulation 7-5 Depletion 7-6

4 Inversion 7-7 Surface Potential Semiconductor Surface q E g E C q S ( S >0) Insulator ~10 nm (x) q B P Type Semiconductor qn x A Q n E i E F E V S < 0 Accumulation S = 0 Flatband B > S >0 Depletion S > B Inversion Surface charge density Q S can be obtained by solving the Poisson s equation Q S 7-8

5 Basic MOS Physics Surface Charge vs. S Under accumulation, Q S = (2 S kt/ql D ) exp (q S /2kT ) Under depletion, Q S = ( S /L D ) (2(kT/q) S ) 1/2 = (2 S qp p0 S ) 1/2 = (2 S qn A S ) 1/2 Under strong inversion, when S > 2 B = 2(kT/q) ln(n A /n i ) Q S = ((2n p0 /p p0 ) 1/2 ( S kt/ql D ) exp(q S /2kT) = (2 S n p0 ) 1/2 exp(q S /2kT) C Q S S 7-9 Quasi Static MOS Capacitance For V G << 0, C TOTAL C C For 0 < V G < 2 B, C TOTAL = ( C s C ) / ( C s + C ) For V G > 2 B, Inversion layer shields electric field from penetrating into the semiconductor bulk. d A Do the minority carriers follow the ac gate signal? (a) Low frequency (b) High frequency (c) Deep depletion (pulse) 7-10

6 Basic MOS Physics Threshold Voltage, V T Threshold voltage is the minimum gate voltage at which the strong inversion exists V G = V + S Oxide field: V =E t = Q S t / = Q S /C V T = Q S /C + 2 B = (4 S kt/q 2 N A )ln(n A /n i )] 1/2 /C + (2kT/q)ln(N A /n i ) 7-11 Oxide and Interface Charges It is convenient to define a net effective ide charge per unit area Q 1 t 0 t ( x' t so that V FB = MS -Q/C ) ( x') dx' Besides Q it and Q f, Q m (alkali ion charge, positive) and Q ot (ide trap charge, positive or negative) are also possible: Q = Q f + Q it + Q m + Q ot 7-12

7 Threshold Voltage Non Ideal MOS Non-ideal MOS factors include: (a) Metal-Semiconductor work function difference, MS = ( m - S ) = ( B + ) - ( + E g /2q + B ) (b) Fixed ide charges (Q f ), (c) Mobile ion charges in the ide (Q m ), (d) Interface state charges (Q it ). V T V T = V T ideal + MS + (Q f +Q m +Q it )/C V T ideal + MS + Q f /C 7-13 Threshold Voltage Gate Oxide vs. Field Oxide 7-14

8 MOSFET Basic Operation: A field-induced channel to connect two adjacent source and drain junctions. MOSFET Features: 4 th terminal (substrate or backgate terminal) MOS-induced channel Pinchoff near the drain end Parasitic npn 7-15 MOSFET Assumptions: V SB = 0 and V DS > 0 If V GS > V T, a layer of inversion electrons is formed and flows from the source region to the drain. The electrical current, corresponding to this electron flow, I DS, flows from the drain to the source. If V GS < V T, I DS 0. This is an Enhancement-Mode, N-Channel MOSFET When V SB > 0, V T increases. Other types of MOSFETs: Depletion-Mode, N-Channel Enhancement-Mode, P-Channel Depletion-Mode, P-Channel 7-16

9 MOSFET 7-17 MOSFET Type of MOSFETs Enhancement Mode, N Channel Depletion Mode, N Channel Enhancement Mode, P Channel Depletion Mode, P Channel V T I DS > 0 > 0 < 0 > 0 < 0 < 0 > 0 <

10 MOSFET A unipolar carrier device. Minority carriers in the surface channel are separated from the majority carriers in the substrate by a space-charge or depletion layer. Carriers are transported across the channel by drift. Current condition continues even when the inversion layer disappears on the drain end MOSFET 7-20

11 MOSFET Channel Resistance Gate voltage exceeds threshold voltage to induce an inversion layer in the channel region (Vertical electric field across the gate ide) Drain voltage to cause electron flow from source to drain (Lateral electric field to drift electrons across the channel) 7-21 MOSFET Channel Resistance Inversion charge Q n = C ( V G -V T ) Gradual Channel Apprimation dr = dy / (Z ns Q n (y)) Q n (y) = C [V GS -V T - V(y)] dv = I D dr 0 L I D At low drain voltages (linear region), and dy Z C ns V DS 0 ( V G V Z I D nsc ( VG VT ) V L L 1 Rch Z C ( V V ) ns G T T DS V ) dv MOSFET acts as a gatecontrolled resistor 7-22

12 MOSFET Channel Pinch off With increasing drain voltage 7-23 MOSFET I V Characteristics In the linear region, I Z D gm V DS ns VGS L At pinch-off and beyond (saturation region), g I D m, sat Z nsc 2L Z nsc L ( V C Channel length modulation: V G G V V T T V 2 ) DS MOSFET acts as a current source 2 S L VDS VDS, sat qn A 7-24

13 Start Material P Substrate Starting wafers (75) (100), 10 cm, P type Scribe wafers number IDs 7-25 Field Oxide P Substrate Field Oxide Mask #: M1 Active Area RCA clean Grow ide 1 m 1000C, dry/wet/dry/n2 Pattern field ide Etch field ide Plasma/BHF Strip PR Function: Device isolation, cross talk suppression Device Parameter: Field Threshold: >20 V desired 7-26

14 Field Oxide Poly Si Gate P Substrate Gate Definition Gate Oxide (100nm) Mask #: M2 Gate Function: MOS gate electrode Device Parameter MOS Threshold Voltage: V desired Poly Si: < 5 k/square sheet resistance desired RCA clean Grow gate ide 100 nm 1000C dry O2/N2 (30min) Poly Si 650 nm RCA Clean POCl 3 doping Deglaze Pattern gate Plasma etch doped Poly Si Strip PR 7-27 Field Oxide Poly Si Gate N + Source/Drain P Substrate n + (As or P) n+ n+ Function: Access regions to MOS channel Junction Depth: 0.5 m targeted Device Parameter R source, R drain <500 /square sheet resistance desired RCA clean Pattern source/drain (leave <30 nm ide) N+ Implantation Arsenic or Phosphorus*, 4e15cm 2, 150keV Strip PR 7-28

15 Source Gate and Source/Drain Contacts Gate ILD Drain n+ n+ P Substrate Mask #: M5 Contacts RCA clean Function: Transistor access to metallization Device Parameters Specific contact resistivity: <10 cm 2 desired 1 m ILD (ide) deposition (P5000) Densify ILD and activate implants (1000 o C/N2) Pattern gate and Source/drain contacts Etch ide Plasma etch (BHF dip) 7-29 Source Gate Metallization Drain ILD n+ n+ P Substrate Mask #: M6 Metallization Al/1% Si sputter deposition: 1.2 µm Pattern metal Etch Al/Si Plasma or wet etch Back side Al metal deposition Metal sinter Function: Transistor access to outside Device Parameters Metal sheet resistance: 0.1 /square desired 7-30