ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices
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1 ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University
2 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Part 1: ASIC Design Overview P M P M Topic 1 Hardware Description Languages Topic 4 Full-Custom Design Methodology Topic 6 Closing the Gap Topic 5 Automated Design Methodologies Topic 8 Testing and Verification Topic 3 CMOS Circuits Topic 2 CMOS Devices Topic 7 Clocking, Power Distribution, Packaging, and I/O ECE 5745 T02: CMOS Devices 2 / 33
3 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Agenda Simple Transistor RC Model Simple Wire RC Model CMOS Fabrication ECE 5745 T02: CMOS Devices 3 / 33
4 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Fundamental Building Block: MOSFET Transistor IBM Power Billion Transistors ECE 5745 T02: CMOS Devices 4 / 33
5 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Metal -Oxide-Semiconductor Structure Polysilicon Gate Silicon Dioxide Insulator p-type Silicon Body (doped to create mobile majority carriers, positively charged holes) Accumulation: Battery puts negative charge on gate, attracts positively-charged majority carriers in p-type silicon body Adapted from [Weste 11] ECE 5745 T02: CMOS Devices 5 / 33
6 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Metal -Oxide-Semiconductor Structure Polysilicon Gate Silicon Dioxide Insulator p-type Silicon Body (doped to create mobile majority carriers, positively charged holes) Depletion Region Depletion: Battery puts positive charge on gate, pushes positively-charged carriers away from surface, uncovers some negatively-charged dopant atoms in substrate Adapted from [Weste 11] ECE 5745 T02: CMOS Devices 5 / 33
7 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Metal -Oxide-Semiconductor Structure Polysilicon Gate Silicon Dioxide Insulator p-type Silicon Body (doped to create mobile majority carriers, positively charged holes) Depletion Region Inversion Region Inversion: Battery puts more positive charge on gate, instead of pushing holes even further away, draws free electrons to surface. Where did electrons come from? No electron donors in p-type silicon; electron/hole pairs always being generated by thermal excitation electrons caught by efield in depletion region Adapted from [Weste 11] ECE 5745 T02: CMOS Devices 5 / 33
8 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication NMOS Transistor Cutoff: V gs = 0V, Vds can be 0V or Vdd No Channel, I ds = 0 Linear: V gs = Vdd, V ds = 0V Channel Formed, I ds increases with V ds 0 < Vds < Vgs - Vt Vds > Vgs - Vt Linear: Vgs = Vdd, Vds = Vdd Channel Formed, I ds increases with V ds Saturation: Channel Pinched Off, I ds independent of V ds Adapted from [Weste 11] ECE 5745 T02: CMOS Devices 6 / 33
9 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Simple NMOS Circuit d V ds 0 < Vds < > Vgs - Vt Saturation: Cutoff: Linear: No Channel Channel, Pinched Formed I ds = 0 Off, I ds independent increases with of V ds V gs s Vgs =Vdd V t Vds =Vdd V gs I d I d log I d V V ds V ds V gs V gs time ECE 5745 T02: CMOS Devices 7 / 33
10 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Key Qualitative Characteristics of MOSFET Transistors R eff C d I V t sets when transistor turns on, impacts leakage current I I d / µ (W /L) C g C d I µ n >µ p =) R N,eff < R P,eff I C g / (W L) I C d / W Width I " W = # R eff = " I d = " C d, C g I " L = " R eff = # I d = " C g Length ECE 5745 T02: CMOS Devices 8 / 33
11 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Agenda Simple Transistor RC Model Simple Wire RC Model CMOS Fabrication ECE 5745 T02: CMOS Devices 9 / 33
12 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Wire Resistance Height Length resistance length resistivity height width Width bulk aluminum 2.8x10-8 -m bulk copper 1.7x10-8 -m bulk silver 1.6x10-8 -m Thickness fixed in given manufacturing process Resistances quoted as /square TSMC 0.18 m 6 Aluminum metal layers M /square (0.5 m x 1mm wire = 160 ) M /square (0.5 m x 1mm wire = 60 ) R sq = resistivity / height resistance = R sq ( length / width ) Adapted from [Terman 02] ECE 5745 T02: CMOS Devices 10 / 33
13 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Wire Capacitance 2 H2 12 W2 D12 1 H1 D1 W1 S1 DD1 Capacitance depends on geometry of surrounding wires and relative permittivity, r,of dielectric silicon dioxide, SiO 2 r = 3.9 silicon flouride, SiOF r = 3.1 SiLK TM polymer, r = 2.6 Can have different materials between wires and between Adapted from [Terman 02] ECE 5745 T02: CMOS Devices 11 / 33
14 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Key Qualitative Characteristics of Wires R driver R 1 R 2 R N C load C 1 C 2 C N Because both wire resistance and wire capacitance increase with length, wire delay grows quadratically with length R driver R w C w /2 C w /2 C load ECE 5745 T02: CMOS Devices 12 / 33
15 Agenda Simple Transistor RC Model Simple Wire RC Model CMOS Fabrication ECE 5745 T02: CMOS Devices 13 / 33
16 Mask Set for NMOS Transistor (circa 1986) Vd = 1V I na n+ Vg = 0V dielectric p- Vs = 0V n+ Masks #1: n+ diffusion #2: poly (gate) #3: diff contact #4: metal Top-down view: Layers to do p-fet not shown. Modern processes have 6 to 10 metal layers (or more) (in 1986: 2). 38 Adapted from [Asanovic 11] ECE 5745 T02: CMOS Devices 14 / 33
17 Design Rules for Masks (circa 1986) Poly overhang. So that if masks are misaligned, channel doesn t short out. Minimum gate length. So that the source and drain depletion regions do not meet! length Metal rules: Contact separation from channel, one fixed contact size, overlap rules with metal, etc... #1: n+ diffusion #3: diff contact #2: poly (gate) #4: metal Adapted from [Asanovic 11] ECE 5745 T02: CMOS Devices 15 / 33
18 Start With an Un-Doped Wafer UV hardens exposed resist. A wafer wash leaves only hard resist. oxide p- Steps #1: dope wafer p- #2: grow gate oxide #3: deposit undoped polysilicon #4: spin on photoresist #5: place positive poly mask and expose with UV. Adapted from [Asanovic 11] ECE 5745 T02: CMOS Devices 16 / 33
19 Wet Etch to Remove Unmasked Regions HF acid etches through poly and oxide, but not hardened resist. oxide p- oxide p- After etch and resist removal Adapted from [Asanovic 11] ECE 5745 T02: CMOS Devices 17 / 33
20 Use Diffusion Mask to Implant N-Type accelerated donor atoms oxide n+ n+ p- Notice how donor atoms are blocked by gate and do not enter channel. Thus, the channel is self-aligned, precise mask alignment is not needed! Adapted from [Asanovic 11] ECE 5745 T02: CMOS Devices 18 / 33
21 Metallization Completes Device oxide n+ n+ p- Grow a thick oxide on top of the wafer. oxide n+ n+ p- oxide n+ n+ p- Mask and etch to make contact holes Put a layer of metal on chip. Be sure to fill in the holes! Adapted from [Asanovic 11] ECE 5745 T02: CMOS Devices 19 / 33
22 Final NMOS Transistor Vd Vs The planar process Top-down view: oxide n+ n+ p- Jean Hoerni, Fairchild Semiconductor Adapted from [Asanovic 11] ECE 5745 T02: CMOS Devices 20 / 33
23 PMOS Transistor is Dual of NMOS Transistor V well = Vs = 1V I μa p+ Vg = 0V dielectric n-well p- Vd = 0V p+ Vg Vs Isd Vd New n-well mask Mobility of holes is slower than electrons. p-fets drive less current than n- Fets, all else being equal Lecture 02, Introduction 1 Adapted from [Asanovic 11] ECE 5745 T02: CMOS Devices 21 / 33
24 Single- and Triple-Well Processes Adapted from [Weste 11] ECE 5745 T02: CMOS Devices 22 / 33
25 Local Interconnect IBM 6-Transistor SRAM Cell Adapted from [Weste 11] ECE 5745 T02: CMOS Devices 23 / 33
26 Intel Metal Stacks: 90nm and 45nm Adapted from [Weste 11] ECE 5745 T02: CMOS Devices 24 / 33
27 Intel Metal Stacks: 45nm with M9 and I/O Bump ECE 5745 T02: CMOS Devices Adapted from [Weste 11] 25 / 33
28 Intel Metal Layer Dimensions in 45nm Layer t (nm) w (nm) s (nm) pitch (nm) M9 7µm 17.5µm 13µm 30.5µm M M M M M M M M ECE 5745 T02: CMOS Devices 26 / 33 Adapted from [Weste 11]
29 IBM Metal Stacks IBM 11-layer Copper Metal Stack IBM 6-layer Copper Metal Stack Adapted from [Weste 11] ECE 5745 T02: CMOS Devices 27 / 33
30 Bulk vs. Silicon-on-Insulator Processing I Eliminates parasitic capacitance between source/drain and the body! lower energy, higher performance I Lower subthreshold leakage, but threshold voltage varies over time I 10 15% increase in total manufacturing cost due to substrate cost Adapted from [Asanovic 11,Weste 11] ECE 5745 T02: CMOS Devices 28 / 33
31 Lithography SEM of Mask I Resolution of patterns far exceeds wavelength of light used for exposure which is usually 193 nm generated with an argon fluoride laser desired (drawn) modified mask exposure I Sophisticated tricks used to pattern µm features including immersion lithography, optical proximity correction, double patterning ECE 5745 T02: CMOS Devices 29 / 33 Adapted from [Asanovic 11,Weste 11]
32 Processing Enhancements I High-K Dieletrics and Metal Gates Replacing silicon dioxide gate dielectric with a high-k material allows increased vertical electric field without increasing gate leakage I Strained Silicon Layer of silicon in which silicon atoms are stretched beyond their normal interatomic distance leading to better mobility I Gate Engineering Multiple transistor designs with different threshold voltages to allow optimization of delay or power Adapted from [Asanovic 11,Weste 11] ECE 5745 T02: CMOS Devices 30 / 33
33 FinFET Transistors I Small footprint, but good control of the gate due to using the vertical dimension I Intel is using FinFETs in 22 nm process ECE 5745 T02: CMOS Devices 31 / 33 Adapted from [Weste 11]
34 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Take-Away Points I Although a basic understanding of devices and fabrication is important for understanding technology constraints, mostly in this course we will focus on first-order RC models of CMOS logic, state, and interconnect I In the next topic of this part of the course, we will briefly introduce CMOS circuits using these devices. Combinational Logic: static CMOS, pass-transistor, tri-state buffers. Sequential State: latches, flip-flops I In the next part of the course, we will explore the details of how to quantitatively evaluate the cycle time, area, and energy of these digital circuits ECE 5745 T02: CMOS Devices 32 / 33
35 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Acknowledgments I [Weste 11] N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed, Addison Wesley, I [Terman 02] C. Terman and K. Asanović, CMOS Technology, and Wires, MIT Introduction to VLSI Systems, Lectures, I [Asanovic 11] K. Asanović, J. Wawrzynek, and J. Lazzaro, Introduction, UC Berkeley CS 250 VLSI Systems Design, Lecture, ECE 5745 T02: CMOS Devices 33 / 33
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